1/* 2 * Copyright (C) 2003 Rick Bronson 3 * 4 * Derived from drivers/mtd/nand/autcpu12.c 5 * Copyright (c) 2001 Thomas Gleixner (gleixner@autronix.de) 6 * 7 * Derived from drivers/mtd/spia.c 8 * Copyright (C) 2000 Steven J. Hill (sjhill@cotw.com) 9 * 10 * 11 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263 12 * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright (C) 2007 13 * 14 * Derived from Das U-Boot source code 15 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c) 16 * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas 17 * 18 * 19 * This program is free software; you can redistribute it and/or modify 20 * it under the terms of the GNU General Public License version 2 as 21 * published by the Free Software Foundation. 22 * 23 */ 24 25#include <linux/slab.h> 26#include <linux/module.h> 27#include <linux/moduleparam.h> 28#include <linux/platform_device.h> 29#include <linux/mtd/mtd.h> 30#include <linux/mtd/nand.h> 31#include <linux/mtd/partitions.h> 32 33#include <linux/gpio.h> 34#include <linux/io.h> 35 36#include <mach/board.h> 37#include <mach/cpu.h> 38 39#ifdef CONFIG_MTD_NAND_ATMEL_ECC_HW 40#define hard_ecc 1 41#else 42#define hard_ecc 0 43#endif 44 45#ifdef CONFIG_MTD_NAND_ATMEL_ECC_NONE 46#define no_ecc 1 47#else 48#define no_ecc 0 49#endif 50 51static int on_flash_bbt = 0; 52module_param(on_flash_bbt, int, 0); 53 54/* Register access macros */ 55#define ecc_readl(add, reg) \ 56 __raw_readl(add + ATMEL_ECC_##reg) 57#define ecc_writel(add, reg, value) \ 58 __raw_writel((value), add + ATMEL_ECC_##reg) 59 60#include "atmel_nand_ecc.h" /* Hardware ECC registers */ 61 62/* oob layout for large page size 63 * bad block info is on bytes 0 and 1 64 * the bytes have to be consecutives to avoid 65 * several NAND_CMD_RNDOUT during read 66 */ 67static struct nand_ecclayout atmel_oobinfo_large = { 68 .eccbytes = 4, 69 .eccpos = {60, 61, 62, 63}, 70 .oobfree = { 71 {2, 58} 72 }, 73}; 74 75/* oob layout for small page size 76 * bad block info is on bytes 4 and 5 77 * the bytes have to be consecutives to avoid 78 * several NAND_CMD_RNDOUT during read 79 */ 80static struct nand_ecclayout atmel_oobinfo_small = { 81 .eccbytes = 4, 82 .eccpos = {0, 1, 2, 3}, 83 .oobfree = { 84 {6, 10} 85 }, 86}; 87 88struct atmel_nand_host { 89 struct nand_chip nand_chip; 90 struct mtd_info mtd; 91 void __iomem *io_base; 92 struct atmel_nand_data *board; 93 struct device *dev; 94 void __iomem *ecc; 95}; 96 97/* 98 * Enable NAND. 99 */ 100static void atmel_nand_enable(struct atmel_nand_host *host) 101{ 102 if (host->board->enable_pin) 103 gpio_set_value(host->board->enable_pin, 0); 104} 105 106/* 107 * Disable NAND. 108 */ 109static void atmel_nand_disable(struct atmel_nand_host *host) 110{ 111 if (host->board->enable_pin) 112 gpio_set_value(host->board->enable_pin, 1); 113} 114 115/* 116 * Hardware specific access to control-lines 117 */ 118static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) 119{ 120 struct nand_chip *nand_chip = mtd->priv; 121 struct atmel_nand_host *host = nand_chip->priv; 122 123 if (ctrl & NAND_CTRL_CHANGE) { 124 if (ctrl & NAND_NCE) 125 atmel_nand_enable(host); 126 else 127 atmel_nand_disable(host); 128 } 129 if (cmd == NAND_CMD_NONE) 130 return; 131 132 if (ctrl & NAND_CLE) 133 writeb(cmd, host->io_base + (1 << host->board->cle)); 134 else 135 writeb(cmd, host->io_base + (1 << host->board->ale)); 136} 137 138/* 139 * Read the Device Ready pin. 140 */ 141static int atmel_nand_device_ready(struct mtd_info *mtd) 142{ 143 struct nand_chip *nand_chip = mtd->priv; 144 struct atmel_nand_host *host = nand_chip->priv; 145 146 return gpio_get_value(host->board->rdy_pin) ^ 147 !!host->board->rdy_pin_active_low; 148} 149 150/* 151 * Minimal-overhead PIO for data access. 152 */ 153static void atmel_read_buf(struct mtd_info *mtd, u8 *buf, int len) 154{ 155 struct nand_chip *nand_chip = mtd->priv; 156 157 __raw_readsb(nand_chip->IO_ADDR_R, buf, len); 158} 159 160static void atmel_read_buf16(struct mtd_info *mtd, u8 *buf, int len) 161{ 162 struct nand_chip *nand_chip = mtd->priv; 163 164 __raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2); 165} 166 167static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len) 168{ 169 struct nand_chip *nand_chip = mtd->priv; 170 171 __raw_writesb(nand_chip->IO_ADDR_W, buf, len); 172} 173 174static void atmel_write_buf16(struct mtd_info *mtd, const u8 *buf, int len) 175{ 176 struct nand_chip *nand_chip = mtd->priv; 177 178 __raw_writesw(nand_chip->IO_ADDR_W, buf, len / 2); 179} 180 181/* 182 * Calculate HW ECC 183 * 184 * function called after a write 185 * 186 * mtd: MTD block structure 187 * dat: raw data (unused) 188 * ecc_code: buffer for ECC 189 */ 190static int atmel_nand_calculate(struct mtd_info *mtd, 191 const u_char *dat, unsigned char *ecc_code) 192{ 193 struct nand_chip *nand_chip = mtd->priv; 194 struct atmel_nand_host *host = nand_chip->priv; 195 unsigned int ecc_value; 196 197 /* get the first 2 ECC bytes */ 198 ecc_value = ecc_readl(host->ecc, PR); 199 200 ecc_code[0] = ecc_value & 0xFF; 201 ecc_code[1] = (ecc_value >> 8) & 0xFF; 202 203 /* get the last 2 ECC bytes */ 204 ecc_value = ecc_readl(host->ecc, NPR) & ATMEL_ECC_NPARITY; 205 206 ecc_code[2] = ecc_value & 0xFF; 207 ecc_code[3] = (ecc_value >> 8) & 0xFF; 208 209 return 0; 210} 211 212/* 213 * HW ECC read page function 214 * 215 * mtd: mtd info structure 216 * chip: nand chip info structure 217 * buf: buffer to store read data 218 */ 219static int atmel_nand_read_page(struct mtd_info *mtd, 220 struct nand_chip *chip, uint8_t *buf, int page) 221{ 222 int eccsize = chip->ecc.size; 223 int eccbytes = chip->ecc.bytes; 224 uint32_t *eccpos = chip->ecc.layout->eccpos; 225 uint8_t *p = buf; 226 uint8_t *oob = chip->oob_poi; 227 uint8_t *ecc_pos; 228 int stat; 229 230 if (cpu_is_at32ap7000()) { 231 struct atmel_nand_host *host = chip->priv; 232 ecc_writel(host->ecc, CR, ATMEL_ECC_RST); 233 } 234 235 /* read the page */ 236 chip->read_buf(mtd, p, eccsize); 237 238 /* move to ECC position if needed */ 239 if (eccpos[0] != 0) { 240 /* This only works on large pages 241 * because the ECC controller waits for 242 * NAND_CMD_RNDOUTSTART after the 243 * NAND_CMD_RNDOUT. 244 * anyway, for small pages, the eccpos[0] == 0 245 */ 246 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, 247 mtd->writesize + eccpos[0], -1); 248 } 249 250 /* the ECC controller needs to read the ECC just after the data */ 251 ecc_pos = oob + eccpos[0]; 252 chip->read_buf(mtd, ecc_pos, eccbytes); 253 254 /* check if there's an error */ 255 stat = chip->ecc.correct(mtd, p, oob, NULL); 256 257 if (stat < 0) 258 mtd->ecc_stats.failed++; 259 else 260 mtd->ecc_stats.corrected += stat; 261 262 /* get back to oob start (end of page) */ 263 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1); 264 265 /* read the oob */ 266 chip->read_buf(mtd, oob, mtd->oobsize); 267 268 return 0; 269} 270 271/* 272 * HW ECC Correction 273 * 274 * function called after a read 275 * 276 * mtd: MTD block structure 277 * dat: raw data read from the chip 278 * read_ecc: ECC from the chip (unused) 279 * isnull: unused 280 * 281 * Detect and correct a 1 bit error for a page 282 */ 283static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat, 284 u_char *read_ecc, u_char *isnull) 285{ 286 struct nand_chip *nand_chip = mtd->priv; 287 struct atmel_nand_host *host = nand_chip->priv; 288 unsigned int ecc_status; 289 unsigned int ecc_word, ecc_bit; 290 291 /* get the status from the Status Register */ 292 ecc_status = ecc_readl(host->ecc, SR); 293 294 /* if there's no error */ 295 if (likely(!(ecc_status & ATMEL_ECC_RECERR))) 296 return 0; 297 298 /* get error bit offset (4 bits) */ 299 ecc_bit = ecc_readl(host->ecc, PR) & ATMEL_ECC_BITADDR; 300 /* get word address (12 bits) */ 301 ecc_word = ecc_readl(host->ecc, PR) & ATMEL_ECC_WORDADDR; 302 ecc_word >>= 4; 303 304 /* if there are multiple errors */ 305 if (ecc_status & ATMEL_ECC_MULERR) { 306 /* check if it is a freshly erased block 307 * (filled with 0xff) */ 308 if ((ecc_bit == ATMEL_ECC_BITADDR) 309 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) { 310 /* the block has just been erased, return OK */ 311 return 0; 312 } 313 /* it doesn't seems to be a freshly 314 * erased block. 315 * We can't correct so many errors */ 316 dev_dbg(host->dev, "atmel_nand : multiple errors detected." 317 " Unable to correct.\n"); 318 return -EIO; 319 } 320 321 /* if there's a single bit error : we can correct it */ 322 if (ecc_status & ATMEL_ECC_ECCERR) { 323 /* there's nothing much to do here. 324 * the bit error is on the ECC itself. 325 */ 326 dev_dbg(host->dev, "atmel_nand : one bit error on ECC code." 327 " Nothing to correct\n"); 328 return 0; 329 } 330 331 dev_dbg(host->dev, "atmel_nand : one bit error on data." 332 " (word offset in the page :" 333 " 0x%x bit offset : 0x%x)\n", 334 ecc_word, ecc_bit); 335 /* correct the error */ 336 if (nand_chip->options & NAND_BUSWIDTH_16) { 337 /* 16 bits words */ 338 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit); 339 } else { 340 /* 8 bits words */ 341 dat[ecc_word] ^= (1 << ecc_bit); 342 } 343 dev_dbg(host->dev, "atmel_nand : error corrected\n"); 344 return 1; 345} 346 347/* 348 * Enable HW ECC : unused on most chips 349 */ 350static void atmel_nand_hwctl(struct mtd_info *mtd, int mode) 351{ 352 if (cpu_is_at32ap7000()) { 353 struct nand_chip *nand_chip = mtd->priv; 354 struct atmel_nand_host *host = nand_chip->priv; 355 ecc_writel(host->ecc, CR, ATMEL_ECC_RST); 356 } 357} 358 359#ifdef CONFIG_MTD_CMDLINE_PARTS 360static const char *part_probes[] = { "cmdlinepart", NULL }; 361#endif 362 363/* 364 * Probe for the NAND device. 365 */ 366static int __init atmel_nand_probe(struct platform_device *pdev) 367{ 368 struct atmel_nand_host *host; 369 struct mtd_info *mtd; 370 struct nand_chip *nand_chip; 371 struct resource *regs; 372 struct resource *mem; 373 int res; 374 375#ifdef CONFIG_MTD_PARTITIONS 376 struct mtd_partition *partitions = NULL; 377 int num_partitions = 0; 378#endif 379 380 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 381 if (!mem) { 382 printk(KERN_ERR "atmel_nand: can't get I/O resource mem\n"); 383 return -ENXIO; 384 } 385 386 /* Allocate memory for the device structure (and zero it) */ 387 host = kzalloc(sizeof(struct atmel_nand_host), GFP_KERNEL); 388 if (!host) { 389 printk(KERN_ERR "atmel_nand: failed to allocate device structure.\n"); 390 return -ENOMEM; 391 } 392 393 host->io_base = ioremap(mem->start, mem->end - mem->start + 1); 394 if (host->io_base == NULL) { 395 printk(KERN_ERR "atmel_nand: ioremap failed\n"); 396 res = -EIO; 397 goto err_nand_ioremap; 398 } 399 400 mtd = &host->mtd; 401 nand_chip = &host->nand_chip; 402 host->board = pdev->dev.platform_data; 403 host->dev = &pdev->dev; 404 405 nand_chip->priv = host; /* link the private data structures */ 406 mtd->priv = nand_chip; 407 mtd->owner = THIS_MODULE; 408 409 /* Set address of NAND IO lines */ 410 nand_chip->IO_ADDR_R = host->io_base; 411 nand_chip->IO_ADDR_W = host->io_base; 412 nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl; 413 414 if (host->board->rdy_pin) 415 nand_chip->dev_ready = atmel_nand_device_ready; 416 417 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1); 418 if (!regs && hard_ecc) { 419 printk(KERN_ERR "atmel_nand: can't get I/O resource " 420 "regs\nFalling back on software ECC\n"); 421 } 422 423 nand_chip->ecc.mode = NAND_ECC_SOFT; /* enable ECC */ 424 if (no_ecc) 425 nand_chip->ecc.mode = NAND_ECC_NONE; 426 if (hard_ecc && regs) { 427 host->ecc = ioremap(regs->start, regs->end - regs->start + 1); 428 if (host->ecc == NULL) { 429 printk(KERN_ERR "atmel_nand: ioremap failed\n"); 430 res = -EIO; 431 goto err_ecc_ioremap; 432 } 433 nand_chip->ecc.mode = NAND_ECC_HW; 434 nand_chip->ecc.calculate = atmel_nand_calculate; 435 nand_chip->ecc.correct = atmel_nand_correct; 436 nand_chip->ecc.hwctl = atmel_nand_hwctl; 437 nand_chip->ecc.read_page = atmel_nand_read_page; 438 nand_chip->ecc.bytes = 4; 439 } 440 441 nand_chip->chip_delay = 20; /* 20us command delay time */ 442 443 if (host->board->bus_width_16) { /* 16-bit bus width */ 444 nand_chip->options |= NAND_BUSWIDTH_16; 445 nand_chip->read_buf = atmel_read_buf16; 446 nand_chip->write_buf = atmel_write_buf16; 447 } else { 448 nand_chip->read_buf = atmel_read_buf; 449 nand_chip->write_buf = atmel_write_buf; 450 } 451 452 platform_set_drvdata(pdev, host); 453 atmel_nand_enable(host); 454 455 if (host->board->det_pin) { 456 if (gpio_get_value(host->board->det_pin)) { 457 printk(KERN_INFO "No SmartMedia card inserted.\n"); 458 res = -ENXIO; 459 goto err_no_card; 460 } 461 } 462 463 if (on_flash_bbt) { 464 printk(KERN_INFO "atmel_nand: Use On Flash BBT\n"); 465 nand_chip->options |= NAND_USE_FLASH_BBT; 466 } 467 468 /* first scan to find the device and get the page size */ 469 if (nand_scan_ident(mtd, 1, NULL)) { 470 res = -ENXIO; 471 goto err_scan_ident; 472 } 473 474 if (nand_chip->ecc.mode == NAND_ECC_HW) { 475 /* ECC is calculated for the whole page (1 step) */ 476 nand_chip->ecc.size = mtd->writesize; 477 478 /* set ECC page size and oob layout */ 479 switch (mtd->writesize) { 480 case 512: 481 nand_chip->ecc.layout = &atmel_oobinfo_small; 482 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528); 483 break; 484 case 1024: 485 nand_chip->ecc.layout = &atmel_oobinfo_large; 486 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056); 487 break; 488 case 2048: 489 nand_chip->ecc.layout = &atmel_oobinfo_large; 490 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112); 491 break; 492 case 4096: 493 nand_chip->ecc.layout = &atmel_oobinfo_large; 494 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224); 495 break; 496 default: 497 /* page size not handled by HW ECC */ 498 /* switching back to soft ECC */ 499 nand_chip->ecc.mode = NAND_ECC_SOFT; 500 nand_chip->ecc.calculate = NULL; 501 nand_chip->ecc.correct = NULL; 502 nand_chip->ecc.hwctl = NULL; 503 nand_chip->ecc.read_page = NULL; 504 nand_chip->ecc.postpad = 0; 505 nand_chip->ecc.prepad = 0; 506 nand_chip->ecc.bytes = 0; 507 break; 508 } 509 } 510 511 /* second phase scan */ 512 if (nand_scan_tail(mtd)) { 513 res = -ENXIO; 514 goto err_scan_tail; 515 } 516 517#ifdef CONFIG_MTD_PARTITIONS 518#ifdef CONFIG_MTD_CMDLINE_PARTS 519 mtd->name = "atmel_nand"; 520 num_partitions = parse_mtd_partitions(mtd, part_probes, 521 &partitions, 0); 522#endif 523 if (num_partitions <= 0 && host->board->partition_info) 524 partitions = host->board->partition_info(mtd->size, 525 &num_partitions); 526 527 if ((!partitions) || (num_partitions == 0)) { 528 printk(KERN_ERR "atmel_nand: No partitions defined, or unsupported device.\n"); 529 res = -ENXIO; 530 goto err_no_partitions; 531 } 532 533 res = add_mtd_partitions(mtd, partitions, num_partitions); 534#else 535 res = add_mtd_device(mtd); 536#endif 537 538 if (!res) 539 return res; 540 541#ifdef CONFIG_MTD_PARTITIONS 542err_no_partitions: 543#endif 544 nand_release(mtd); 545err_scan_tail: 546err_scan_ident: 547err_no_card: 548 atmel_nand_disable(host); 549 platform_set_drvdata(pdev, NULL); 550 if (host->ecc) 551 iounmap(host->ecc); 552err_ecc_ioremap: 553 iounmap(host->io_base); 554err_nand_ioremap: 555 kfree(host); 556 return res; 557} 558 559/* 560 * Remove a NAND device. 561 */ 562static int __exit atmel_nand_remove(struct platform_device *pdev) 563{ 564 struct atmel_nand_host *host = platform_get_drvdata(pdev); 565 struct mtd_info *mtd = &host->mtd; 566 567 nand_release(mtd); 568 569 atmel_nand_disable(host); 570 571 if (host->ecc) 572 iounmap(host->ecc); 573 iounmap(host->io_base); 574 kfree(host); 575 576 return 0; 577} 578 579static struct platform_driver atmel_nand_driver = { 580 .remove = __exit_p(atmel_nand_remove), 581 .driver = { 582 .name = "atmel_nand", 583 .owner = THIS_MODULE, 584 }, 585}; 586 587static int __init atmel_nand_init(void) 588{ 589 return platform_driver_probe(&atmel_nand_driver, atmel_nand_probe); 590} 591 592 593static void __exit atmel_nand_exit(void) 594{ 595 platform_driver_unregister(&atmel_nand_driver); 596} 597 598 599module_init(atmel_nand_init); 600module_exit(atmel_nand_exit); 601 602MODULE_LICENSE("GPL"); 603MODULE_AUTHOR("Rick Bronson"); 604MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91 / AVR32"); 605MODULE_ALIAS("platform:atmel_nand"); 606