1/* 2 * linux/drivers/mmc/host/at91_mci.c - ATMEL AT91 MCI Driver 3 * 4 * Copyright (C) 2005 Cougar Creek Computing Devices Ltd, All Rights Reserved 5 * 6 * Copyright (C) 2006 Malcolm Noyes 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13/* 14 This is the AT91 MCI driver that has been tested with both MMC cards 15 and SD-cards. Boards that support write protect are now supported. 16 The CCAT91SBC001 board does not support SD cards. 17 18 The three entry points are at91_mci_request, at91_mci_set_ios 19 and at91_mci_get_ro. 20 21 SET IOS 22 This configures the device to put it into the correct mode and clock speed 23 required. 24 25 MCI REQUEST 26 MCI request processes the commands sent in the mmc_request structure. This 27 can consist of a processing command and a stop command in the case of 28 multiple block transfers. 29 30 There are three main types of request, commands, reads and writes. 31 32 Commands are straight forward. The command is submitted to the controller and 33 the request function returns. When the controller generates an interrupt to indicate 34 the command is finished, the response to the command are read and the mmc_request_done 35 function called to end the request. 36 37 Reads and writes work in a similar manner to normal commands but involve the PDC (DMA) 38 controller to manage the transfers. 39 40 A read is done from the controller directly to the scatterlist passed in from the request. 41 Due to a bug in the AT91RM9200 controller, when a read is completed, all the words are byte 42 swapped in the scatterlist buffers. AT91SAM926x are not affected by this bug. 43 44 The sequence of read interrupts is: ENDRX, RXBUFF, CMDRDY 45 46 A write is slightly different in that the bytes to write are read from the scatterlist 47 into a dma memory buffer (this is in case the source buffer should be read only). The 48 entire write buffer is then done from this single dma memory buffer. 49 50 The sequence of write interrupts is: ENDTX, TXBUFE, NOTBUSY, CMDRDY 51 52 GET RO 53 Gets the status of the write protect pin, if available. 54*/ 55 56#include <linux/module.h> 57#include <linux/moduleparam.h> 58#include <linux/init.h> 59#include <linux/ioport.h> 60#include <linux/platform_device.h> 61#include <linux/interrupt.h> 62#include <linux/blkdev.h> 63#include <linux/delay.h> 64#include <linux/err.h> 65#include <linux/dma-mapping.h> 66#include <linux/clk.h> 67#include <linux/atmel_pdc.h> 68#include <linux/gfp.h> 69#include <linux/highmem.h> 70 71#include <linux/mmc/host.h> 72#include <linux/mmc/sdio.h> 73 74#include <asm/io.h> 75#include <asm/irq.h> 76#include <asm/gpio.h> 77 78#include <mach/board.h> 79#include <mach/cpu.h> 80#include <mach/at91_mci.h> 81 82#define DRIVER_NAME "at91_mci" 83 84static inline int at91mci_is_mci1rev2xx(void) 85{ 86 return ( cpu_is_at91sam9260() 87 || cpu_is_at91sam9263() 88 || cpu_is_at91cap9() 89 || cpu_is_at91sam9rl() 90 || cpu_is_at91sam9g10() 91 || cpu_is_at91sam9g20() 92 ); 93} 94 95#define FL_SENT_COMMAND (1 << 0) 96#define FL_SENT_STOP (1 << 1) 97 98#define AT91_MCI_ERRORS (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE \ 99 | AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE \ 100 | AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE) 101 102#define at91_mci_read(host, reg) __raw_readl((host)->baseaddr + (reg)) 103#define at91_mci_write(host, reg, val) __raw_writel((val), (host)->baseaddr + (reg)) 104 105#define MCI_BLKSIZE 512 106#define MCI_MAXBLKSIZE 4095 107#define MCI_BLKATONCE 256 108#define MCI_BUFSIZE (MCI_BLKSIZE * MCI_BLKATONCE) 109 110/* 111 * Low level type for this driver 112 */ 113struct at91mci_host 114{ 115 struct mmc_host *mmc; 116 struct mmc_command *cmd; 117 struct mmc_request *request; 118 119 void __iomem *baseaddr; 120 int irq; 121 122 struct at91_mmc_data *board; 123 int present; 124 125 struct clk *mci_clk; 126 127 /* 128 * Flag indicating when the command has been sent. This is used to 129 * work out whether or not to send the stop 130 */ 131 unsigned int flags; 132 /* flag for current bus settings */ 133 u32 bus_mode; 134 135 /* DMA buffer used for transmitting */ 136 unsigned int* buffer; 137 dma_addr_t physical_address; 138 unsigned int total_length; 139 140 /* Latest in the scatterlist that has been enabled for transfer, but not freed */ 141 int in_use_index; 142 143 /* Latest in the scatterlist that has been enabled for transfer */ 144 int transfer_index; 145 146 /* Timer for timeouts */ 147 struct timer_list timer; 148}; 149 150/* 151 * Reset the controller and restore most of the state 152 */ 153static void at91_reset_host(struct at91mci_host *host) 154{ 155 unsigned long flags; 156 u32 mr; 157 u32 sdcr; 158 u32 dtor; 159 u32 imr; 160 161 local_irq_save(flags); 162 imr = at91_mci_read(host, AT91_MCI_IMR); 163 164 at91_mci_write(host, AT91_MCI_IDR, 0xffffffff); 165 166 /* save current state */ 167 mr = at91_mci_read(host, AT91_MCI_MR) & 0x7fff; 168 sdcr = at91_mci_read(host, AT91_MCI_SDCR); 169 dtor = at91_mci_read(host, AT91_MCI_DTOR); 170 171 /* reset the controller */ 172 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST); 173 174 /* restore state */ 175 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN); 176 at91_mci_write(host, AT91_MCI_MR, mr); 177 at91_mci_write(host, AT91_MCI_SDCR, sdcr); 178 at91_mci_write(host, AT91_MCI_DTOR, dtor); 179 at91_mci_write(host, AT91_MCI_IER, imr); 180 181 /* make sure sdio interrupts will fire */ 182 at91_mci_read(host, AT91_MCI_SR); 183 184 local_irq_restore(flags); 185} 186 187static void at91_timeout_timer(unsigned long data) 188{ 189 struct at91mci_host *host; 190 191 host = (struct at91mci_host *)data; 192 193 if (host->request) { 194 dev_err(host->mmc->parent, "Timeout waiting end of packet\n"); 195 196 if (host->cmd && host->cmd->data) { 197 host->cmd->data->error = -ETIMEDOUT; 198 } else { 199 if (host->cmd) 200 host->cmd->error = -ETIMEDOUT; 201 else 202 host->request->cmd->error = -ETIMEDOUT; 203 } 204 205 at91_reset_host(host); 206 mmc_request_done(host->mmc, host->request); 207 } 208} 209 210/* 211 * Copy from sg to a dma block - used for transfers 212 */ 213static inline void at91_mci_sg_to_dma(struct at91mci_host *host, struct mmc_data *data) 214{ 215 unsigned int len, i, size; 216 unsigned *dmabuf = host->buffer; 217 218 size = data->blksz * data->blocks; 219 len = data->sg_len; 220 221 /* MCI1 rev2xx Data Write Operation and number of bytes erratum */ 222 if (at91mci_is_mci1rev2xx()) 223 if (host->total_length == 12) 224 memset(dmabuf, 0, 12); 225 226 /* 227 * Just loop through all entries. Size might not 228 * be the entire list though so make sure that 229 * we do not transfer too much. 230 */ 231 for (i = 0; i < len; i++) { 232 struct scatterlist *sg; 233 int amount; 234 unsigned int *sgbuffer; 235 236 sg = &data->sg[i]; 237 238 sgbuffer = kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset; 239 amount = min(size, sg->length); 240 size -= amount; 241 242 if (cpu_is_at91rm9200()) { /* AT91RM9200 errata */ 243 int index; 244 245 for (index = 0; index < (amount / 4); index++) 246 *dmabuf++ = swab32(sgbuffer[index]); 247 } else { 248 char *tmpv = (char *)dmabuf; 249 memcpy(tmpv, sgbuffer, amount); 250 tmpv += amount; 251 dmabuf = (unsigned *)tmpv; 252 } 253 254 kunmap_atomic(sgbuffer, KM_BIO_SRC_IRQ); 255 256 if (size == 0) 257 break; 258 } 259 260 /* 261 * Check that we didn't get a request to transfer 262 * more data than can fit into the SG list. 263 */ 264 BUG_ON(size != 0); 265} 266 267/* 268 * Handle after a dma read 269 */ 270static void at91_mci_post_dma_read(struct at91mci_host *host) 271{ 272 struct mmc_command *cmd; 273 struct mmc_data *data; 274 unsigned int len, i, size; 275 unsigned *dmabuf = host->buffer; 276 277 pr_debug("post dma read\n"); 278 279 cmd = host->cmd; 280 if (!cmd) { 281 pr_debug("no command\n"); 282 return; 283 } 284 285 data = cmd->data; 286 if (!data) { 287 pr_debug("no data\n"); 288 return; 289 } 290 291 size = data->blksz * data->blocks; 292 len = data->sg_len; 293 294 at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_ENDRX); 295 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_RXBUFF); 296 297 for (i = 0; i < len; i++) { 298 struct scatterlist *sg; 299 int amount; 300 unsigned int *sgbuffer; 301 302 sg = &data->sg[i]; 303 304 sgbuffer = kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset; 305 amount = min(size, sg->length); 306 size -= amount; 307 308 if (cpu_is_at91rm9200()) { /* AT91RM9200 errata */ 309 int index; 310 for (index = 0; index < (amount / 4); index++) 311 sgbuffer[index] = swab32(*dmabuf++); 312 } else { 313 char *tmpv = (char *)dmabuf; 314 memcpy(sgbuffer, tmpv, amount); 315 tmpv += amount; 316 dmabuf = (unsigned *)tmpv; 317 } 318 319 flush_kernel_dcache_page(sg_page(sg)); 320 kunmap_atomic(sgbuffer, KM_BIO_SRC_IRQ); 321 data->bytes_xfered += amount; 322 if (size == 0) 323 break; 324 } 325 326 pr_debug("post dma read done\n"); 327} 328 329/* 330 * Handle transmitted data 331 */ 332static void at91_mci_handle_transmitted(struct at91mci_host *host) 333{ 334 struct mmc_command *cmd; 335 struct mmc_data *data; 336 337 pr_debug("Handling the transmit\n"); 338 339 /* Disable the transfer */ 340 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); 341 342 /* Now wait for cmd ready */ 343 at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_TXBUFE); 344 345 cmd = host->cmd; 346 if (!cmd) return; 347 348 data = cmd->data; 349 if (!data) return; 350 351 if (cmd->data->blocks > 1) { 352 pr_debug("multiple write : wait for BLKE...\n"); 353 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_BLKE); 354 } else 355 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY); 356} 357 358/* 359 * Update bytes tranfered count during a write operation 360 */ 361static void at91_mci_update_bytes_xfered(struct at91mci_host *host) 362{ 363 struct mmc_data *data; 364 365 /* always deal with the effective request (and not the current cmd) */ 366 367 if (host->request->cmd && host->request->cmd->error != 0) 368 return; 369 370 if (host->request->data) { 371 data = host->request->data; 372 if (data->flags & MMC_DATA_WRITE) { 373 /* card is in IDLE mode now */ 374 pr_debug("-> bytes_xfered %d, total_length = %d\n", 375 data->bytes_xfered, host->total_length); 376 data->bytes_xfered = data->blksz * data->blocks; 377 } 378 } 379} 380 381 382/*Handle after command sent ready*/ 383static int at91_mci_handle_cmdrdy(struct at91mci_host *host) 384{ 385 if (!host->cmd) 386 return 1; 387 else if (!host->cmd->data) { 388 if (host->flags & FL_SENT_STOP) { 389 /*After multi block write, we must wait for NOTBUSY*/ 390 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY); 391 } else return 1; 392 } else if (host->cmd->data->flags & MMC_DATA_WRITE) { 393 /*After sendding multi-block-write command, start DMA transfer*/ 394 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_TXBUFE | AT91_MCI_BLKE); 395 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN); 396 } 397 398 /* command not completed, have to wait */ 399 return 0; 400} 401 402 403/* 404 * Enable the controller 405 */ 406static void at91_mci_enable(struct at91mci_host *host) 407{ 408 unsigned int mr; 409 410 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN); 411 at91_mci_write(host, AT91_MCI_IDR, 0xffffffff); 412 at91_mci_write(host, AT91_MCI_DTOR, AT91_MCI_DTOMUL_1M | AT91_MCI_DTOCYC); 413 mr = AT91_MCI_PDCMODE | 0x34a; 414 415 if (at91mci_is_mci1rev2xx()) 416 mr |= AT91_MCI_RDPROOF | AT91_MCI_WRPROOF; 417 418 at91_mci_write(host, AT91_MCI_MR, mr); 419 420 /* use Slot A or B (only one at same time) */ 421 at91_mci_write(host, AT91_MCI_SDCR, host->board->slot_b); 422} 423 424/* 425 * Disable the controller 426 */ 427static void at91_mci_disable(struct at91mci_host *host) 428{ 429 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST); 430} 431 432/* 433 * Send a command 434 */ 435static void at91_mci_send_command(struct at91mci_host *host, struct mmc_command *cmd) 436{ 437 unsigned int cmdr, mr; 438 unsigned int block_length; 439 struct mmc_data *data = cmd->data; 440 441 unsigned int blocks; 442 unsigned int ier = 0; 443 444 host->cmd = cmd; 445 446 /* Needed for leaving busy state before CMD1 */ 447 if ((at91_mci_read(host, AT91_MCI_SR) & AT91_MCI_RTOE) && (cmd->opcode == 1)) { 448 pr_debug("Clearing timeout\n"); 449 at91_mci_write(host, AT91_MCI_ARGR, 0); 450 at91_mci_write(host, AT91_MCI_CMDR, AT91_MCI_OPDCMD); 451 while (!(at91_mci_read(host, AT91_MCI_SR) & AT91_MCI_CMDRDY)) { 452 /* spin */ 453 pr_debug("Clearing: SR = %08X\n", at91_mci_read(host, AT91_MCI_SR)); 454 } 455 } 456 457 cmdr = cmd->opcode; 458 459 if (mmc_resp_type(cmd) == MMC_RSP_NONE) 460 cmdr |= AT91_MCI_RSPTYP_NONE; 461 else { 462 /* if a response is expected then allow maximum response latancy */ 463 cmdr |= AT91_MCI_MAXLAT; 464 /* set 136 bit response for R2, 48 bit response otherwise */ 465 if (mmc_resp_type(cmd) == MMC_RSP_R2) 466 cmdr |= AT91_MCI_RSPTYP_136; 467 else 468 cmdr |= AT91_MCI_RSPTYP_48; 469 } 470 471 if (data) { 472 473 if (cpu_is_at91rm9200() || cpu_is_at91sam9261()) { 474 if (data->blksz & 0x3) { 475 pr_debug("Unsupported block size\n"); 476 cmd->error = -EINVAL; 477 mmc_request_done(host->mmc, host->request); 478 return; 479 } 480 if (data->flags & MMC_DATA_STREAM) { 481 pr_debug("Stream commands not supported\n"); 482 cmd->error = -EINVAL; 483 mmc_request_done(host->mmc, host->request); 484 return; 485 } 486 } 487 488 block_length = data->blksz; 489 blocks = data->blocks; 490 491 /* always set data start - also set direction flag for read */ 492 if (data->flags & MMC_DATA_READ) 493 cmdr |= (AT91_MCI_TRDIR | AT91_MCI_TRCMD_START); 494 else if (data->flags & MMC_DATA_WRITE) 495 cmdr |= AT91_MCI_TRCMD_START; 496 497 if (cmd->opcode == SD_IO_RW_EXTENDED) { 498 cmdr |= AT91_MCI_TRTYP_SDIO_BLOCK; 499 } else { 500 if (data->flags & MMC_DATA_STREAM) 501 cmdr |= AT91_MCI_TRTYP_STREAM; 502 if (data->blocks > 1) 503 cmdr |= AT91_MCI_TRTYP_MULTIPLE; 504 } 505 } 506 else { 507 block_length = 0; 508 blocks = 0; 509 } 510 511 if (host->flags & FL_SENT_STOP) 512 cmdr |= AT91_MCI_TRCMD_STOP; 513 514 if (host->bus_mode == MMC_BUSMODE_OPENDRAIN) 515 cmdr |= AT91_MCI_OPDCMD; 516 517 /* 518 * Set the arguments and send the command 519 */ 520 pr_debug("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08X)\n", 521 cmd->opcode, cmdr, cmd->arg, blocks, block_length, at91_mci_read(host, AT91_MCI_MR)); 522 523 if (!data) { 524 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS | ATMEL_PDC_RXTDIS); 525 at91_mci_write(host, ATMEL_PDC_RPR, 0); 526 at91_mci_write(host, ATMEL_PDC_RCR, 0); 527 at91_mci_write(host, ATMEL_PDC_RNPR, 0); 528 at91_mci_write(host, ATMEL_PDC_RNCR, 0); 529 at91_mci_write(host, ATMEL_PDC_TPR, 0); 530 at91_mci_write(host, ATMEL_PDC_TCR, 0); 531 at91_mci_write(host, ATMEL_PDC_TNPR, 0); 532 at91_mci_write(host, ATMEL_PDC_TNCR, 0); 533 ier = AT91_MCI_CMDRDY; 534 } else { 535 /* zero block length and PDC mode */ 536 mr = at91_mci_read(host, AT91_MCI_MR) & 0x5fff; 537 mr |= (data->blksz & 0x3) ? AT91_MCI_PDCFBYTE : 0; 538 mr |= (block_length << 16); 539 mr |= AT91_MCI_PDCMODE; 540 at91_mci_write(host, AT91_MCI_MR, mr); 541 542 if (!(cpu_is_at91rm9200() || cpu_is_at91sam9261())) 543 at91_mci_write(host, AT91_MCI_BLKR, 544 AT91_MCI_BLKR_BCNT(blocks) | 545 AT91_MCI_BLKR_BLKLEN(block_length)); 546 547 /* 548 * Disable the PDC controller 549 */ 550 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); 551 552 if (cmdr & AT91_MCI_TRCMD_START) { 553 data->bytes_xfered = 0; 554 host->transfer_index = 0; 555 host->in_use_index = 0; 556 if (cmdr & AT91_MCI_TRDIR) { 557 /* 558 * Handle a read 559 */ 560 host->total_length = 0; 561 562 at91_mci_write(host, ATMEL_PDC_RPR, host->physical_address); 563 at91_mci_write(host, ATMEL_PDC_RCR, (data->blksz & 0x3) ? 564 (blocks * block_length) : (blocks * block_length) / 4); 565 at91_mci_write(host, ATMEL_PDC_RNPR, 0); 566 at91_mci_write(host, ATMEL_PDC_RNCR, 0); 567 568 ier = AT91_MCI_ENDRX /* | AT91_MCI_RXBUFF */; 569 } 570 else { 571 /* 572 * Handle a write 573 */ 574 host->total_length = block_length * blocks; 575 /* 576 * MCI1 rev2xx Data Write Operation and 577 * number of bytes erratum 578 */ 579 if (at91mci_is_mci1rev2xx()) 580 if (host->total_length < 12) 581 host->total_length = 12; 582 583 at91_mci_sg_to_dma(host, data); 584 585 pr_debug("Transmitting %d bytes\n", host->total_length); 586 587 at91_mci_write(host, ATMEL_PDC_TPR, host->physical_address); 588 at91_mci_write(host, ATMEL_PDC_TCR, (data->blksz & 0x3) ? 589 host->total_length : host->total_length / 4); 590 591 ier = AT91_MCI_CMDRDY; 592 } 593 } 594 } 595 596 /* 597 * Send the command and then enable the PDC - not the other way round as 598 * the data sheet says 599 */ 600 601 at91_mci_write(host, AT91_MCI_ARGR, cmd->arg); 602 at91_mci_write(host, AT91_MCI_CMDR, cmdr); 603 604 if (cmdr & AT91_MCI_TRCMD_START) { 605 if (cmdr & AT91_MCI_TRDIR) 606 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN); 607 } 608 609 /* Enable selected interrupts */ 610 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_ERRORS | ier); 611} 612 613/* 614 * Process the next step in the request 615 */ 616static void at91_mci_process_next(struct at91mci_host *host) 617{ 618 if (!(host->flags & FL_SENT_COMMAND)) { 619 host->flags |= FL_SENT_COMMAND; 620 at91_mci_send_command(host, host->request->cmd); 621 } 622 else if ((!(host->flags & FL_SENT_STOP)) && host->request->stop) { 623 host->flags |= FL_SENT_STOP; 624 at91_mci_send_command(host, host->request->stop); 625 } else { 626 del_timer(&host->timer); 627 if (cpu_is_at91rm9200()) 628 at91_reset_host(host); 629 mmc_request_done(host->mmc, host->request); 630 } 631} 632 633/* 634 * Handle a command that has been completed 635 */ 636static void at91_mci_completed_command(struct at91mci_host *host, unsigned int status) 637{ 638 struct mmc_command *cmd = host->cmd; 639 struct mmc_data *data = cmd->data; 640 641 at91_mci_write(host, AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB)); 642 643 cmd->resp[0] = at91_mci_read(host, AT91_MCI_RSPR(0)); 644 cmd->resp[1] = at91_mci_read(host, AT91_MCI_RSPR(1)); 645 cmd->resp[2] = at91_mci_read(host, AT91_MCI_RSPR(2)); 646 cmd->resp[3] = at91_mci_read(host, AT91_MCI_RSPR(3)); 647 648 pr_debug("Status = %08X/%08x [%08X %08X %08X %08X]\n", 649 status, at91_mci_read(host, AT91_MCI_SR), 650 cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); 651 652 if (status & AT91_MCI_ERRORS) { 653 if ((status & AT91_MCI_RCRCE) && !(mmc_resp_type(cmd) & MMC_RSP_CRC)) { 654 cmd->error = 0; 655 } 656 else { 657 if (status & (AT91_MCI_DTOE | AT91_MCI_DCRCE)) { 658 if (data) { 659 if (status & AT91_MCI_DTOE) 660 data->error = -ETIMEDOUT; 661 else if (status & AT91_MCI_DCRCE) 662 data->error = -EILSEQ; 663 } 664 } else { 665 if (status & AT91_MCI_RTOE) 666 cmd->error = -ETIMEDOUT; 667 else if (status & AT91_MCI_RCRCE) 668 cmd->error = -EILSEQ; 669 else 670 cmd->error = -EIO; 671 } 672 673 pr_debug("Error detected and set to %d/%d (cmd = %d, retries = %d)\n", 674 cmd->error, data ? data->error : 0, 675 cmd->opcode, cmd->retries); 676 } 677 } 678 else 679 cmd->error = 0; 680 681 at91_mci_process_next(host); 682} 683 684/* 685 * Handle an MMC request 686 */ 687static void at91_mci_request(struct mmc_host *mmc, struct mmc_request *mrq) 688{ 689 struct at91mci_host *host = mmc_priv(mmc); 690 host->request = mrq; 691 host->flags = 0; 692 693 /* more than 1s timeout needed with slow SD cards */ 694 mod_timer(&host->timer, jiffies + msecs_to_jiffies(2000)); 695 696 at91_mci_process_next(host); 697} 698 699/* 700 * Set the IOS 701 */ 702static void at91_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 703{ 704 int clkdiv; 705 struct at91mci_host *host = mmc_priv(mmc); 706 unsigned long at91_master_clock = clk_get_rate(host->mci_clk); 707 708 host->bus_mode = ios->bus_mode; 709 710 if (ios->clock == 0) { 711 /* Disable the MCI controller */ 712 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS); 713 clkdiv = 0; 714 } 715 else { 716 /* Enable the MCI controller */ 717 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN); 718 719 if ((at91_master_clock % (ios->clock * 2)) == 0) 720 clkdiv = ((at91_master_clock / ios->clock) / 2) - 1; 721 else 722 clkdiv = (at91_master_clock / ios->clock) / 2; 723 724 pr_debug("clkdiv = %d. mcck = %ld\n", clkdiv, 725 at91_master_clock / (2 * (clkdiv + 1))); 726 } 727 if (ios->bus_width == MMC_BUS_WIDTH_4 && host->board->wire4) { 728 pr_debug("MMC: Setting controller bus width to 4\n"); 729 at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) | AT91_MCI_SDCBUS); 730 } 731 else { 732 pr_debug("MMC: Setting controller bus width to 1\n"); 733 at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS); 734 } 735 736 /* Set the clock divider */ 737 at91_mci_write(host, AT91_MCI_MR, (at91_mci_read(host, AT91_MCI_MR) & ~AT91_MCI_CLKDIV) | clkdiv); 738 739 /* maybe switch power to the card */ 740 if (host->board->vcc_pin) { 741 switch (ios->power_mode) { 742 case MMC_POWER_OFF: 743 gpio_set_value(host->board->vcc_pin, 0); 744 break; 745 case MMC_POWER_UP: 746 gpio_set_value(host->board->vcc_pin, 1); 747 break; 748 case MMC_POWER_ON: 749 break; 750 default: 751 WARN_ON(1); 752 } 753 } 754} 755 756/* 757 * Handle an interrupt 758 */ 759static irqreturn_t at91_mci_irq(int irq, void *devid) 760{ 761 struct at91mci_host *host = devid; 762 int completed = 0; 763 unsigned int int_status, int_mask; 764 765 int_status = at91_mci_read(host, AT91_MCI_SR); 766 int_mask = at91_mci_read(host, AT91_MCI_IMR); 767 768 pr_debug("MCI irq: status = %08X, %08X, %08X\n", int_status, int_mask, 769 int_status & int_mask); 770 771 int_status = int_status & int_mask; 772 773 if (int_status & AT91_MCI_ERRORS) { 774 completed = 1; 775 776 if (int_status & AT91_MCI_UNRE) 777 pr_debug("MMC: Underrun error\n"); 778 if (int_status & AT91_MCI_OVRE) 779 pr_debug("MMC: Overrun error\n"); 780 if (int_status & AT91_MCI_DTOE) 781 pr_debug("MMC: Data timeout\n"); 782 if (int_status & AT91_MCI_DCRCE) 783 pr_debug("MMC: CRC error in data\n"); 784 if (int_status & AT91_MCI_RTOE) 785 pr_debug("MMC: Response timeout\n"); 786 if (int_status & AT91_MCI_RENDE) 787 pr_debug("MMC: Response end bit error\n"); 788 if (int_status & AT91_MCI_RCRCE) 789 pr_debug("MMC: Response CRC error\n"); 790 if (int_status & AT91_MCI_RDIRE) 791 pr_debug("MMC: Response direction error\n"); 792 if (int_status & AT91_MCI_RINDE) 793 pr_debug("MMC: Response index error\n"); 794 } else { 795 /* Only continue processing if no errors */ 796 797 if (int_status & AT91_MCI_TXBUFE) { 798 pr_debug("TX buffer empty\n"); 799 at91_mci_handle_transmitted(host); 800 } 801 802 if (int_status & AT91_MCI_ENDRX) { 803 pr_debug("ENDRX\n"); 804 at91_mci_post_dma_read(host); 805 } 806 807 if (int_status & AT91_MCI_RXBUFF) { 808 pr_debug("RX buffer full\n"); 809 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); 810 at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_RXBUFF | AT91_MCI_ENDRX); 811 completed = 1; 812 } 813 814 if (int_status & AT91_MCI_ENDTX) 815 pr_debug("Transmit has ended\n"); 816 817 if (int_status & AT91_MCI_NOTBUSY) { 818 pr_debug("Card is ready\n"); 819 at91_mci_update_bytes_xfered(host); 820 completed = 1; 821 } 822 823 if (int_status & AT91_MCI_DTIP) 824 pr_debug("Data transfer in progress\n"); 825 826 if (int_status & AT91_MCI_BLKE) { 827 pr_debug("Block transfer has ended\n"); 828 if (host->request->data && host->request->data->blocks > 1) { 829 /* multi block write : complete multi write 830 * command and send stop */ 831 completed = 1; 832 } else { 833 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY); 834 } 835 } 836 837 if (int_status & AT91_MCI_SDIOIRQA) 838 mmc_signal_sdio_irq(host->mmc); 839 840 if (int_status & AT91_MCI_SDIOIRQB) 841 mmc_signal_sdio_irq(host->mmc); 842 843 if (int_status & AT91_MCI_TXRDY) 844 pr_debug("Ready to transmit\n"); 845 846 if (int_status & AT91_MCI_RXRDY) 847 pr_debug("Ready to receive\n"); 848 849 if (int_status & AT91_MCI_CMDRDY) { 850 pr_debug("Command ready\n"); 851 completed = at91_mci_handle_cmdrdy(host); 852 } 853 } 854 855 if (completed) { 856 pr_debug("Completed command\n"); 857 at91_mci_write(host, AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB)); 858 at91_mci_completed_command(host, int_status); 859 } else 860 at91_mci_write(host, AT91_MCI_IDR, int_status & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB)); 861 862 return IRQ_HANDLED; 863} 864 865static irqreturn_t at91_mmc_det_irq(int irq, void *_host) 866{ 867 struct at91mci_host *host = _host; 868 int present = !gpio_get_value(irq_to_gpio(irq)); 869 870 /* 871 * we expect this irq on both insert and remove, 872 * and use a short delay to debounce. 873 */ 874 if (present != host->present) { 875 host->present = present; 876 pr_debug("%s: card %s\n", mmc_hostname(host->mmc), 877 present ? "insert" : "remove"); 878 if (!present) { 879 pr_debug("****** Resetting SD-card bus width ******\n"); 880 at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS); 881 } 882 /* 0.5s needed because of early card detect switch firing */ 883 mmc_detect_change(host->mmc, msecs_to_jiffies(500)); 884 } 885 return IRQ_HANDLED; 886} 887 888static int at91_mci_get_ro(struct mmc_host *mmc) 889{ 890 struct at91mci_host *host = mmc_priv(mmc); 891 892 if (host->board->wp_pin) 893 return !!gpio_get_value(host->board->wp_pin); 894 /* 895 * Board doesn't support read only detection; let the mmc core 896 * decide what to do. 897 */ 898 return -ENOSYS; 899} 900 901static void at91_mci_enable_sdio_irq(struct mmc_host *mmc, int enable) 902{ 903 struct at91mci_host *host = mmc_priv(mmc); 904 905 pr_debug("%s: sdio_irq %c : %s\n", mmc_hostname(host->mmc), 906 host->board->slot_b ? 'B':'A', enable ? "enable" : "disable"); 907 at91_mci_write(host, enable ? AT91_MCI_IER : AT91_MCI_IDR, 908 host->board->slot_b ? AT91_MCI_SDIOIRQB : AT91_MCI_SDIOIRQA); 909 910} 911 912static const struct mmc_host_ops at91_mci_ops = { 913 .request = at91_mci_request, 914 .set_ios = at91_mci_set_ios, 915 .get_ro = at91_mci_get_ro, 916 .enable_sdio_irq = at91_mci_enable_sdio_irq, 917}; 918 919/* 920 * Probe for the device 921 */ 922static int __init at91_mci_probe(struct platform_device *pdev) 923{ 924 struct mmc_host *mmc; 925 struct at91mci_host *host; 926 struct resource *res; 927 int ret; 928 929 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 930 if (!res) 931 return -ENXIO; 932 933 if (!request_mem_region(res->start, res->end - res->start + 1, DRIVER_NAME)) 934 return -EBUSY; 935 936 mmc = mmc_alloc_host(sizeof(struct at91mci_host), &pdev->dev); 937 if (!mmc) { 938 ret = -ENOMEM; 939 dev_dbg(&pdev->dev, "couldn't allocate mmc host\n"); 940 goto fail6; 941 } 942 943 mmc->ops = &at91_mci_ops; 944 mmc->f_min = 375000; 945 mmc->f_max = 25000000; 946 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 947 mmc->caps = 0; 948 949 mmc->max_blk_size = MCI_MAXBLKSIZE; 950 mmc->max_blk_count = MCI_BLKATONCE; 951 mmc->max_req_size = MCI_BUFSIZE; 952 mmc->max_phys_segs = MCI_BLKATONCE; 953 mmc->max_hw_segs = MCI_BLKATONCE; 954 mmc->max_seg_size = MCI_BUFSIZE; 955 956 host = mmc_priv(mmc); 957 host->mmc = mmc; 958 host->bus_mode = 0; 959 host->board = pdev->dev.platform_data; 960 if (host->board->wire4) { 961 if (at91mci_is_mci1rev2xx()) 962 mmc->caps |= MMC_CAP_4_BIT_DATA; 963 else 964 dev_warn(&pdev->dev, "4 wire bus mode not supported" 965 " - using 1 wire\n"); 966 } 967 968 host->buffer = dma_alloc_coherent(&pdev->dev, MCI_BUFSIZE, 969 &host->physical_address, GFP_KERNEL); 970 if (!host->buffer) { 971 ret = -ENOMEM; 972 dev_err(&pdev->dev, "Can't allocate transmit buffer\n"); 973 goto fail5; 974 } 975 976 /* Add SDIO capability when available */ 977 if (at91mci_is_mci1rev2xx()) { 978 /* at91mci MCI1 rev2xx sdio interrupt erratum */ 979 if (host->board->wire4 || !host->board->slot_b) 980 mmc->caps |= MMC_CAP_SDIO_IRQ; 981 } 982 983 /* 984 * Reserve GPIOs ... board init code makes sure these pins are set 985 * up as GPIOs with the right direction (input, except for vcc) 986 */ 987 if (host->board->det_pin) { 988 ret = gpio_request(host->board->det_pin, "mmc_detect"); 989 if (ret < 0) { 990 dev_dbg(&pdev->dev, "couldn't claim card detect pin\n"); 991 goto fail4b; 992 } 993 } 994 if (host->board->wp_pin) { 995 ret = gpio_request(host->board->wp_pin, "mmc_wp"); 996 if (ret < 0) { 997 dev_dbg(&pdev->dev, "couldn't claim wp sense pin\n"); 998 goto fail4; 999 } 1000 } 1001 if (host->board->vcc_pin) { 1002 ret = gpio_request(host->board->vcc_pin, "mmc_vcc"); 1003 if (ret < 0) { 1004 dev_dbg(&pdev->dev, "couldn't claim vcc switch pin\n"); 1005 goto fail3; 1006 } 1007 } 1008 1009 /* 1010 * Get Clock 1011 */ 1012 host->mci_clk = clk_get(&pdev->dev, "mci_clk"); 1013 if (IS_ERR(host->mci_clk)) { 1014 ret = -ENODEV; 1015 dev_dbg(&pdev->dev, "no mci_clk?\n"); 1016 goto fail2; 1017 } 1018 1019 /* 1020 * Map I/O region 1021 */ 1022 host->baseaddr = ioremap(res->start, res->end - res->start + 1); 1023 if (!host->baseaddr) { 1024 ret = -ENOMEM; 1025 goto fail1; 1026 } 1027 1028 /* 1029 * Reset hardware 1030 */ 1031 clk_enable(host->mci_clk); /* Enable the peripheral clock */ 1032 at91_mci_disable(host); 1033 at91_mci_enable(host); 1034 1035 /* 1036 * Allocate the MCI interrupt 1037 */ 1038 host->irq = platform_get_irq(pdev, 0); 1039 ret = request_irq(host->irq, at91_mci_irq, IRQF_SHARED, 1040 mmc_hostname(mmc), host); 1041 if (ret) { 1042 dev_dbg(&pdev->dev, "request MCI interrupt failed\n"); 1043 goto fail0; 1044 } 1045 1046 setup_timer(&host->timer, at91_timeout_timer, (unsigned long)host); 1047 1048 platform_set_drvdata(pdev, mmc); 1049 1050 /* 1051 * Add host to MMC layer 1052 */ 1053 if (host->board->det_pin) { 1054 host->present = !gpio_get_value(host->board->det_pin); 1055 } 1056 else 1057 host->present = -1; 1058 1059 mmc_add_host(mmc); 1060 1061 /* 1062 * monitor card insertion/removal if we can 1063 */ 1064 if (host->board->det_pin) { 1065 ret = request_irq(gpio_to_irq(host->board->det_pin), 1066 at91_mmc_det_irq, 0, mmc_hostname(mmc), host); 1067 if (ret) 1068 dev_warn(&pdev->dev, "request MMC detect irq failed\n"); 1069 else 1070 device_init_wakeup(&pdev->dev, 1); 1071 } 1072 1073 pr_debug("Added MCI driver\n"); 1074 1075 return 0; 1076 1077fail0: 1078 clk_disable(host->mci_clk); 1079 iounmap(host->baseaddr); 1080fail1: 1081 clk_put(host->mci_clk); 1082fail2: 1083 if (host->board->vcc_pin) 1084 gpio_free(host->board->vcc_pin); 1085fail3: 1086 if (host->board->wp_pin) 1087 gpio_free(host->board->wp_pin); 1088fail4: 1089 if (host->board->det_pin) 1090 gpio_free(host->board->det_pin); 1091fail4b: 1092 if (host->buffer) 1093 dma_free_coherent(&pdev->dev, MCI_BUFSIZE, 1094 host->buffer, host->physical_address); 1095fail5: 1096 mmc_free_host(mmc); 1097fail6: 1098 release_mem_region(res->start, res->end - res->start + 1); 1099 dev_err(&pdev->dev, "probe failed, err %d\n", ret); 1100 return ret; 1101} 1102 1103/* 1104 * Remove a device 1105 */ 1106static int __exit at91_mci_remove(struct platform_device *pdev) 1107{ 1108 struct mmc_host *mmc = platform_get_drvdata(pdev); 1109 struct at91mci_host *host; 1110 struct resource *res; 1111 1112 if (!mmc) 1113 return -1; 1114 1115 host = mmc_priv(mmc); 1116 1117 if (host->buffer) 1118 dma_free_coherent(&pdev->dev, MCI_BUFSIZE, 1119 host->buffer, host->physical_address); 1120 1121 if (host->board->det_pin) { 1122 if (device_can_wakeup(&pdev->dev)) 1123 free_irq(gpio_to_irq(host->board->det_pin), host); 1124 device_init_wakeup(&pdev->dev, 0); 1125 gpio_free(host->board->det_pin); 1126 } 1127 1128 at91_mci_disable(host); 1129 del_timer_sync(&host->timer); 1130 mmc_remove_host(mmc); 1131 free_irq(host->irq, host); 1132 1133 clk_disable(host->mci_clk); /* Disable the peripheral clock */ 1134 clk_put(host->mci_clk); 1135 1136 if (host->board->vcc_pin) 1137 gpio_free(host->board->vcc_pin); 1138 if (host->board->wp_pin) 1139 gpio_free(host->board->wp_pin); 1140 1141 iounmap(host->baseaddr); 1142 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1143 release_mem_region(res->start, res->end - res->start + 1); 1144 1145 mmc_free_host(mmc); 1146 platform_set_drvdata(pdev, NULL); 1147 pr_debug("MCI Removed\n"); 1148 1149 return 0; 1150} 1151 1152#ifdef CONFIG_PM 1153static int at91_mci_suspend(struct platform_device *pdev, pm_message_t state) 1154{ 1155 struct mmc_host *mmc = platform_get_drvdata(pdev); 1156 struct at91mci_host *host = mmc_priv(mmc); 1157 int ret = 0; 1158 1159 if (host->board->det_pin && device_may_wakeup(&pdev->dev)) 1160 enable_irq_wake(host->board->det_pin); 1161 1162 if (mmc) 1163 ret = mmc_suspend_host(mmc); 1164 1165 return ret; 1166} 1167 1168static int at91_mci_resume(struct platform_device *pdev) 1169{ 1170 struct mmc_host *mmc = platform_get_drvdata(pdev); 1171 struct at91mci_host *host = mmc_priv(mmc); 1172 int ret = 0; 1173 1174 if (host->board->det_pin && device_may_wakeup(&pdev->dev)) 1175 disable_irq_wake(host->board->det_pin); 1176 1177 if (mmc) 1178 ret = mmc_resume_host(mmc); 1179 1180 return ret; 1181} 1182#else 1183#define at91_mci_suspend NULL 1184#define at91_mci_resume NULL 1185#endif 1186 1187static struct platform_driver at91_mci_driver = { 1188 .remove = __exit_p(at91_mci_remove), 1189 .suspend = at91_mci_suspend, 1190 .resume = at91_mci_resume, 1191 .driver = { 1192 .name = DRIVER_NAME, 1193 .owner = THIS_MODULE, 1194 }, 1195}; 1196 1197static int __init at91_mci_init(void) 1198{ 1199 return platform_driver_probe(&at91_mci_driver, at91_mci_probe); 1200} 1201 1202static void __exit at91_mci_exit(void) 1203{ 1204 platform_driver_unregister(&at91_mci_driver); 1205} 1206 1207module_init(at91_mci_init); 1208module_exit(at91_mci_exit); 1209 1210MODULE_DESCRIPTION("AT91 Multimedia Card Interface driver"); 1211MODULE_AUTHOR("Nick Randell"); 1212MODULE_LICENSE("GPL"); 1213MODULE_ALIAS("platform:at91_mci"); 1214