1/* 2 * twl4030-irq.c - TWL4030/TPS659x0 irq support 3 * 4 * Copyright (C) 2005-2006 Texas Instruments, Inc. 5 * 6 * Modifications to defer interrupt handling to a kernel thread: 7 * Copyright (C) 2006 MontaVista Software, Inc. 8 * 9 * Based on tlv320aic23.c: 10 * Copyright (c) by Kai Svahn <kai.svahn@nokia.com> 11 * 12 * Code cleanup and modifications to IRQ handler. 13 * by syed khasim <x0khasim@ti.com> 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2 of the License, or 18 * (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 28 */ 29 30#include <linux/init.h> 31#include <linux/interrupt.h> 32#include <linux/irq.h> 33#include <linux/kthread.h> 34#include <linux/slab.h> 35 36#include <linux/i2c/twl.h> 37 38 39/* 40 * TWL4030 IRQ handling has two stages in hardware, and thus in software. 41 * The Primary Interrupt Handler (PIH) stage exposes status bits saying 42 * which Secondary Interrupt Handler (SIH) stage is raising an interrupt. 43 * SIH modules are more traditional IRQ components, which support per-IRQ 44 * enable/disable and trigger controls; they do most of the work. 45 * 46 * These chips are designed to support IRQ handling from two different 47 * I2C masters. Each has a dedicated IRQ line, and dedicated IRQ status 48 * and mask registers in the PIH and SIH modules. 49 * 50 * We set up IRQs starting at a platform-specified base, always starting 51 * with PIH and the SIH for PWR_INT and then usually adding GPIO: 52 * base + 0 .. base + 7 PIH 53 * base + 8 .. base + 15 SIH for PWR_INT 54 * base + 16 .. base + 33 SIH for GPIO 55 */ 56 57/* PIH register offsets */ 58#define REG_PIH_ISR_P1 0x01 59#define REG_PIH_ISR_P2 0x02 60#define REG_PIH_SIR 0x03 /* for testing */ 61 62 63/* Linux could (eventually) use either IRQ line */ 64static int irq_line; 65 66struct sih { 67 char name[8]; 68 u8 module; /* module id */ 69 u8 control_offset; /* for SIH_CTRL */ 70 bool set_cor; 71 72 u8 bits; /* valid in isr/imr */ 73 u8 bytes_ixr; /* bytelen of ISR/IMR/SIR */ 74 75 u8 edr_offset; 76 u8 bytes_edr; /* bytelen of EDR */ 77 78 u8 irq_lines; /* number of supported irq lines */ 79 80 /* SIR ignored -- set interrupt, for testing only */ 81 struct irq_data { 82 u8 isr_offset; 83 u8 imr_offset; 84 } mask[2]; 85 /* + 2 bytes padding */ 86}; 87 88static const struct sih *sih_modules; 89static int nr_sih_modules; 90 91#define SIH_INITIALIZER(modname, nbits) \ 92 .module = TWL4030_MODULE_ ## modname, \ 93 .control_offset = TWL4030_ ## modname ## _SIH_CTRL, \ 94 .bits = nbits, \ 95 .bytes_ixr = DIV_ROUND_UP(nbits, 8), \ 96 .edr_offset = TWL4030_ ## modname ## _EDR, \ 97 .bytes_edr = DIV_ROUND_UP((2*(nbits)), 8), \ 98 .irq_lines = 2, \ 99 .mask = { { \ 100 .isr_offset = TWL4030_ ## modname ## _ISR1, \ 101 .imr_offset = TWL4030_ ## modname ## _IMR1, \ 102 }, \ 103 { \ 104 .isr_offset = TWL4030_ ## modname ## _ISR2, \ 105 .imr_offset = TWL4030_ ## modname ## _IMR2, \ 106 }, }, 107 108/* register naming policies are inconsistent ... */ 109#define TWL4030_INT_PWR_EDR TWL4030_INT_PWR_EDR1 110#define TWL4030_MODULE_KEYPAD_KEYP TWL4030_MODULE_KEYPAD 111#define TWL4030_MODULE_INT_PWR TWL4030_MODULE_INT 112 113 114/* Order in this table matches order in PIH_ISR. That is, 115 * BIT(n) in PIH_ISR is sih_modules[n]. 116 */ 117/* sih_modules_twl4030 is used both in twl4030 and twl5030 */ 118static const struct sih sih_modules_twl4030[6] = { 119 [0] = { 120 .name = "gpio", 121 .module = TWL4030_MODULE_GPIO, 122 .control_offset = REG_GPIO_SIH_CTRL, 123 .set_cor = true, 124 .bits = TWL4030_GPIO_MAX, 125 .bytes_ixr = 3, 126 /* Note: *all* of these IRQs default to no-trigger */ 127 .edr_offset = REG_GPIO_EDR1, 128 .bytes_edr = 5, 129 .irq_lines = 2, 130 .mask = { { 131 .isr_offset = REG_GPIO_ISR1A, 132 .imr_offset = REG_GPIO_IMR1A, 133 }, { 134 .isr_offset = REG_GPIO_ISR1B, 135 .imr_offset = REG_GPIO_IMR1B, 136 }, }, 137 }, 138 [1] = { 139 .name = "keypad", 140 .set_cor = true, 141 SIH_INITIALIZER(KEYPAD_KEYP, 4) 142 }, 143 [2] = { 144 .name = "bci", 145 .module = TWL4030_MODULE_INTERRUPTS, 146 .control_offset = TWL4030_INTERRUPTS_BCISIHCTRL, 147 .bits = 12, 148 .bytes_ixr = 2, 149 .edr_offset = TWL4030_INTERRUPTS_BCIEDR1, 150 /* Note: most of these IRQs default to no-trigger */ 151 .bytes_edr = 3, 152 .irq_lines = 2, 153 .mask = { { 154 .isr_offset = TWL4030_INTERRUPTS_BCIISR1A, 155 .imr_offset = TWL4030_INTERRUPTS_BCIIMR1A, 156 }, { 157 .isr_offset = TWL4030_INTERRUPTS_BCIISR1B, 158 .imr_offset = TWL4030_INTERRUPTS_BCIIMR1B, 159 }, }, 160 }, 161 [3] = { 162 .name = "madc", 163 SIH_INITIALIZER(MADC, 4) 164 }, 165 [4] = { 166 /* USB doesn't use the same SIH organization */ 167 .name = "usb", 168 }, 169 [5] = { 170 .name = "power", 171 .set_cor = true, 172 SIH_INITIALIZER(INT_PWR, 8) 173 }, 174 /* there are no SIH modules #6 or #7 ... */ 175}; 176 177static const struct sih sih_modules_twl5031[8] = { 178 [0] = { 179 .name = "gpio", 180 .module = TWL4030_MODULE_GPIO, 181 .control_offset = REG_GPIO_SIH_CTRL, 182 .set_cor = true, 183 .bits = TWL4030_GPIO_MAX, 184 .bytes_ixr = 3, 185 /* Note: *all* of these IRQs default to no-trigger */ 186 .edr_offset = REG_GPIO_EDR1, 187 .bytes_edr = 5, 188 .irq_lines = 2, 189 .mask = { { 190 .isr_offset = REG_GPIO_ISR1A, 191 .imr_offset = REG_GPIO_IMR1A, 192 }, { 193 .isr_offset = REG_GPIO_ISR1B, 194 .imr_offset = REG_GPIO_IMR1B, 195 }, }, 196 }, 197 [1] = { 198 .name = "keypad", 199 .set_cor = true, 200 SIH_INITIALIZER(KEYPAD_KEYP, 4) 201 }, 202 [2] = { 203 .name = "bci", 204 .module = TWL5031_MODULE_INTERRUPTS, 205 .control_offset = TWL5031_INTERRUPTS_BCISIHCTRL, 206 .bits = 7, 207 .bytes_ixr = 1, 208 .edr_offset = TWL5031_INTERRUPTS_BCIEDR1, 209 /* Note: most of these IRQs default to no-trigger */ 210 .bytes_edr = 2, 211 .irq_lines = 2, 212 .mask = { { 213 .isr_offset = TWL5031_INTERRUPTS_BCIISR1, 214 .imr_offset = TWL5031_INTERRUPTS_BCIIMR1, 215 }, { 216 .isr_offset = TWL5031_INTERRUPTS_BCIISR2, 217 .imr_offset = TWL5031_INTERRUPTS_BCIIMR2, 218 }, }, 219 }, 220 [3] = { 221 .name = "madc", 222 SIH_INITIALIZER(MADC, 4) 223 }, 224 [4] = { 225 /* USB doesn't use the same SIH organization */ 226 .name = "usb", 227 }, 228 [5] = { 229 .name = "power", 230 .set_cor = true, 231 SIH_INITIALIZER(INT_PWR, 8) 232 }, 233 [6] = { 234 /* 235 * ECI/DBI doesn't use the same SIH organization. 236 * For example, it supports only one interrupt output line. 237 * That is, the interrupts are seen on both INT1 and INT2 lines. 238 */ 239 .name = "eci_dbi", 240 .module = TWL5031_MODULE_ACCESSORY, 241 .bits = 9, 242 .bytes_ixr = 2, 243 .irq_lines = 1, 244 .mask = { { 245 .isr_offset = TWL5031_ACIIDR_LSB, 246 .imr_offset = TWL5031_ACIIMR_LSB, 247 }, }, 248 249 }, 250 [7] = { 251 /* Audio accessory */ 252 .name = "audio", 253 .module = TWL5031_MODULE_ACCESSORY, 254 .control_offset = TWL5031_ACCSIHCTRL, 255 .bits = 2, 256 .bytes_ixr = 1, 257 .edr_offset = TWL5031_ACCEDR1, 258 /* Note: most of these IRQs default to no-trigger */ 259 .bytes_edr = 1, 260 .irq_lines = 2, 261 .mask = { { 262 .isr_offset = TWL5031_ACCISR1, 263 .imr_offset = TWL5031_ACCIMR1, 264 }, { 265 .isr_offset = TWL5031_ACCISR2, 266 .imr_offset = TWL5031_ACCIMR2, 267 }, }, 268 }, 269}; 270 271#undef TWL4030_MODULE_KEYPAD_KEYP 272#undef TWL4030_MODULE_INT_PWR 273#undef TWL4030_INT_PWR_EDR 274 275/*----------------------------------------------------------------------*/ 276 277static unsigned twl4030_irq_base; 278 279static struct completion irq_event; 280 281/* 282 * This thread processes interrupts reported by the Primary Interrupt Handler. 283 */ 284static int twl4030_irq_thread(void *data) 285{ 286 long irq = (long)data; 287 static unsigned i2c_errors; 288 static const unsigned max_i2c_errors = 100; 289 290 291 current->flags |= PF_NOFREEZE; 292 293 while (!kthread_should_stop()) { 294 int ret; 295 int module_irq; 296 u8 pih_isr; 297 298 /* Wait for IRQ, then read PIH irq status (also blocking) */ 299 wait_for_completion_interruptible(&irq_event); 300 301 ret = twl_i2c_read_u8(TWL4030_MODULE_PIH, &pih_isr, 302 REG_PIH_ISR_P1); 303 if (ret) { 304 pr_warning("twl4030: I2C error %d reading PIH ISR\n", 305 ret); 306 if (++i2c_errors >= max_i2c_errors) { 307 printk(KERN_ERR "Maximum I2C error count" 308 " exceeded. Terminating %s.\n", 309 __func__); 310 break; 311 } 312 complete(&irq_event); 313 continue; 314 } 315 316 /* these handlers deal with the relevant SIH irq status */ 317 local_irq_disable(); 318 for (module_irq = twl4030_irq_base; 319 pih_isr; 320 pih_isr >>= 1, module_irq++) { 321 if (pih_isr & 0x1) { 322 struct irq_desc *d = irq_to_desc(module_irq); 323 324 if (!d) { 325 pr_err("twl4030: Invalid SIH IRQ: %d\n", 326 module_irq); 327 return -EINVAL; 328 } 329 330 /* These can't be masked ... always warn 331 * if we get any surprises. 332 */ 333 if (d->status & IRQ_DISABLED) 334 note_interrupt(module_irq, d, 335 IRQ_NONE); 336 else 337 d->handle_irq(module_irq, d); 338 } 339 } 340 local_irq_enable(); 341 342 enable_irq(irq); 343 } 344 345 return 0; 346} 347 348/* 349 * handle_twl4030_pih() is the desc->handle method for the twl4030 interrupt. 350 * This is a chained interrupt, so there is no desc->action method for it. 351 * Now we need to query the interrupt controller in the twl4030 to determine 352 * which module is generating the interrupt request. However, we can't do i2c 353 * transactions in interrupt context, so we must defer that work to a kernel 354 * thread. All we do here is acknowledge and mask the interrupt and wakeup 355 * the kernel thread. 356 */ 357static irqreturn_t handle_twl4030_pih(int irq, void *devid) 358{ 359 /* Acknowledge, clear *AND* mask the interrupt... */ 360 disable_irq_nosync(irq); 361 complete(devid); 362 return IRQ_HANDLED; 363} 364/*----------------------------------------------------------------------*/ 365 366/* 367 * twl4030_init_sih_modules() ... start from a known state where no 368 * IRQs will be coming in, and where we can quickly enable them then 369 * handle them as they arrive. Mask all IRQs: maybe init SIH_CTRL. 370 * 371 * NOTE: we don't touch EDR registers here; they stay with hardware 372 * defaults or whatever the last value was. Note that when both EDR 373 * bits for an IRQ are clear, that's as if its IMR bit is set... 374 */ 375static int twl4030_init_sih_modules(unsigned line) 376{ 377 const struct sih *sih; 378 u8 buf[4]; 379 int i; 380 int status; 381 382 /* line 0 == int1_n signal; line 1 == int2_n signal */ 383 if (line > 1) 384 return -EINVAL; 385 386 irq_line = line; 387 388 /* disable all interrupts on our line */ 389 memset(buf, 0xff, sizeof buf); 390 sih = sih_modules; 391 for (i = 0; i < nr_sih_modules; i++, sih++) { 392 393 /* skip USB -- it's funky */ 394 if (!sih->bytes_ixr) 395 continue; 396 397 /* Not all the SIH modules support multiple interrupt lines */ 398 if (sih->irq_lines <= line) 399 continue; 400 401 status = twl_i2c_write(sih->module, buf, 402 sih->mask[line].imr_offset, sih->bytes_ixr); 403 if (status < 0) 404 pr_err("twl4030: err %d initializing %s %s\n", 405 status, sih->name, "IMR"); 406 407 /* Maybe disable "exclusive" mode; buffer second pending irq; 408 * set Clear-On-Read (COR) bit. 409 * 410 * NOTE that sometimes COR polarity is documented as being 411 * inverted: for MADC and BCI, COR=1 means "clear on write". 412 * And for PWR_INT it's not documented... 413 */ 414 if (sih->set_cor) { 415 status = twl_i2c_write_u8(sih->module, 416 TWL4030_SIH_CTRL_COR_MASK, 417 sih->control_offset); 418 if (status < 0) 419 pr_err("twl4030: err %d initializing %s %s\n", 420 status, sih->name, "SIH_CTRL"); 421 } 422 } 423 424 sih = sih_modules; 425 for (i = 0; i < nr_sih_modules; i++, sih++) { 426 u8 rxbuf[4]; 427 int j; 428 429 /* skip USB */ 430 if (!sih->bytes_ixr) 431 continue; 432 433 /* Not all the SIH modules support multiple interrupt lines */ 434 if (sih->irq_lines <= line) 435 continue; 436 437 /* Clear pending interrupt status. Either the read was 438 * enough, or we need to write those bits. Repeat, in 439 * case an IRQ is pending (PENDDIS=0) ... that's not 440 * uncommon with PWR_INT.PWRON. 441 */ 442 for (j = 0; j < 2; j++) { 443 status = twl_i2c_read(sih->module, rxbuf, 444 sih->mask[line].isr_offset, sih->bytes_ixr); 445 if (status < 0) 446 pr_err("twl4030: err %d initializing %s %s\n", 447 status, sih->name, "ISR"); 448 449 if (!sih->set_cor) 450 status = twl_i2c_write(sih->module, buf, 451 sih->mask[line].isr_offset, 452 sih->bytes_ixr); 453 /* else COR=1 means read sufficed. 454 * (for most SIH modules...) 455 */ 456 } 457 } 458 459 return 0; 460} 461 462static inline void activate_irq(int irq) 463{ 464#ifdef CONFIG_ARM 465 /* ARM requires an extra step to clear IRQ_NOREQUEST, which it 466 * sets on behalf of every irq_chip. Also sets IRQ_NOPROBE. 467 */ 468 set_irq_flags(irq, IRQF_VALID); 469#else 470 /* same effect on other architectures */ 471 set_irq_noprobe(irq); 472#endif 473} 474 475/*----------------------------------------------------------------------*/ 476 477static DEFINE_SPINLOCK(sih_agent_lock); 478 479static struct workqueue_struct *wq; 480 481struct sih_agent { 482 int irq_base; 483 const struct sih *sih; 484 485 u32 imr; 486 bool imr_change_pending; 487 struct work_struct mask_work; 488 489 u32 edge_change; 490 struct work_struct edge_work; 491}; 492 493static void twl4030_sih_do_mask(struct work_struct *work) 494{ 495 struct sih_agent *agent; 496 const struct sih *sih; 497 union { 498 u8 bytes[4]; 499 u32 word; 500 } imr; 501 int status; 502 503 agent = container_of(work, struct sih_agent, mask_work); 504 505 /* see what work we have */ 506 spin_lock_irq(&sih_agent_lock); 507 if (agent->imr_change_pending) { 508 sih = agent->sih; 509 /* byte[0] gets overwritten as we write ... */ 510 imr.word = cpu_to_le32(agent->imr << 8); 511 agent->imr_change_pending = false; 512 } else 513 sih = NULL; 514 spin_unlock_irq(&sih_agent_lock); 515 if (!sih) 516 return; 517 518 /* write the whole mask ... simpler than subsetting it */ 519 status = twl_i2c_write(sih->module, imr.bytes, 520 sih->mask[irq_line].imr_offset, sih->bytes_ixr); 521 if (status) 522 pr_err("twl4030: %s, %s --> %d\n", __func__, 523 "write", status); 524} 525 526static void twl4030_sih_do_edge(struct work_struct *work) 527{ 528 struct sih_agent *agent; 529 const struct sih *sih; 530 u8 bytes[6]; 531 u32 edge_change; 532 int status; 533 534 agent = container_of(work, struct sih_agent, edge_work); 535 536 /* see what work we have */ 537 spin_lock_irq(&sih_agent_lock); 538 edge_change = agent->edge_change; 539 agent->edge_change = 0; 540 sih = edge_change ? agent->sih : NULL; 541 spin_unlock_irq(&sih_agent_lock); 542 if (!sih) 543 return; 544 545 /* Read, reserving first byte for write scratch. Yes, this 546 * could be cached for some speedup ... but be careful about 547 * any processor on the other IRQ line, EDR registers are 548 * shared. 549 */ 550 status = twl_i2c_read(sih->module, bytes + 1, 551 sih->edr_offset, sih->bytes_edr); 552 if (status) { 553 pr_err("twl4030: %s, %s --> %d\n", __func__, 554 "read", status); 555 return; 556 } 557 558 /* Modify only the bits we know must change */ 559 while (edge_change) { 560 int i = fls(edge_change) - 1; 561 struct irq_desc *d = irq_to_desc(i + agent->irq_base); 562 int byte = 1 + (i >> 2); 563 int off = (i & 0x3) * 2; 564 565 if (!d) { 566 pr_err("twl4030: Invalid IRQ: %d\n", 567 i + agent->irq_base); 568 return; 569 } 570 571 bytes[byte] &= ~(0x03 << off); 572 573 raw_spin_lock_irq(&d->lock); 574 if (d->status & IRQ_TYPE_EDGE_RISING) 575 bytes[byte] |= BIT(off + 1); 576 if (d->status & IRQ_TYPE_EDGE_FALLING) 577 bytes[byte] |= BIT(off + 0); 578 raw_spin_unlock_irq(&d->lock); 579 580 edge_change &= ~BIT(i); 581 } 582 583 /* Write */ 584 status = twl_i2c_write(sih->module, bytes, 585 sih->edr_offset, sih->bytes_edr); 586 if (status) 587 pr_err("twl4030: %s, %s --> %d\n", __func__, 588 "write", status); 589} 590 591/*----------------------------------------------------------------------*/ 592 593/* 594 * All irq_chip methods get issued from code holding irq_desc[irq].lock, 595 * which can't perform the underlying I2C operations (because they sleep). 596 * So we must hand them off to a thread (workqueue) and cope with asynch 597 * completion, potentially including some re-ordering, of these requests. 598 */ 599 600static void twl4030_sih_mask(unsigned irq) 601{ 602 struct sih_agent *sih = get_irq_chip_data(irq); 603 unsigned long flags; 604 605 spin_lock_irqsave(&sih_agent_lock, flags); 606 sih->imr |= BIT(irq - sih->irq_base); 607 sih->imr_change_pending = true; 608 queue_work(wq, &sih->mask_work); 609 spin_unlock_irqrestore(&sih_agent_lock, flags); 610} 611 612static void twl4030_sih_unmask(unsigned irq) 613{ 614 struct sih_agent *sih = get_irq_chip_data(irq); 615 unsigned long flags; 616 617 spin_lock_irqsave(&sih_agent_lock, flags); 618 sih->imr &= ~BIT(irq - sih->irq_base); 619 sih->imr_change_pending = true; 620 queue_work(wq, &sih->mask_work); 621 spin_unlock_irqrestore(&sih_agent_lock, flags); 622} 623 624static int twl4030_sih_set_type(unsigned irq, unsigned trigger) 625{ 626 struct sih_agent *sih = get_irq_chip_data(irq); 627 struct irq_desc *desc = irq_to_desc(irq); 628 unsigned long flags; 629 630 if (!desc) { 631 pr_err("twl4030: Invalid IRQ: %d\n", irq); 632 return -EINVAL; 633 } 634 635 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 636 return -EINVAL; 637 638 spin_lock_irqsave(&sih_agent_lock, flags); 639 if ((desc->status & IRQ_TYPE_SENSE_MASK) != trigger) { 640 desc->status &= ~IRQ_TYPE_SENSE_MASK; 641 desc->status |= trigger; 642 sih->edge_change |= BIT(irq - sih->irq_base); 643 queue_work(wq, &sih->edge_work); 644 } 645 spin_unlock_irqrestore(&sih_agent_lock, flags); 646 return 0; 647} 648 649static struct irq_chip twl4030_sih_irq_chip = { 650 .name = "twl4030", 651 .mask = twl4030_sih_mask, 652 .unmask = twl4030_sih_unmask, 653 .set_type = twl4030_sih_set_type, 654}; 655 656/*----------------------------------------------------------------------*/ 657 658static inline int sih_read_isr(const struct sih *sih) 659{ 660 int status; 661 union { 662 u8 bytes[4]; 663 u32 word; 664 } isr; 665 666 667 isr.word = 0; 668 status = twl_i2c_read(sih->module, isr.bytes, 669 sih->mask[irq_line].isr_offset, sih->bytes_ixr); 670 671 return (status < 0) ? status : le32_to_cpu(isr.word); 672} 673 674/* 675 * Generic handler for SIH interrupts ... we "know" this is called 676 * in task context, with IRQs enabled. 677 */ 678static void handle_twl4030_sih(unsigned irq, struct irq_desc *desc) 679{ 680 struct sih_agent *agent = get_irq_data(irq); 681 const struct sih *sih = agent->sih; 682 int isr; 683 684 /* reading ISR acks the IRQs, using clear-on-read mode */ 685 local_irq_enable(); 686 isr = sih_read_isr(sih); 687 local_irq_disable(); 688 689 if (isr < 0) { 690 pr_err("twl4030: %s SIH, read ISR error %d\n", 691 sih->name, isr); 692 /* REVISIT: recover; eventually mask it all, etc */ 693 return; 694 } 695 696 while (isr) { 697 irq = fls(isr); 698 irq--; 699 isr &= ~BIT(irq); 700 701 if (irq < sih->bits) 702 generic_handle_irq(agent->irq_base + irq); 703 else 704 pr_err("twl4030: %s SIH, invalid ISR bit %d\n", 705 sih->name, irq); 706 } 707} 708 709static unsigned twl4030_irq_next; 710 711/* returns the first IRQ used by this SIH bank, 712 * or negative errno 713 */ 714int twl4030_sih_setup(int module) 715{ 716 int sih_mod; 717 const struct sih *sih = NULL; 718 struct sih_agent *agent; 719 int i, irq; 720 int status = -EINVAL; 721 unsigned irq_base = twl4030_irq_next; 722 723 /* only support modules with standard clear-on-read for now */ 724 for (sih_mod = 0, sih = sih_modules; 725 sih_mod < nr_sih_modules; 726 sih_mod++, sih++) { 727 if (sih->module == module && sih->set_cor) { 728 if (!WARN((irq_base + sih->bits) > NR_IRQS, 729 "irq %d for %s too big\n", 730 irq_base + sih->bits, 731 sih->name)) 732 status = 0; 733 break; 734 } 735 } 736 if (status < 0) 737 return status; 738 739 agent = kzalloc(sizeof *agent, GFP_KERNEL); 740 if (!agent) 741 return -ENOMEM; 742 743 status = 0; 744 745 agent->irq_base = irq_base; 746 agent->sih = sih; 747 agent->imr = ~0; 748 INIT_WORK(&agent->mask_work, twl4030_sih_do_mask); 749 INIT_WORK(&agent->edge_work, twl4030_sih_do_edge); 750 751 for (i = 0; i < sih->bits; i++) { 752 irq = irq_base + i; 753 754 set_irq_chip_and_handler(irq, &twl4030_sih_irq_chip, 755 handle_edge_irq); 756 set_irq_chip_data(irq, agent); 757 activate_irq(irq); 758 } 759 760 status = irq_base; 761 twl4030_irq_next += i; 762 763 /* replace generic PIH handler (handle_simple_irq) */ 764 irq = sih_mod + twl4030_irq_base; 765 set_irq_data(irq, agent); 766 set_irq_chained_handler(irq, handle_twl4030_sih); 767 768 pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", sih->name, 769 irq, irq_base, twl4030_irq_next - 1); 770 771 return status; 772} 773 774 775 776/*----------------------------------------------------------------------*/ 777 778#define twl_irq_line 0 779 780int twl4030_init_irq(int irq_num, unsigned irq_base, unsigned irq_end) 781{ 782 static struct irq_chip twl4030_irq_chip; 783 784 int status; 785 int i; 786 struct task_struct *task; 787 788 /* 789 * Mask and clear all TWL4030 interrupts since initially we do 790 * not have any TWL4030 module interrupt handlers present 791 */ 792 status = twl4030_init_sih_modules(twl_irq_line); 793 if (status < 0) 794 return status; 795 796 wq = create_singlethread_workqueue("twl4030-irqchip"); 797 if (!wq) { 798 pr_err("twl4030: workqueue FAIL\n"); 799 return -ESRCH; 800 } 801 802 twl4030_irq_base = irq_base; 803 804 /* install an irq handler for each of the SIH modules; 805 * clone dummy irq_chip since PIH can't *do* anything 806 */ 807 twl4030_irq_chip = dummy_irq_chip; 808 twl4030_irq_chip.name = "twl4030"; 809 810 twl4030_sih_irq_chip.ack = dummy_irq_chip.ack; 811 812 for (i = irq_base; i < irq_end; i++) { 813 set_irq_chip_and_handler(i, &twl4030_irq_chip, 814 handle_simple_irq); 815 activate_irq(i); 816 } 817 twl4030_irq_next = i; 818 pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", "PIH", 819 irq_num, irq_base, twl4030_irq_next - 1); 820 821 /* ... and the PWR_INT module ... */ 822 status = twl4030_sih_setup(TWL4030_MODULE_INT); 823 if (status < 0) { 824 pr_err("twl4030: sih_setup PWR INT --> %d\n", status); 825 goto fail; 826 } 827 828 /* install an irq handler to demultiplex the TWL4030 interrupt */ 829 830 831 init_completion(&irq_event); 832 833 status = request_irq(irq_num, handle_twl4030_pih, IRQF_DISABLED, 834 "TWL4030-PIH", &irq_event); 835 if (status < 0) { 836 pr_err("twl4030: could not claim irq%d: %d\n", irq_num, status); 837 goto fail_rqirq; 838 } 839 840 task = kthread_run(twl4030_irq_thread, (void *)(long)irq_num, 841 "twl4030-irq"); 842 if (IS_ERR(task)) { 843 pr_err("twl4030: could not create irq %d thread!\n", irq_num); 844 status = PTR_ERR(task); 845 goto fail_kthread; 846 } 847 return status; 848fail_kthread: 849 free_irq(irq_num, &irq_event); 850fail_rqirq: 851 /* clean up twl4030_sih_setup */ 852fail: 853 for (i = irq_base; i < irq_end; i++) 854 set_irq_chip_and_handler(i, NULL, NULL); 855 destroy_workqueue(wq); 856 wq = NULL; 857 return status; 858} 859 860int twl4030_exit_irq(void) 861{ 862 if (twl4030_irq_base) { 863 pr_err("twl4030: can't yet clean up IRQs?\n"); 864 return -ENOSYS; 865 } 866 return 0; 867} 868 869int twl4030_init_chip_irq(const char *chip) 870{ 871 if (!strcmp(chip, "twl5031")) { 872 sih_modules = sih_modules_twl5031; 873 nr_sih_modules = ARRAY_SIZE(sih_modules_twl5031); 874 } else { 875 sih_modules = sih_modules_twl4030; 876 nr_sih_modules = ARRAY_SIZE(sih_modules_twl4030); 877 } 878 879 return 0; 880} 881