1/* saa711x - Philips SAA711x video decoder driver 2 * This driver can work with saa7111, saa7111a, saa7113, saa7114, 3 * saa7115 and saa7118. 4 * 5 * Based on saa7114 driver by Maxim Yevtyushkin, which is based on 6 * the saa7111 driver by Dave Perks. 7 * 8 * Copyright (C) 1998 Dave Perks <dperks@ibm.net> 9 * Copyright (C) 2002 Maxim Yevtyushkin <max@linuxmedialabs.com> 10 * 11 * Slight changes for video timing and attachment output by 12 * Wolfgang Scherr <scherr@net4you.net> 13 * 14 * Moved over to the linux >= 2.4.x i2c protocol (1/1/2003) 15 * by Ronald Bultje <rbultje@ronald.bitfreak.net> 16 * 17 * Added saa7115 support by Kevin Thayer <nufan_wfk at yahoo.com> 18 * (2/17/2003) 19 * 20 * VBI support (2004) and cleanups (2005) by Hans Verkuil <hverkuil@xs4all.nl> 21 * 22 * Copyright (c) 2005-2006 Mauro Carvalho Chehab <mchehab@infradead.org> 23 * SAA7111, SAA7113 and SAA7118 support 24 * 25 * This program is free software; you can redistribute it and/or 26 * modify it under the terms of the GNU General Public License 27 * as published by the Free Software Foundation; either version 2 28 * of the License, or (at your option) any later version. 29 * 30 * This program is distributed in the hope that it will be useful, 31 * but WITHOUT ANY WARRANTY; without even the implied warranty of 32 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 33 * GNU General Public License for more details. 34 * 35 * You should have received a copy of the GNU General Public License 36 * along with this program; if not, write to the Free Software 37 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 38 */ 39 40#include "saa711x_regs.h" 41 42#include <linux/kernel.h> 43#include <linux/module.h> 44#include <linux/slab.h> 45#include <linux/i2c.h> 46#include <linux/videodev2.h> 47#include <media/v4l2-device.h> 48#include <media/v4l2-ctrls.h> 49#include <media/v4l2-chip-ident.h> 50#include <media/v4l2-i2c-drv.h> 51#include <media/saa7115.h> 52#include <asm/div64.h> 53 54#define VRES_60HZ (480+16) 55 56MODULE_DESCRIPTION("Philips SAA7111/SAA7113/SAA7114/SAA7115/SAA7118 video decoder driver"); 57MODULE_AUTHOR( "Maxim Yevtyushkin, Kevin Thayer, Chris Kennedy, " 58 "Hans Verkuil, Mauro Carvalho Chehab"); 59MODULE_LICENSE("GPL"); 60 61static int debug; 62module_param(debug, bool, 0644); 63 64MODULE_PARM_DESC(debug, "Debug level (0-1)"); 65 66 67struct saa711x_state { 68 struct v4l2_subdev sd; 69 struct v4l2_ctrl_handler hdl; 70 71 struct { 72 /* chroma gain control cluster */ 73 struct v4l2_ctrl *agc; 74 struct v4l2_ctrl *gain; 75 }; 76 77 v4l2_std_id std; 78 int input; 79 int output; 80 int enable; 81 int radio; 82 int width; 83 int height; 84 u32 ident; 85 u32 audclk_freq; 86 u32 crystal_freq; 87 u8 ucgc; 88 u8 cgcdiv; 89 u8 apll; 90}; 91 92static inline struct saa711x_state *to_state(struct v4l2_subdev *sd) 93{ 94 return container_of(sd, struct saa711x_state, sd); 95} 96 97static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl) 98{ 99 return &container_of(ctrl->handler, struct saa711x_state, hdl)->sd; 100} 101 102/* ----------------------------------------------------------------------- */ 103 104static inline int saa711x_write(struct v4l2_subdev *sd, u8 reg, u8 value) 105{ 106 struct i2c_client *client = v4l2_get_subdevdata(sd); 107 108 return i2c_smbus_write_byte_data(client, reg, value); 109} 110 111/* Sanity routine to check if a register is present */ 112static int saa711x_has_reg(const int id, const u8 reg) 113{ 114 if (id == V4L2_IDENT_SAA7111) 115 return reg < 0x20 && reg != 0x01 && reg != 0x0f && 116 (reg < 0x13 || reg > 0x19) && reg != 0x1d && reg != 0x1e; 117 if (id == V4L2_IDENT_SAA7111A) 118 return reg < 0x20 && reg != 0x01 && reg != 0x0f && 119 reg != 0x14 && reg != 0x18 && reg != 0x19 && 120 reg != 0x1d && reg != 0x1e; 121 122 /* common for saa7113/4/5/8 */ 123 if (unlikely((reg >= 0x3b && reg <= 0x3f) || reg == 0x5c || reg == 0x5f || 124 reg == 0xa3 || reg == 0xa7 || reg == 0xab || reg == 0xaf || (reg >= 0xb5 && reg <= 0xb7) || 125 reg == 0xd3 || reg == 0xd7 || reg == 0xdb || reg == 0xdf || (reg >= 0xe5 && reg <= 0xe7) || 126 reg == 0x82 || (reg >= 0x89 && reg <= 0x8e))) 127 return 0; 128 129 switch (id) { 130 case V4L2_IDENT_SAA7113: 131 return reg != 0x14 && (reg < 0x18 || reg > 0x1e) && (reg < 0x20 || reg > 0x3f) && 132 reg != 0x5d && reg < 0x63; 133 case V4L2_IDENT_SAA7114: 134 return (reg < 0x1a || reg > 0x1e) && (reg < 0x20 || reg > 0x2f) && 135 (reg < 0x63 || reg > 0x7f) && reg != 0x33 && reg != 0x37 && 136 reg != 0x81 && reg < 0xf0; 137 case V4L2_IDENT_SAA7115: 138 return (reg < 0x20 || reg > 0x2f) && reg != 0x65 && (reg < 0xfc || reg > 0xfe); 139 case V4L2_IDENT_SAA7118: 140 return (reg < 0x1a || reg > 0x1d) && (reg < 0x20 || reg > 0x22) && 141 (reg < 0x26 || reg > 0x28) && reg != 0x33 && reg != 0x37 && 142 (reg < 0x63 || reg > 0x7f) && reg != 0x81 && reg < 0xf0; 143 } 144 return 1; 145} 146 147static int saa711x_writeregs(struct v4l2_subdev *sd, const unsigned char *regs) 148{ 149 struct saa711x_state *state = to_state(sd); 150 unsigned char reg, data; 151 152 while (*regs != 0x00) { 153 reg = *(regs++); 154 data = *(regs++); 155 156 /* According with datasheets, reserved regs should be 157 filled with 0 - seems better not to touch on they */ 158 if (saa711x_has_reg(state->ident, reg)) { 159 if (saa711x_write(sd, reg, data) < 0) 160 return -1; 161 } else { 162 v4l2_dbg(1, debug, sd, "tried to access reserved reg 0x%02x\n", reg); 163 } 164 } 165 return 0; 166} 167 168static inline int saa711x_read(struct v4l2_subdev *sd, u8 reg) 169{ 170 struct i2c_client *client = v4l2_get_subdevdata(sd); 171 172 return i2c_smbus_read_byte_data(client, reg); 173} 174 175/* ----------------------------------------------------------------------- */ 176 177/* SAA7111 initialization table */ 178static const unsigned char saa7111_init[] = { 179 R_01_INC_DELAY, 0x00, /* reserved */ 180 181 /*front end */ 182 R_02_INPUT_CNTL_1, 0xd0, /* FUSE=3, GUDL=2, MODE=0 */ 183 R_03_INPUT_CNTL_2, 0x23, /* HLNRS=0, VBSL=1, WPOFF=0, HOLDG=0, 184 * GAFIX=0, GAI1=256, GAI2=256 */ 185 R_04_INPUT_CNTL_3, 0x00, /* GAI1=256 */ 186 R_05_INPUT_CNTL_4, 0x00, /* GAI2=256 */ 187 188 /* decoder */ 189 R_06_H_SYNC_START, 0xf3, /* HSB at 13(50Hz) / 17(60Hz) 190 * pixels after end of last line */ 191 R_07_H_SYNC_STOP, 0xe8, /* HSS seems to be needed to 192 * work with NTSC, too */ 193 R_08_SYNC_CNTL, 0xc8, /* AUFD=1, FSEL=1, EXFIL=0, 194 * VTRC=1, HPLL=0, VNOI=0 */ 195 R_09_LUMA_CNTL, 0x01, /* BYPS=0, PREF=0, BPSS=0, 196 * VBLB=0, UPTCV=0, APER=1 */ 197 R_0A_LUMA_BRIGHT_CNTL, 0x80, 198 R_0B_LUMA_CONTRAST_CNTL, 0x47, /* 0b - CONT=1.109 */ 199 R_0C_CHROMA_SAT_CNTL, 0x40, 200 R_0D_CHROMA_HUE_CNTL, 0x00, 201 R_0E_CHROMA_CNTL_1, 0x01, /* 0e - CDTO=0, CSTD=0, DCCF=0, 202 * FCTC=0, CHBW=1 */ 203 R_0F_CHROMA_GAIN_CNTL, 0x00, /* reserved */ 204 R_10_CHROMA_CNTL_2, 0x48, /* 10 - OFTS=1, HDEL=0, VRLN=1, YDEL=0 */ 205 R_11_MODE_DELAY_CNTL, 0x1c, /* 11 - GPSW=0, CM99=0, FECO=0, COMPO=1, 206 * OEYC=1, OEHV=1, VIPB=0, COLO=0 */ 207 R_12_RT_SIGNAL_CNTL, 0x00, /* 12 - output control 2 */ 208 R_13_RT_X_PORT_OUT_CNTL, 0x00, /* 13 - output control 3 */ 209 R_14_ANAL_ADC_COMPAT_CNTL, 0x00, 210 R_15_VGATE_START_FID_CHG, 0x00, 211 R_16_VGATE_STOP, 0x00, 212 R_17_MISC_VGATE_CONF_AND_MSB, 0x00, 213 214 0x00, 0x00 215}; 216 217/* SAA7113 init codes */ 218static const unsigned char saa7113_init[] = { 219 R_01_INC_DELAY, 0x08, 220 R_02_INPUT_CNTL_1, 0xc2, 221 R_03_INPUT_CNTL_2, 0x30, 222 R_04_INPUT_CNTL_3, 0x00, 223 R_05_INPUT_CNTL_4, 0x00, 224 R_06_H_SYNC_START, 0x89, 225 R_07_H_SYNC_STOP, 0x0d, 226 R_08_SYNC_CNTL, 0x88, 227 R_09_LUMA_CNTL, 0x01, 228 R_0A_LUMA_BRIGHT_CNTL, 0x80, 229 R_0B_LUMA_CONTRAST_CNTL, 0x47, 230 R_0C_CHROMA_SAT_CNTL, 0x40, 231 R_0D_CHROMA_HUE_CNTL, 0x00, 232 R_0E_CHROMA_CNTL_1, 0x01, 233 R_0F_CHROMA_GAIN_CNTL, 0x2a, 234 R_10_CHROMA_CNTL_2, 0x08, 235 R_11_MODE_DELAY_CNTL, 0x0c, 236 R_12_RT_SIGNAL_CNTL, 0x07, 237 R_13_RT_X_PORT_OUT_CNTL, 0x00, 238 R_14_ANAL_ADC_COMPAT_CNTL, 0x00, 239 R_15_VGATE_START_FID_CHG, 0x00, 240 R_16_VGATE_STOP, 0x00, 241 R_17_MISC_VGATE_CONF_AND_MSB, 0x00, 242 243 0x00, 0x00 244}; 245 246/* If a value differs from the Hauppauge driver values, then the comment starts with 247 'was 0xXX' to denote the Hauppauge value. Otherwise the value is identical to what the 248 Hauppauge driver sets. */ 249 250/* SAA7114 and SAA7115 initialization table */ 251static const unsigned char saa7115_init_auto_input[] = { 252 /* Front-End Part */ 253 R_01_INC_DELAY, 0x48, /* white peak control disabled */ 254 R_03_INPUT_CNTL_2, 0x20, /* was 0x30. 0x20: long vertical blanking */ 255 R_04_INPUT_CNTL_3, 0x90, /* analog gain set to 0 */ 256 R_05_INPUT_CNTL_4, 0x90, /* analog gain set to 0 */ 257 /* Decoder Part */ 258 R_06_H_SYNC_START, 0xeb, /* horiz sync begin = -21 */ 259 R_07_H_SYNC_STOP, 0xe0, /* horiz sync stop = -17 */ 260 R_09_LUMA_CNTL, 0x53, /* 0x53, was 0x56 for 60hz. luminance control */ 261 R_0A_LUMA_BRIGHT_CNTL, 0x80, /* was 0x88. decoder brightness, 0x80 is itu standard */ 262 R_0B_LUMA_CONTRAST_CNTL, 0x44, /* was 0x48. decoder contrast, 0x44 is itu standard */ 263 R_0C_CHROMA_SAT_CNTL, 0x40, /* was 0x47. decoder saturation, 0x40 is itu standard */ 264 R_0D_CHROMA_HUE_CNTL, 0x00, 265 R_0F_CHROMA_GAIN_CNTL, 0x00, /* use automatic gain */ 266 R_10_CHROMA_CNTL_2, 0x06, /* chroma: active adaptive combfilter */ 267 R_11_MODE_DELAY_CNTL, 0x00, 268 R_12_RT_SIGNAL_CNTL, 0x9d, /* RTS0 output control: VGATE */ 269 R_13_RT_X_PORT_OUT_CNTL, 0x80, /* ITU656 standard mode, RTCO output enable RTCE */ 270 R_14_ANAL_ADC_COMPAT_CNTL, 0x00, 271 R_18_RAW_DATA_GAIN_CNTL, 0x40, /* gain 0x00 = nominal */ 272 R_19_RAW_DATA_OFF_CNTL, 0x80, 273 R_1A_COLOR_KILL_LVL_CNTL, 0x77, /* recommended value */ 274 R_1B_MISC_TVVCRDET, 0x42, /* recommended value */ 275 R_1C_ENHAN_COMB_CTRL1, 0xa9, /* recommended value */ 276 R_1D_ENHAN_COMB_CTRL2, 0x01, /* recommended value */ 277 278 279 R_80_GLOBAL_CNTL_1, 0x0, /* No tasks enabled at init */ 280 281 /* Power Device Control */ 282 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset device */ 283 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* set device programmed, all in operational mode */ 284 0x00, 0x00 285}; 286 287/* Used to reset saa7113, saa7114 and saa7115 */ 288static const unsigned char saa7115_cfg_reset_scaler[] = { 289 R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x00, /* disable I-port output */ 290 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */ 291 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* activate scaler */ 292 R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, /* enable I-port output */ 293 0x00, 0x00 294}; 295 296/* ============== SAA7715 VIDEO templates ============= */ 297 298static const unsigned char saa7115_cfg_60hz_video[] = { 299 R_80_GLOBAL_CNTL_1, 0x00, /* reset tasks */ 300 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */ 301 302 R_15_VGATE_START_FID_CHG, 0x03, 303 R_16_VGATE_STOP, 0x11, 304 R_17_MISC_VGATE_CONF_AND_MSB, 0x9c, 305 306 R_08_SYNC_CNTL, 0x68, /* 0xBO: auto detection, 0x68 = NTSC */ 307 R_0E_CHROMA_CNTL_1, 0x07, /* video autodetection is on */ 308 309 R_5A_V_OFF_FOR_SLICER, 0x06, /* standard 60hz value for ITU656 line counting */ 310 311 /* Task A */ 312 R_90_A_TASK_HANDLING_CNTL, 0x80, 313 R_91_A_X_PORT_FORMATS_AND_CONF, 0x48, 314 R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL, 0x40, 315 R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF, 0x84, 316 317 /* hoffset low (input), 0x0002 is minimum */ 318 R_94_A_HORIZ_INPUT_WINDOW_START, 0x01, 319 R_95_A_HORIZ_INPUT_WINDOW_START_MSB, 0x00, 320 321 /* hsize low (input), 0x02d0 = 720 */ 322 R_96_A_HORIZ_INPUT_WINDOW_LENGTH, 0xd0, 323 R_97_A_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02, 324 325 R_98_A_VERT_INPUT_WINDOW_START, 0x05, 326 R_99_A_VERT_INPUT_WINDOW_START_MSB, 0x00, 327 328 R_9A_A_VERT_INPUT_WINDOW_LENGTH, 0x0c, 329 R_9B_A_VERT_INPUT_WINDOW_LENGTH_MSB, 0x00, 330 331 R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH, 0xa0, 332 R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x05, 333 334 R_9E_A_VERT_OUTPUT_WINDOW_LENGTH, 0x0c, 335 R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x00, 336 337 /* Task B */ 338 R_C0_B_TASK_HANDLING_CNTL, 0x00, 339 R_C1_B_X_PORT_FORMATS_AND_CONF, 0x08, 340 R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION, 0x00, 341 R_C3_B_I_PORT_FORMATS_AND_CONF, 0x80, 342 343 /* 0x0002 is minimum */ 344 R_C4_B_HORIZ_INPUT_WINDOW_START, 0x02, 345 R_C5_B_HORIZ_INPUT_WINDOW_START_MSB, 0x00, 346 347 /* 0x02d0 = 720 */ 348 R_C6_B_HORIZ_INPUT_WINDOW_LENGTH, 0xd0, 349 R_C7_B_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02, 350 351 /* vwindow start 0x12 = 18 */ 352 R_C8_B_VERT_INPUT_WINDOW_START, 0x12, 353 R_C9_B_VERT_INPUT_WINDOW_START_MSB, 0x00, 354 355 /* vwindow length 0xf8 = 248 */ 356 R_CA_B_VERT_INPUT_WINDOW_LENGTH, VRES_60HZ>>1, 357 R_CB_B_VERT_INPUT_WINDOW_LENGTH_MSB, VRES_60HZ>>9, 358 359 /* hwindow 0x02d0 = 720 */ 360 R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0, 361 R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02, 362 363 R_F0_LFCO_PER_LINE, 0xad, /* Set PLL Register. 60hz 525 lines per frame, 27 MHz */ 364 R_F1_P_I_PARAM_SELECT, 0x05, /* low bit with 0xF0 */ 365 R_F5_PULSGEN_LINE_LENGTH, 0xad, 366 R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG, 0x01, 367 368 0x00, 0x00 369}; 370 371static const unsigned char saa7115_cfg_50hz_video[] = { 372 R_80_GLOBAL_CNTL_1, 0x00, 373 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */ 374 375 R_15_VGATE_START_FID_CHG, 0x37, /* VGATE start */ 376 R_16_VGATE_STOP, 0x16, 377 R_17_MISC_VGATE_CONF_AND_MSB, 0x99, 378 379 R_08_SYNC_CNTL, 0x28, /* 0x28 = PAL */ 380 R_0E_CHROMA_CNTL_1, 0x07, 381 382 R_5A_V_OFF_FOR_SLICER, 0x03, /* standard 50hz value */ 383 384 /* Task A */ 385 R_90_A_TASK_HANDLING_CNTL, 0x81, 386 R_91_A_X_PORT_FORMATS_AND_CONF, 0x48, 387 R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL, 0x40, 388 R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF, 0x84, 389 390 /* This is weird: the datasheet says that you should use 2 as the minimum value, */ 391 /* but Hauppauge uses 0, and changing that to 2 causes indeed problems (for 50hz) */ 392 /* hoffset low (input), 0x0002 is minimum */ 393 R_94_A_HORIZ_INPUT_WINDOW_START, 0x00, 394 R_95_A_HORIZ_INPUT_WINDOW_START_MSB, 0x00, 395 396 /* hsize low (input), 0x02d0 = 720 */ 397 R_96_A_HORIZ_INPUT_WINDOW_LENGTH, 0xd0, 398 R_97_A_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02, 399 400 R_98_A_VERT_INPUT_WINDOW_START, 0x03, 401 R_99_A_VERT_INPUT_WINDOW_START_MSB, 0x00, 402 403 /* vsize 0x12 = 18 */ 404 R_9A_A_VERT_INPUT_WINDOW_LENGTH, 0x12, 405 R_9B_A_VERT_INPUT_WINDOW_LENGTH_MSB, 0x00, 406 407 /* hsize 0x05a0 = 1440 */ 408 R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH, 0xa0, 409 R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x05, /* hsize hi (output) */ 410 R_9E_A_VERT_OUTPUT_WINDOW_LENGTH, 0x12, /* vsize low (output), 0x12 = 18 */ 411 R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x00, /* vsize hi (output) */ 412 413 /* Task B */ 414 R_C0_B_TASK_HANDLING_CNTL, 0x00, 415 R_C1_B_X_PORT_FORMATS_AND_CONF, 0x08, 416 R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION, 0x00, 417 R_C3_B_I_PORT_FORMATS_AND_CONF, 0x80, 418 419 /* This is weird: the datasheet says that you should use 2 as the minimum value, */ 420 /* but Hauppauge uses 0, and changing that to 2 causes indeed problems (for 50hz) */ 421 /* hoffset low (input), 0x0002 is minimum. See comment above. */ 422 R_C4_B_HORIZ_INPUT_WINDOW_START, 0x00, 423 R_C5_B_HORIZ_INPUT_WINDOW_START_MSB, 0x00, 424 425 /* hsize 0x02d0 = 720 */ 426 R_C6_B_HORIZ_INPUT_WINDOW_LENGTH, 0xd0, 427 R_C7_B_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02, 428 429 /* voffset 0x16 = 22 */ 430 R_C8_B_VERT_INPUT_WINDOW_START, 0x16, 431 R_C9_B_VERT_INPUT_WINDOW_START_MSB, 0x00, 432 433 /* vsize 0x0120 = 288 */ 434 R_CA_B_VERT_INPUT_WINDOW_LENGTH, 0x20, 435 R_CB_B_VERT_INPUT_WINDOW_LENGTH_MSB, 0x01, 436 437 /* hsize 0x02d0 = 720 */ 438 R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0, 439 R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02, 440 441 R_F0_LFCO_PER_LINE, 0xb0, /* Set PLL Register. 50hz 625 lines per frame, 27 MHz */ 442 R_F1_P_I_PARAM_SELECT, 0x05, /* low bit with 0xF0, (was 0x05) */ 443 R_F5_PULSGEN_LINE_LENGTH, 0xb0, 444 R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG, 0x01, 445 446 0x00, 0x00 447}; 448 449/* ============== SAA7715 VIDEO templates (end) ======= */ 450 451static const unsigned char saa7115_cfg_vbi_on[] = { 452 R_80_GLOBAL_CNTL_1, 0x00, /* reset tasks */ 453 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */ 454 R_80_GLOBAL_CNTL_1, 0x30, /* Activate both tasks */ 455 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* activate scaler */ 456 R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, /* Enable I-port output */ 457 458 0x00, 0x00 459}; 460 461static const unsigned char saa7115_cfg_vbi_off[] = { 462 R_80_GLOBAL_CNTL_1, 0x00, /* reset tasks */ 463 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */ 464 R_80_GLOBAL_CNTL_1, 0x20, /* Activate only task "B" */ 465 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* activate scaler */ 466 R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, /* Enable I-port output */ 467 468 0x00, 0x00 469}; 470 471 472static const unsigned char saa7115_init_misc[] = { 473 R_81_V_SYNC_FLD_ID_SRC_SEL_AND_RETIMED_V_F, 0x01, 474 R_83_X_PORT_I_O_ENA_AND_OUT_CLK, 0x01, 475 R_84_I_PORT_SIGNAL_DEF, 0x20, 476 R_85_I_PORT_SIGNAL_POLAR, 0x21, 477 R_86_I_PORT_FIFO_FLAG_CNTL_AND_ARBIT, 0xc5, 478 R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, 479 480 /* Task A */ 481 R_A0_A_HORIZ_PRESCALING, 0x01, 482 R_A1_A_ACCUMULATION_LENGTH, 0x00, 483 R_A2_A_PRESCALER_DC_GAIN_AND_FIR_PREFILTER, 0x00, 484 485 /* Configure controls at nominal value*/ 486 R_A4_A_LUMA_BRIGHTNESS_CNTL, 0x80, 487 R_A5_A_LUMA_CONTRAST_CNTL, 0x40, 488 R_A6_A_CHROMA_SATURATION_CNTL, 0x40, 489 490 /* note: 2 x zoom ensures that VBI lines have same length as video lines. */ 491 R_A8_A_HORIZ_LUMA_SCALING_INC, 0x00, 492 R_A9_A_HORIZ_LUMA_SCALING_INC_MSB, 0x02, 493 494 R_AA_A_HORIZ_LUMA_PHASE_OFF, 0x00, 495 496 /* must be horiz lum scaling / 2 */ 497 R_AC_A_HORIZ_CHROMA_SCALING_INC, 0x00, 498 R_AD_A_HORIZ_CHROMA_SCALING_INC_MSB, 0x01, 499 500 /* must be offset luma / 2 */ 501 R_AE_A_HORIZ_CHROMA_PHASE_OFF, 0x00, 502 503 R_B0_A_VERT_LUMA_SCALING_INC, 0x00, 504 R_B1_A_VERT_LUMA_SCALING_INC_MSB, 0x04, 505 506 R_B2_A_VERT_CHROMA_SCALING_INC, 0x00, 507 R_B3_A_VERT_CHROMA_SCALING_INC_MSB, 0x04, 508 509 R_B4_A_VERT_SCALING_MODE_CNTL, 0x01, 510 511 R_B8_A_VERT_CHROMA_PHASE_OFF_00, 0x00, 512 R_B9_A_VERT_CHROMA_PHASE_OFF_01, 0x00, 513 R_BA_A_VERT_CHROMA_PHASE_OFF_10, 0x00, 514 R_BB_A_VERT_CHROMA_PHASE_OFF_11, 0x00, 515 516 R_BC_A_VERT_LUMA_PHASE_OFF_00, 0x00, 517 R_BD_A_VERT_LUMA_PHASE_OFF_01, 0x00, 518 R_BE_A_VERT_LUMA_PHASE_OFF_10, 0x00, 519 R_BF_A_VERT_LUMA_PHASE_OFF_11, 0x00, 520 521 /* Task B */ 522 R_D0_B_HORIZ_PRESCALING, 0x01, 523 R_D1_B_ACCUMULATION_LENGTH, 0x00, 524 R_D2_B_PRESCALER_DC_GAIN_AND_FIR_PREFILTER, 0x00, 525 526 /* Configure controls at nominal value*/ 527 R_D4_B_LUMA_BRIGHTNESS_CNTL, 0x80, 528 R_D5_B_LUMA_CONTRAST_CNTL, 0x40, 529 R_D6_B_CHROMA_SATURATION_CNTL, 0x40, 530 531 /* hor lum scaling 0x0400 = 1 */ 532 R_D8_B_HORIZ_LUMA_SCALING_INC, 0x00, 533 R_D9_B_HORIZ_LUMA_SCALING_INC_MSB, 0x04, 534 535 R_DA_B_HORIZ_LUMA_PHASE_OFF, 0x00, 536 537 /* must be hor lum scaling / 2 */ 538 R_DC_B_HORIZ_CHROMA_SCALING, 0x00, 539 R_DD_B_HORIZ_CHROMA_SCALING_MSB, 0x02, 540 541 /* must be offset luma / 2 */ 542 R_DE_B_HORIZ_PHASE_OFFSET_CRHOMA, 0x00, 543 544 R_E0_B_VERT_LUMA_SCALING_INC, 0x00, 545 R_E1_B_VERT_LUMA_SCALING_INC_MSB, 0x04, 546 547 R_E2_B_VERT_CHROMA_SCALING_INC, 0x00, 548 R_E3_B_VERT_CHROMA_SCALING_INC_MSB, 0x04, 549 550 R_E4_B_VERT_SCALING_MODE_CNTL, 0x01, 551 552 R_E8_B_VERT_CHROMA_PHASE_OFF_00, 0x00, 553 R_E9_B_VERT_CHROMA_PHASE_OFF_01, 0x00, 554 R_EA_B_VERT_CHROMA_PHASE_OFF_10, 0x00, 555 R_EB_B_VERT_CHROMA_PHASE_OFF_11, 0x00, 556 557 R_EC_B_VERT_LUMA_PHASE_OFF_00, 0x00, 558 R_ED_B_VERT_LUMA_PHASE_OFF_01, 0x00, 559 R_EE_B_VERT_LUMA_PHASE_OFF_10, 0x00, 560 R_EF_B_VERT_LUMA_PHASE_OFF_11, 0x00, 561 562 R_F2_NOMINAL_PLL2_DTO, 0x50, /* crystal clock = 24.576 MHz, target = 27MHz */ 563 R_F3_PLL_INCREMENT, 0x46, 564 R_F4_PLL2_STATUS, 0x00, 565 R_F7_PULSE_A_POS_MSB, 0x4b, /* not the recommended settings! */ 566 R_F8_PULSE_B_POS, 0x00, 567 R_F9_PULSE_B_POS_MSB, 0x4b, 568 R_FA_PULSE_C_POS, 0x00, 569 R_FB_PULSE_C_POS_MSB, 0x4b, 570 571 /* PLL2 lock detection settings: 71 lines 50% phase error */ 572 R_FF_S_PLL_MAX_PHASE_ERR_THRESH_NUM_LINES, 0x88, 573 574 /* Turn off VBI */ 575 R_40_SLICER_CNTL_1, 0x20, /* No framing code errors allowed. */ 576 R_41_LCR_BASE, 0xff, 577 R_41_LCR_BASE+1, 0xff, 578 R_41_LCR_BASE+2, 0xff, 579 R_41_LCR_BASE+3, 0xff, 580 R_41_LCR_BASE+4, 0xff, 581 R_41_LCR_BASE+5, 0xff, 582 R_41_LCR_BASE+6, 0xff, 583 R_41_LCR_BASE+7, 0xff, 584 R_41_LCR_BASE+8, 0xff, 585 R_41_LCR_BASE+9, 0xff, 586 R_41_LCR_BASE+10, 0xff, 587 R_41_LCR_BASE+11, 0xff, 588 R_41_LCR_BASE+12, 0xff, 589 R_41_LCR_BASE+13, 0xff, 590 R_41_LCR_BASE+14, 0xff, 591 R_41_LCR_BASE+15, 0xff, 592 R_41_LCR_BASE+16, 0xff, 593 R_41_LCR_BASE+17, 0xff, 594 R_41_LCR_BASE+18, 0xff, 595 R_41_LCR_BASE+19, 0xff, 596 R_41_LCR_BASE+20, 0xff, 597 R_41_LCR_BASE+21, 0xff, 598 R_41_LCR_BASE+22, 0xff, 599 R_58_PROGRAM_FRAMING_CODE, 0x40, 600 R_59_H_OFF_FOR_SLICER, 0x47, 601 R_5B_FLD_OFF_AND_MSB_FOR_H_AND_V_OFF, 0x83, 602 R_5D_DID, 0xbd, 603 R_5E_SDID, 0x35, 604 605 R_02_INPUT_CNTL_1, 0xc4, /* input tuner -> input 4, amplifier active */ 606 607 R_80_GLOBAL_CNTL_1, 0x20, /* enable task B */ 608 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, 609 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, 610 0x00, 0x00 611}; 612 613static int saa711x_odd_parity(u8 c) 614{ 615 c ^= (c >> 4); 616 c ^= (c >> 2); 617 c ^= (c >> 1); 618 619 return c & 1; 620} 621 622static int saa711x_decode_vps(u8 *dst, u8 *p) 623{ 624 static const u8 biphase_tbl[] = { 625 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4, 626 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0, 627 0xd2, 0x5a, 0x52, 0xd2, 0x96, 0x1e, 0x16, 0x96, 628 0x92, 0x1a, 0x12, 0x92, 0xd2, 0x5a, 0x52, 0xd2, 629 0xd0, 0x58, 0x50, 0xd0, 0x94, 0x1c, 0x14, 0x94, 630 0x90, 0x18, 0x10, 0x90, 0xd0, 0x58, 0x50, 0xd0, 631 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4, 632 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0, 633 0xe1, 0x69, 0x61, 0xe1, 0xa5, 0x2d, 0x25, 0xa5, 634 0xa1, 0x29, 0x21, 0xa1, 0xe1, 0x69, 0x61, 0xe1, 635 0xc3, 0x4b, 0x43, 0xc3, 0x87, 0x0f, 0x07, 0x87, 636 0x83, 0x0b, 0x03, 0x83, 0xc3, 0x4b, 0x43, 0xc3, 637 0xc1, 0x49, 0x41, 0xc1, 0x85, 0x0d, 0x05, 0x85, 638 0x81, 0x09, 0x01, 0x81, 0xc1, 0x49, 0x41, 0xc1, 639 0xe1, 0x69, 0x61, 0xe1, 0xa5, 0x2d, 0x25, 0xa5, 640 0xa1, 0x29, 0x21, 0xa1, 0xe1, 0x69, 0x61, 0xe1, 641 0xe0, 0x68, 0x60, 0xe0, 0xa4, 0x2c, 0x24, 0xa4, 642 0xa0, 0x28, 0x20, 0xa0, 0xe0, 0x68, 0x60, 0xe0, 643 0xc2, 0x4a, 0x42, 0xc2, 0x86, 0x0e, 0x06, 0x86, 644 0x82, 0x0a, 0x02, 0x82, 0xc2, 0x4a, 0x42, 0xc2, 645 0xc0, 0x48, 0x40, 0xc0, 0x84, 0x0c, 0x04, 0x84, 646 0x80, 0x08, 0x00, 0x80, 0xc0, 0x48, 0x40, 0xc0, 647 0xe0, 0x68, 0x60, 0xe0, 0xa4, 0x2c, 0x24, 0xa4, 648 0xa0, 0x28, 0x20, 0xa0, 0xe0, 0x68, 0x60, 0xe0, 649 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4, 650 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0, 651 0xd2, 0x5a, 0x52, 0xd2, 0x96, 0x1e, 0x16, 0x96, 652 0x92, 0x1a, 0x12, 0x92, 0xd2, 0x5a, 0x52, 0xd2, 653 0xd0, 0x58, 0x50, 0xd0, 0x94, 0x1c, 0x14, 0x94, 654 0x90, 0x18, 0x10, 0x90, 0xd0, 0x58, 0x50, 0xd0, 655 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4, 656 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0, 657 }; 658 int i; 659 u8 c, err = 0; 660 661 for (i = 0; i < 2 * 13; i += 2) { 662 err |= biphase_tbl[p[i]] | biphase_tbl[p[i + 1]]; 663 c = (biphase_tbl[p[i + 1]] & 0xf) | ((biphase_tbl[p[i]] & 0xf) << 4); 664 dst[i / 2] = c; 665 } 666 return err & 0xf0; 667} 668 669static int saa711x_decode_wss(u8 *p) 670{ 671 static const int wss_bits[8] = { 672 0, 0, 0, 1, 0, 1, 1, 1 673 }; 674 unsigned char parity; 675 int wss = 0; 676 int i; 677 678 for (i = 0; i < 16; i++) { 679 int b1 = wss_bits[p[i] & 7]; 680 int b2 = wss_bits[(p[i] >> 3) & 7]; 681 682 if (b1 == b2) 683 return -1; 684 wss |= b2 << i; 685 } 686 parity = wss & 15; 687 parity ^= parity >> 2; 688 parity ^= parity >> 1; 689 690 if (!(parity & 1)) 691 return -1; 692 693 return wss; 694} 695 696static int saa711x_s_clock_freq(struct v4l2_subdev *sd, u32 freq) 697{ 698 struct saa711x_state *state = to_state(sd); 699 u32 acpf; 700 u32 acni; 701 u32 hz; 702 u64 f; 703 u8 acc = 0; /* reg 0x3a, audio clock control */ 704 705 /* Checks for chips that don't have audio clock (saa7111, saa7113) */ 706 if (!saa711x_has_reg(state->ident, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD)) 707 return 0; 708 709 v4l2_dbg(1, debug, sd, "set audio clock freq: %d\n", freq); 710 711 /* sanity check */ 712 if (freq < 32000 || freq > 48000) 713 return -EINVAL; 714 715 /* hz is the refresh rate times 100 */ 716 hz = (state->std & V4L2_STD_525_60) ? 5994 : 5000; 717 /* acpf = (256 * freq) / field_frequency == (256 * 100 * freq) / hz */ 718 acpf = (25600 * freq) / hz; 719 /* acni = (256 * freq * 2^23) / crystal_frequency = 720 (freq * 2^(8+23)) / crystal_frequency = 721 (freq << 31) / crystal_frequency */ 722 f = freq; 723 f = f << 31; 724 do_div(f, state->crystal_freq); 725 acni = f; 726 if (state->ucgc) { 727 acpf = acpf * state->cgcdiv / 16; 728 acni = acni * state->cgcdiv / 16; 729 acc = 0x80; 730 if (state->cgcdiv == 3) 731 acc |= 0x40; 732 } 733 if (state->apll) 734 acc |= 0x08; 735 736 saa711x_write(sd, R_38_CLK_RATIO_AMXCLK_TO_ASCLK, 0x03); 737 saa711x_write(sd, R_39_CLK_RATIO_ASCLK_TO_ALRCLK, 0x10); 738 saa711x_write(sd, R_3A_AUD_CLK_GEN_BASIC_SETUP, acc); 739 740 saa711x_write(sd, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD, acpf & 0xff); 741 saa711x_write(sd, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD+1, 742 (acpf >> 8) & 0xff); 743 saa711x_write(sd, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD+2, 744 (acpf >> 16) & 0x03); 745 746 saa711x_write(sd, R_34_AUD_MAST_CLK_NOMINAL_INC, acni & 0xff); 747 saa711x_write(sd, R_34_AUD_MAST_CLK_NOMINAL_INC+1, (acni >> 8) & 0xff); 748 saa711x_write(sd, R_34_AUD_MAST_CLK_NOMINAL_INC+2, (acni >> 16) & 0x3f); 749 state->audclk_freq = freq; 750 return 0; 751} 752 753static int saa711x_g_volatile_ctrl(struct v4l2_ctrl *ctrl) 754{ 755 struct v4l2_subdev *sd = to_sd(ctrl); 756 struct saa711x_state *state = to_state(sd); 757 758 switch (ctrl->id) { 759 case V4L2_CID_CHROMA_AGC: 760 /* chroma gain cluster */ 761 if (state->agc->cur.val) 762 state->gain->cur.val = 763 saa711x_read(sd, R_0F_CHROMA_GAIN_CNTL) & 0x7f; 764 break; 765 } 766 return 0; 767} 768 769static int saa711x_s_ctrl(struct v4l2_ctrl *ctrl) 770{ 771 struct v4l2_subdev *sd = to_sd(ctrl); 772 struct saa711x_state *state = to_state(sd); 773 774 switch (ctrl->id) { 775 case V4L2_CID_BRIGHTNESS: 776 saa711x_write(sd, R_0A_LUMA_BRIGHT_CNTL, ctrl->val); 777 break; 778 779 case V4L2_CID_CONTRAST: 780 saa711x_write(sd, R_0B_LUMA_CONTRAST_CNTL, ctrl->val); 781 break; 782 783 case V4L2_CID_SATURATION: 784 saa711x_write(sd, R_0C_CHROMA_SAT_CNTL, ctrl->val); 785 break; 786 787 case V4L2_CID_HUE: 788 saa711x_write(sd, R_0D_CHROMA_HUE_CNTL, ctrl->val); 789 break; 790 791 case V4L2_CID_CHROMA_AGC: 792 /* chroma gain cluster */ 793 if (state->agc->val) 794 saa711x_write(sd, R_0F_CHROMA_GAIN_CNTL, state->gain->val); 795 else 796 saa711x_write(sd, R_0F_CHROMA_GAIN_CNTL, state->gain->val | 0x80); 797 v4l2_ctrl_activate(state->gain, !state->agc->val); 798 break; 799 800 default: 801 return -EINVAL; 802 } 803 804 return 0; 805} 806 807static int saa711x_set_size(struct v4l2_subdev *sd, int width, int height) 808{ 809 struct saa711x_state *state = to_state(sd); 810 int HPSC, HFSC; 811 int VSCY; 812 int res; 813 int is_50hz = state->std & V4L2_STD_625_50; 814 int Vsrc = is_50hz ? 576 : 480; 815 816 v4l2_dbg(1, debug, sd, "decoder set size to %ix%i\n", width, height); 817 818 if ((width < 1) || (width > 1440)) 819 return -EINVAL; 820 if ((height < 1) || (height > Vsrc)) 821 return -EINVAL; 822 823 if (!saa711x_has_reg(state->ident, R_D0_B_HORIZ_PRESCALING)) { 824 /* Decoder only supports 720 columns and 480 or 576 lines */ 825 if (width != 720) 826 return -EINVAL; 827 if (height != Vsrc) 828 return -EINVAL; 829 } 830 831 state->width = width; 832 state->height = height; 833 834 if (!saa711x_has_reg(state->ident, R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH)) 835 return 0; 836 837 /* probably have a valid size, let's set it */ 838 /* Set output width/height */ 839 /* width */ 840 841 saa711x_write(sd, R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 842 (u8) (width & 0xff)); 843 saa711x_write(sd, R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 844 (u8) ((width >> 8) & 0xff)); 845 846 /* Vertical Scaling uses height/2 */ 847 res = height / 2; 848 849 /* On 60Hz, it is using a higher Vertical Output Size */ 850 if (!is_50hz) 851 res += (VRES_60HZ - 480) >> 1; 852 853 /* height */ 854 saa711x_write(sd, R_CE_B_VERT_OUTPUT_WINDOW_LENGTH, 855 (u8) (res & 0xff)); 856 saa711x_write(sd, R_CF_B_VERT_OUTPUT_WINDOW_LENGTH_MSB, 857 (u8) ((res >> 8) & 0xff)); 858 859 /* Scaling settings */ 860 /* Hprescaler is floor(inres/outres) */ 861 HPSC = (int)(720 / width); 862 /* 0 is not allowed (div. by zero) */ 863 HPSC = HPSC ? HPSC : 1; 864 HFSC = (int)((1024 * 720) / (HPSC * width)); 865 saa711x_write(sd, R_D0_B_HORIZ_PRESCALING, 866 (u8) (HPSC & 0x3f)); 867 868 v4l2_dbg(1, debug, sd, "Hpsc: 0x%05x, Hfsc: 0x%05x\n", HPSC, HFSC); 869 /* write H fine-scaling (luminance) */ 870 saa711x_write(sd, R_D8_B_HORIZ_LUMA_SCALING_INC, 871 (u8) (HFSC & 0xff)); 872 saa711x_write(sd, R_D9_B_HORIZ_LUMA_SCALING_INC_MSB, 873 (u8) ((HFSC >> 8) & 0xff)); 874 /* write H fine-scaling (chrominance) 875 * must be lum/2, so i'll just bitshift :) */ 876 saa711x_write(sd, R_DC_B_HORIZ_CHROMA_SCALING, 877 (u8) ((HFSC >> 1) & 0xff)); 878 saa711x_write(sd, R_DD_B_HORIZ_CHROMA_SCALING_MSB, 879 (u8) ((HFSC >> 9) & 0xff)); 880 881 VSCY = (int)((1024 * Vsrc) / height); 882 v4l2_dbg(1, debug, sd, "Vsrc: %d, Vscy: 0x%05x\n", Vsrc, VSCY); 883 884 /* Correct Contrast and Luminance */ 885 saa711x_write(sd, R_D5_B_LUMA_CONTRAST_CNTL, 886 (u8) (64 * 1024 / VSCY)); 887 saa711x_write(sd, R_D6_B_CHROMA_SATURATION_CNTL, 888 (u8) (64 * 1024 / VSCY)); 889 890 /* write V fine-scaling (luminance) */ 891 saa711x_write(sd, R_E0_B_VERT_LUMA_SCALING_INC, 892 (u8) (VSCY & 0xff)); 893 saa711x_write(sd, R_E1_B_VERT_LUMA_SCALING_INC_MSB, 894 (u8) ((VSCY >> 8) & 0xff)); 895 /* write V fine-scaling (chrominance) */ 896 saa711x_write(sd, R_E2_B_VERT_CHROMA_SCALING_INC, 897 (u8) (VSCY & 0xff)); 898 saa711x_write(sd, R_E3_B_VERT_CHROMA_SCALING_INC_MSB, 899 (u8) ((VSCY >> 8) & 0xff)); 900 901 saa711x_writeregs(sd, saa7115_cfg_reset_scaler); 902 903 /* Activates task "B" */ 904 saa711x_write(sd, R_80_GLOBAL_CNTL_1, 905 saa711x_read(sd, R_80_GLOBAL_CNTL_1) | 0x20); 906 907 return 0; 908} 909 910static void saa711x_set_v4lstd(struct v4l2_subdev *sd, v4l2_std_id std) 911{ 912 struct saa711x_state *state = to_state(sd); 913 914 /* Prevent unnecessary standard changes. During a standard 915 change the I-Port is temporarily disabled. Any devices 916 reading from that port can get confused. 917 Note that s_std is also used to switch from 918 radio to TV mode, so if a s_std is broadcast to 919 all I2C devices then you do not want to have an unwanted 920 side-effect here. */ 921 if (std == state->std) 922 return; 923 924 state->std = std; 925 926 // This works for NTSC-M, SECAM-L and the 50Hz PAL variants. 927 if (std & V4L2_STD_525_60) { 928 v4l2_dbg(1, debug, sd, "decoder set standard 60 Hz\n"); 929 saa711x_writeregs(sd, saa7115_cfg_60hz_video); 930 saa711x_set_size(sd, 720, 480); 931 } else { 932 v4l2_dbg(1, debug, sd, "decoder set standard 50 Hz\n"); 933 saa711x_writeregs(sd, saa7115_cfg_50hz_video); 934 saa711x_set_size(sd, 720, 576); 935 } 936 937 /* Register 0E - Bits D6-D4 on NO-AUTO mode 938 (SAA7111 and SAA7113 doesn't have auto mode) 939 50 Hz / 625 lines 60 Hz / 525 lines 940 000 PAL BGDHI (4.43Mhz) NTSC M (3.58MHz) 941 001 NTSC 4.43 (50 Hz) PAL 4.43 (60 Hz) 942 010 Combination-PAL N (3.58MHz) NTSC 4.43 (60 Hz) 943 011 NTSC N (3.58MHz) PAL M (3.58MHz) 944 100 reserved NTSC-Japan (3.58MHz) 945 */ 946 if (state->ident <= V4L2_IDENT_SAA7113) { 947 u8 reg = saa711x_read(sd, R_0E_CHROMA_CNTL_1) & 0x8f; 948 949 if (std == V4L2_STD_PAL_M) { 950 reg |= 0x30; 951 } else if (std == V4L2_STD_PAL_Nc) { 952 reg |= 0x20; 953 } else if (std == V4L2_STD_PAL_60) { 954 reg |= 0x10; 955 } else if (std == V4L2_STD_NTSC_M_JP) { 956 reg |= 0x40; 957 } else if (std & V4L2_STD_SECAM) { 958 reg |= 0x50; 959 } 960 saa711x_write(sd, R_0E_CHROMA_CNTL_1, reg); 961 } else { 962 /* restart task B if needed */ 963 int taskb = saa711x_read(sd, R_80_GLOBAL_CNTL_1) & 0x10; 964 965 if (taskb && state->ident == V4L2_IDENT_SAA7114) { 966 saa711x_writeregs(sd, saa7115_cfg_vbi_on); 967 } 968 969 /* switch audio mode too! */ 970 saa711x_s_clock_freq(sd, state->audclk_freq); 971 } 972} 973 974/* setup the sliced VBI lcr registers according to the sliced VBI format */ 975static void saa711x_set_lcr(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *fmt) 976{ 977 struct saa711x_state *state = to_state(sd); 978 int is_50hz = (state->std & V4L2_STD_625_50); 979 u8 lcr[24]; 980 int i, x; 981 982 /* saa7113/7114/7118 VBI support are experimental */ 983 if (!saa711x_has_reg(state->ident, R_41_LCR_BASE)) 984 return; 985 986 for (i = 0; i <= 23; i++) 987 lcr[i] = 0xff; 988 989 if (fmt == NULL) { 990 /* raw VBI */ 991 if (is_50hz) 992 for (i = 6; i <= 23; i++) 993 lcr[i] = 0xdd; 994 else 995 for (i = 10; i <= 21; i++) 996 lcr[i] = 0xdd; 997 } else { 998 /* sliced VBI */ 999 /* first clear lines that cannot be captured */ 1000 if (is_50hz) { 1001 for (i = 0; i <= 5; i++) 1002 fmt->service_lines[0][i] = 1003 fmt->service_lines[1][i] = 0; 1004 } 1005 else { 1006 for (i = 0; i <= 9; i++) 1007 fmt->service_lines[0][i] = 1008 fmt->service_lines[1][i] = 0; 1009 for (i = 22; i <= 23; i++) 1010 fmt->service_lines[0][i] = 1011 fmt->service_lines[1][i] = 0; 1012 } 1013 1014 /* Now set the lcr values according to the specified service */ 1015 for (i = 6; i <= 23; i++) { 1016 lcr[i] = 0; 1017 for (x = 0; x <= 1; x++) { 1018 switch (fmt->service_lines[1-x][i]) { 1019 case 0: 1020 lcr[i] |= 0xf << (4 * x); 1021 break; 1022 case V4L2_SLICED_TELETEXT_B: 1023 lcr[i] |= 1 << (4 * x); 1024 break; 1025 case V4L2_SLICED_CAPTION_525: 1026 lcr[i] |= 4 << (4 * x); 1027 break; 1028 case V4L2_SLICED_WSS_625: 1029 lcr[i] |= 5 << (4 * x); 1030 break; 1031 case V4L2_SLICED_VPS: 1032 lcr[i] |= 7 << (4 * x); 1033 break; 1034 } 1035 } 1036 } 1037 } 1038 1039 /* write the lcr registers */ 1040 for (i = 2; i <= 23; i++) { 1041 saa711x_write(sd, i - 2 + R_41_LCR_BASE, lcr[i]); 1042 } 1043 1044 /* enable/disable raw VBI capturing */ 1045 saa711x_writeregs(sd, fmt == NULL ? 1046 saa7115_cfg_vbi_on : 1047 saa7115_cfg_vbi_off); 1048} 1049 1050static int saa711x_g_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *sliced) 1051{ 1052 static u16 lcr2vbi[] = { 1053 0, V4L2_SLICED_TELETEXT_B, 0, /* 1 */ 1054 0, V4L2_SLICED_CAPTION_525, /* 4 */ 1055 V4L2_SLICED_WSS_625, 0, /* 5 */ 1056 V4L2_SLICED_VPS, 0, 0, 0, 0, /* 7 */ 1057 0, 0, 0, 0 1058 }; 1059 int i; 1060 1061 memset(sliced, 0, sizeof(*sliced)); 1062 /* done if using raw VBI */ 1063 if (saa711x_read(sd, R_80_GLOBAL_CNTL_1) & 0x10) 1064 return 0; 1065 for (i = 2; i <= 23; i++) { 1066 u8 v = saa711x_read(sd, i - 2 + R_41_LCR_BASE); 1067 1068 sliced->service_lines[0][i] = lcr2vbi[v >> 4]; 1069 sliced->service_lines[1][i] = lcr2vbi[v & 0xf]; 1070 sliced->service_set |= 1071 sliced->service_lines[0][i] | sliced->service_lines[1][i]; 1072 } 1073 return 0; 1074} 1075 1076static int saa711x_s_raw_fmt(struct v4l2_subdev *sd, struct v4l2_vbi_format *fmt) 1077{ 1078 saa711x_set_lcr(sd, NULL); 1079 return 0; 1080} 1081 1082static int saa711x_s_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *fmt) 1083{ 1084 saa711x_set_lcr(sd, fmt); 1085 return 0; 1086} 1087 1088static int saa711x_s_mbus_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *fmt) 1089{ 1090 if (fmt->code != V4L2_MBUS_FMT_FIXED) 1091 return -EINVAL; 1092 fmt->field = V4L2_FIELD_INTERLACED; 1093 fmt->colorspace = V4L2_COLORSPACE_SMPTE170M; 1094 return saa711x_set_size(sd, fmt->width, fmt->height); 1095} 1096 1097/* Decode the sliced VBI data stream as created by the saa7115. 1098 The format is described in the saa7115 datasheet in Tables 25 and 26 1099 and in Figure 33. 1100 The current implementation uses SAV/EAV codes and not the ancillary data 1101 headers. The vbi->p pointer points to the R_5E_SDID byte right after the SAV 1102 code. */ 1103static int saa711x_decode_vbi_line(struct v4l2_subdev *sd, struct v4l2_decode_vbi_line *vbi) 1104{ 1105 struct saa711x_state *state = to_state(sd); 1106 static const char vbi_no_data_pattern[] = { 1107 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0 1108 }; 1109 u8 *p = vbi->p; 1110 u32 wss; 1111 int id1, id2; /* the ID1 and ID2 bytes from the internal header */ 1112 1113 vbi->type = 0; /* mark result as a failure */ 1114 id1 = p[2]; 1115 id2 = p[3]; 1116 /* Note: the field bit is inverted for 60 Hz video */ 1117 if (state->std & V4L2_STD_525_60) 1118 id1 ^= 0x40; 1119 1120 /* Skip internal header, p now points to the start of the payload */ 1121 p += 4; 1122 vbi->p = p; 1123 1124 /* calculate field and line number of the VBI packet (1-23) */ 1125 vbi->is_second_field = ((id1 & 0x40) != 0); 1126 vbi->line = (id1 & 0x3f) << 3; 1127 vbi->line |= (id2 & 0x70) >> 4; 1128 1129 /* Obtain data type */ 1130 id2 &= 0xf; 1131 1132 /* If the VBI slicer does not detect any signal it will fill up 1133 the payload buffer with 0xa0 bytes. */ 1134 if (!memcmp(p, vbi_no_data_pattern, sizeof(vbi_no_data_pattern))) 1135 return 0; 1136 1137 /* decode payloads */ 1138 switch (id2) { 1139 case 1: 1140 vbi->type = V4L2_SLICED_TELETEXT_B; 1141 break; 1142 case 4: 1143 if (!saa711x_odd_parity(p[0]) || !saa711x_odd_parity(p[1])) 1144 return 0; 1145 vbi->type = V4L2_SLICED_CAPTION_525; 1146 break; 1147 case 5: 1148 wss = saa711x_decode_wss(p); 1149 if (wss == -1) 1150 return 0; 1151 p[0] = wss & 0xff; 1152 p[1] = wss >> 8; 1153 vbi->type = V4L2_SLICED_WSS_625; 1154 break; 1155 case 7: 1156 if (saa711x_decode_vps(p, p) != 0) 1157 return 0; 1158 vbi->type = V4L2_SLICED_VPS; 1159 break; 1160 default: 1161 break; 1162 } 1163 return 0; 1164} 1165 1166/* ============ SAA7115 AUDIO settings (end) ============= */ 1167 1168static int saa711x_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt) 1169{ 1170 struct saa711x_state *state = to_state(sd); 1171 int status; 1172 1173 if (state->radio) 1174 return 0; 1175 status = saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC); 1176 1177 v4l2_dbg(1, debug, sd, "status: 0x%02x\n", status); 1178 vt->signal = ((status & (1 << 6)) == 0) ? 0xffff : 0x0; 1179 return 0; 1180} 1181 1182static int saa711x_s_std(struct v4l2_subdev *sd, v4l2_std_id std) 1183{ 1184 struct saa711x_state *state = to_state(sd); 1185 1186 state->radio = 0; 1187 saa711x_set_v4lstd(sd, std); 1188 return 0; 1189} 1190 1191static int saa711x_s_radio(struct v4l2_subdev *sd) 1192{ 1193 struct saa711x_state *state = to_state(sd); 1194 1195 state->radio = 1; 1196 return 0; 1197} 1198 1199static int saa711x_s_routing(struct v4l2_subdev *sd, 1200 u32 input, u32 output, u32 config) 1201{ 1202 struct saa711x_state *state = to_state(sd); 1203 u8 mask = (state->ident <= V4L2_IDENT_SAA7111A) ? 0xf8 : 0xf0; 1204 1205 v4l2_dbg(1, debug, sd, "decoder set input %d output %d\n", 1206 input, output); 1207 1208 /* saa7111/3 does not have these inputs */ 1209 if (state->ident <= V4L2_IDENT_SAA7113 && 1210 (input == SAA7115_COMPOSITE4 || 1211 input == SAA7115_COMPOSITE5)) { 1212 return -EINVAL; 1213 } 1214 if (input > SAA7115_SVIDEO3) 1215 return -EINVAL; 1216 if (state->input == input && state->output == output) 1217 return 0; 1218 v4l2_dbg(1, debug, sd, "now setting %s input %s output\n", 1219 (input >= SAA7115_SVIDEO0) ? "S-Video" : "Composite", 1220 (output == SAA7115_IPORT_ON) ? "iport on" : "iport off"); 1221 state->input = input; 1222 1223 /* saa7111 has slightly different input numbering */ 1224 if (state->ident <= V4L2_IDENT_SAA7111A) { 1225 if (input >= SAA7115_COMPOSITE4) 1226 input -= 2; 1227 /* saa7111 specific */ 1228 saa711x_write(sd, R_10_CHROMA_CNTL_2, 1229 (saa711x_read(sd, R_10_CHROMA_CNTL_2) & 0x3f) | 1230 ((output & 0xc0) ^ 0x40)); 1231 saa711x_write(sd, R_13_RT_X_PORT_OUT_CNTL, 1232 (saa711x_read(sd, R_13_RT_X_PORT_OUT_CNTL) & 0xf0) | 1233 ((output & 2) ? 0x0a : 0)); 1234 } 1235 1236 /* select mode */ 1237 saa711x_write(sd, R_02_INPUT_CNTL_1, 1238 (saa711x_read(sd, R_02_INPUT_CNTL_1) & mask) | 1239 input); 1240 1241 /* bypass chrominance trap for S-Video modes */ 1242 saa711x_write(sd, R_09_LUMA_CNTL, 1243 (saa711x_read(sd, R_09_LUMA_CNTL) & 0x7f) | 1244 (state->input >= SAA7115_SVIDEO0 ? 0x80 : 0x0)); 1245 1246 state->output = output; 1247 if (state->ident == V4L2_IDENT_SAA7114 || 1248 state->ident == V4L2_IDENT_SAA7115) { 1249 saa711x_write(sd, R_83_X_PORT_I_O_ENA_AND_OUT_CLK, 1250 (saa711x_read(sd, R_83_X_PORT_I_O_ENA_AND_OUT_CLK) & 0xfe) | 1251 (state->output & 0x01)); 1252 } 1253 return 0; 1254} 1255 1256static int saa711x_s_gpio(struct v4l2_subdev *sd, u32 val) 1257{ 1258 struct saa711x_state *state = to_state(sd); 1259 1260 if (state->ident > V4L2_IDENT_SAA7111A) 1261 return -EINVAL; 1262 saa711x_write(sd, 0x11, (saa711x_read(sd, 0x11) & 0x7f) | 1263 (val ? 0x80 : 0)); 1264 return 0; 1265} 1266 1267static int saa711x_s_stream(struct v4l2_subdev *sd, int enable) 1268{ 1269 struct saa711x_state *state = to_state(sd); 1270 1271 v4l2_dbg(1, debug, sd, "%s output\n", 1272 enable ? "enable" : "disable"); 1273 1274 if (state->enable == enable) 1275 return 0; 1276 state->enable = enable; 1277 if (!saa711x_has_reg(state->ident, R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED)) 1278 return 0; 1279 saa711x_write(sd, R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, state->enable); 1280 return 0; 1281} 1282 1283static int saa711x_s_crystal_freq(struct v4l2_subdev *sd, u32 freq, u32 flags) 1284{ 1285 struct saa711x_state *state = to_state(sd); 1286 1287 if (freq != SAA7115_FREQ_32_11_MHZ && freq != SAA7115_FREQ_24_576_MHZ) 1288 return -EINVAL; 1289 state->crystal_freq = freq; 1290 state->cgcdiv = (flags & SAA7115_FREQ_FL_CGCDIV) ? 3 : 4; 1291 state->ucgc = (flags & SAA7115_FREQ_FL_UCGC) ? 1 : 0; 1292 state->apll = (flags & SAA7115_FREQ_FL_APLL) ? 1 : 0; 1293 saa711x_s_clock_freq(sd, state->audclk_freq); 1294 return 0; 1295} 1296 1297static int saa711x_reset(struct v4l2_subdev *sd, u32 val) 1298{ 1299 v4l2_dbg(1, debug, sd, "decoder RESET\n"); 1300 saa711x_writeregs(sd, saa7115_cfg_reset_scaler); 1301 return 0; 1302} 1303 1304static int saa711x_g_vbi_data(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_data *data) 1305{ 1306 /* Note: the internal field ID is inverted for NTSC, 1307 so data->field 0 maps to the saa7115 even field, 1308 whereas for PAL it maps to the saa7115 odd field. */ 1309 switch (data->id) { 1310 case V4L2_SLICED_WSS_625: 1311 if (saa711x_read(sd, 0x6b) & 0xc0) 1312 return -EIO; 1313 data->data[0] = saa711x_read(sd, 0x6c); 1314 data->data[1] = saa711x_read(sd, 0x6d); 1315 return 0; 1316 case V4L2_SLICED_CAPTION_525: 1317 if (data->field == 0) { 1318 /* CC */ 1319 if (saa711x_read(sd, 0x66) & 0x30) 1320 return -EIO; 1321 data->data[0] = saa711x_read(sd, 0x69); 1322 data->data[1] = saa711x_read(sd, 0x6a); 1323 return 0; 1324 } 1325 /* XDS */ 1326 if (saa711x_read(sd, 0x66) & 0xc0) 1327 return -EIO; 1328 data->data[0] = saa711x_read(sd, 0x67); 1329 data->data[1] = saa711x_read(sd, 0x68); 1330 return 0; 1331 default: 1332 return -EINVAL; 1333 } 1334} 1335 1336static int saa711x_querystd(struct v4l2_subdev *sd, v4l2_std_id *std) 1337{ 1338 struct saa711x_state *state = to_state(sd); 1339 int reg1e; 1340 1341 *std = V4L2_STD_ALL; 1342 if (state->ident != V4L2_IDENT_SAA7115) 1343 return 0; 1344 reg1e = saa711x_read(sd, R_1E_STATUS_BYTE_1_VD_DEC); 1345 1346 switch (reg1e & 0x03) { 1347 case 1: 1348 *std = V4L2_STD_NTSC; 1349 break; 1350 case 2: 1351 *std = V4L2_STD_PAL; 1352 break; 1353 case 3: 1354 *std = V4L2_STD_SECAM; 1355 break; 1356 default: 1357 break; 1358 } 1359 return 0; 1360} 1361 1362static int saa711x_g_input_status(struct v4l2_subdev *sd, u32 *status) 1363{ 1364 struct saa711x_state *state = to_state(sd); 1365 int reg1e = 0x80; 1366 int reg1f; 1367 1368 *status = V4L2_IN_ST_NO_SIGNAL; 1369 if (state->ident == V4L2_IDENT_SAA7115) 1370 reg1e = saa711x_read(sd, R_1E_STATUS_BYTE_1_VD_DEC); 1371 reg1f = saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC); 1372 if ((reg1f & 0xc1) == 0x81 && (reg1e & 0xc0) == 0x80) 1373 *status = 0; 1374 return 0; 1375} 1376 1377#ifdef CONFIG_VIDEO_ADV_DEBUG 1378static int saa711x_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg) 1379{ 1380 struct i2c_client *client = v4l2_get_subdevdata(sd); 1381 1382 if (!v4l2_chip_match_i2c_client(client, ®->match)) 1383 return -EINVAL; 1384 if (!capable(CAP_SYS_ADMIN)) 1385 return -EPERM; 1386 reg->val = saa711x_read(sd, reg->reg & 0xff); 1387 reg->size = 1; 1388 return 0; 1389} 1390 1391static int saa711x_s_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg) 1392{ 1393 struct i2c_client *client = v4l2_get_subdevdata(sd); 1394 1395 if (!v4l2_chip_match_i2c_client(client, ®->match)) 1396 return -EINVAL; 1397 if (!capable(CAP_SYS_ADMIN)) 1398 return -EPERM; 1399 saa711x_write(sd, reg->reg & 0xff, reg->val & 0xff); 1400 return 0; 1401} 1402#endif 1403 1404static int saa711x_g_chip_ident(struct v4l2_subdev *sd, struct v4l2_dbg_chip_ident *chip) 1405{ 1406 struct saa711x_state *state = to_state(sd); 1407 struct i2c_client *client = v4l2_get_subdevdata(sd); 1408 1409 return v4l2_chip_ident_i2c_client(client, chip, state->ident, 0); 1410} 1411 1412static int saa711x_log_status(struct v4l2_subdev *sd) 1413{ 1414 struct saa711x_state *state = to_state(sd); 1415 int reg1e, reg1f; 1416 int signalOk; 1417 int vcr; 1418 1419 v4l2_info(sd, "Audio frequency: %d Hz\n", state->audclk_freq); 1420 if (state->ident != V4L2_IDENT_SAA7115) { 1421 /* status for the saa7114 */ 1422 reg1f = saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC); 1423 signalOk = (reg1f & 0xc1) == 0x81; 1424 v4l2_info(sd, "Video signal: %s\n", signalOk ? "ok" : "bad"); 1425 v4l2_info(sd, "Frequency: %s\n", (reg1f & 0x20) ? "60 Hz" : "50 Hz"); 1426 return 0; 1427 } 1428 1429 /* status for the saa7115 */ 1430 reg1e = saa711x_read(sd, R_1E_STATUS_BYTE_1_VD_DEC); 1431 reg1f = saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC); 1432 1433 signalOk = (reg1f & 0xc1) == 0x81 && (reg1e & 0xc0) == 0x80; 1434 vcr = !(reg1f & 0x10); 1435 1436 if (state->input >= 6) 1437 v4l2_info(sd, "Input: S-Video %d\n", state->input - 6); 1438 else 1439 v4l2_info(sd, "Input: Composite %d\n", state->input); 1440 v4l2_info(sd, "Video signal: %s\n", signalOk ? (vcr ? "VCR" : "broadcast/DVD") : "bad"); 1441 v4l2_info(sd, "Frequency: %s\n", (reg1f & 0x20) ? "60 Hz" : "50 Hz"); 1442 1443 switch (reg1e & 0x03) { 1444 case 1: 1445 v4l2_info(sd, "Detected format: NTSC\n"); 1446 break; 1447 case 2: 1448 v4l2_info(sd, "Detected format: PAL\n"); 1449 break; 1450 case 3: 1451 v4l2_info(sd, "Detected format: SECAM\n"); 1452 break; 1453 default: 1454 v4l2_info(sd, "Detected format: BW/No color\n"); 1455 break; 1456 } 1457 v4l2_info(sd, "Width, Height: %d, %d\n", state->width, state->height); 1458 v4l2_ctrl_handler_log_status(&state->hdl, sd->name); 1459 return 0; 1460} 1461 1462/* ----------------------------------------------------------------------- */ 1463 1464static const struct v4l2_ctrl_ops saa711x_ctrl_ops = { 1465 .s_ctrl = saa711x_s_ctrl, 1466 .g_volatile_ctrl = saa711x_g_volatile_ctrl, 1467}; 1468 1469static const struct v4l2_subdev_core_ops saa711x_core_ops = { 1470 .log_status = saa711x_log_status, 1471 .g_chip_ident = saa711x_g_chip_ident, 1472 .g_ext_ctrls = v4l2_subdev_g_ext_ctrls, 1473 .try_ext_ctrls = v4l2_subdev_try_ext_ctrls, 1474 .s_ext_ctrls = v4l2_subdev_s_ext_ctrls, 1475 .g_ctrl = v4l2_subdev_g_ctrl, 1476 .s_ctrl = v4l2_subdev_s_ctrl, 1477 .queryctrl = v4l2_subdev_queryctrl, 1478 .querymenu = v4l2_subdev_querymenu, 1479 .s_std = saa711x_s_std, 1480 .reset = saa711x_reset, 1481 .s_gpio = saa711x_s_gpio, 1482#ifdef CONFIG_VIDEO_ADV_DEBUG 1483 .g_register = saa711x_g_register, 1484 .s_register = saa711x_s_register, 1485#endif 1486}; 1487 1488static const struct v4l2_subdev_tuner_ops saa711x_tuner_ops = { 1489 .s_radio = saa711x_s_radio, 1490 .g_tuner = saa711x_g_tuner, 1491}; 1492 1493static const struct v4l2_subdev_audio_ops saa711x_audio_ops = { 1494 .s_clock_freq = saa711x_s_clock_freq, 1495}; 1496 1497static const struct v4l2_subdev_video_ops saa711x_video_ops = { 1498 .s_routing = saa711x_s_routing, 1499 .s_crystal_freq = saa711x_s_crystal_freq, 1500 .s_mbus_fmt = saa711x_s_mbus_fmt, 1501 .s_stream = saa711x_s_stream, 1502 .querystd = saa711x_querystd, 1503 .g_input_status = saa711x_g_input_status, 1504}; 1505 1506static const struct v4l2_subdev_vbi_ops saa711x_vbi_ops = { 1507 .g_vbi_data = saa711x_g_vbi_data, 1508 .decode_vbi_line = saa711x_decode_vbi_line, 1509 .g_sliced_fmt = saa711x_g_sliced_fmt, 1510 .s_sliced_fmt = saa711x_s_sliced_fmt, 1511 .s_raw_fmt = saa711x_s_raw_fmt, 1512}; 1513 1514static const struct v4l2_subdev_ops saa711x_ops = { 1515 .core = &saa711x_core_ops, 1516 .tuner = &saa711x_tuner_ops, 1517 .audio = &saa711x_audio_ops, 1518 .video = &saa711x_video_ops, 1519 .vbi = &saa711x_vbi_ops, 1520}; 1521 1522/* ----------------------------------------------------------------------- */ 1523 1524static int saa711x_probe(struct i2c_client *client, 1525 const struct i2c_device_id *id) 1526{ 1527 struct saa711x_state *state; 1528 struct v4l2_subdev *sd; 1529 struct v4l2_ctrl_handler *hdl; 1530 int i; 1531 char name[17]; 1532 char chip_id; 1533 int autodetect = !id || id->driver_data == 1; 1534 1535 /* Check if the adapter supports the needed features */ 1536 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 1537 return -EIO; 1538 1539 for (i = 0; i < 0x0f; i++) { 1540 i2c_smbus_write_byte_data(client, 0, i); 1541 name[i] = (i2c_smbus_read_byte_data(client, 0) & 0x0f) + '0'; 1542 if (name[i] > '9') 1543 name[i] += 'a' - '9' - 1; 1544 } 1545 name[i] = '\0'; 1546 1547 chip_id = name[5]; 1548 1549 /* Check whether this chip is part of the saa711x series */ 1550 if (memcmp(name, "1f711", 5)) { 1551 v4l_dbg(1, debug, client, "chip found @ 0x%x (ID %s) does not match a known saa711x chip.\n", 1552 client->addr << 1, name); 1553 return -ENODEV; 1554 } 1555 1556 /* Safety check */ 1557 if (!autodetect && id->name[6] != chip_id) { 1558 v4l_warn(client, "found saa711%c while %s was expected\n", 1559 chip_id, id->name); 1560 } 1561 snprintf(client->name, sizeof(client->name), "saa711%c", chip_id); 1562 v4l_info(client, "saa711%c found (%s) @ 0x%x (%s)\n", chip_id, name, 1563 client->addr << 1, client->adapter->name); 1564 1565 state = kzalloc(sizeof(struct saa711x_state), GFP_KERNEL); 1566 if (state == NULL) 1567 return -ENOMEM; 1568 sd = &state->sd; 1569 v4l2_i2c_subdev_init(sd, client, &saa711x_ops); 1570 1571 hdl = &state->hdl; 1572 v4l2_ctrl_handler_init(hdl, 6); 1573 /* add in ascending ID order */ 1574 v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops, 1575 V4L2_CID_BRIGHTNESS, 0, 255, 1, 128); 1576 v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops, 1577 V4L2_CID_CONTRAST, 0, 127, 1, 64); 1578 v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops, 1579 V4L2_CID_SATURATION, 0, 127, 1, 64); 1580 v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops, 1581 V4L2_CID_HUE, -128, 127, 1, 0); 1582 state->agc = v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops, 1583 V4L2_CID_CHROMA_AGC, 0, 1, 1, 1); 1584 state->gain = v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops, 1585 V4L2_CID_CHROMA_GAIN, 0, 127, 1, 40); 1586 state->gain->is_volatile = 1; 1587 sd->ctrl_handler = hdl; 1588 if (hdl->error) { 1589 int err = hdl->error; 1590 1591 v4l2_ctrl_handler_free(hdl); 1592 kfree(state); 1593 return err; 1594 } 1595 state->agc->flags |= V4L2_CTRL_FLAG_UPDATE; 1596 v4l2_ctrl_cluster(2, &state->agc); 1597 1598 state->input = -1; 1599 state->output = SAA7115_IPORT_ON; 1600 state->enable = 1; 1601 state->radio = 0; 1602 switch (chip_id) { 1603 case '1': 1604 state->ident = V4L2_IDENT_SAA7111; 1605 if (saa711x_read(sd, R_00_CHIP_VERSION) & 0xf0) { 1606 v4l_info(client, "saa7111a variant found\n"); 1607 state->ident = V4L2_IDENT_SAA7111A; 1608 } 1609 break; 1610 case '3': 1611 state->ident = V4L2_IDENT_SAA7113; 1612 break; 1613 case '4': 1614 state->ident = V4L2_IDENT_SAA7114; 1615 break; 1616 case '5': 1617 state->ident = V4L2_IDENT_SAA7115; 1618 break; 1619 case '8': 1620 state->ident = V4L2_IDENT_SAA7118; 1621 break; 1622 default: 1623 state->ident = V4L2_IDENT_SAA7111; 1624 v4l2_info(sd, "WARNING: Chip is not known - Falling back to saa7111\n"); 1625 break; 1626 } 1627 1628 state->audclk_freq = 48000; 1629 1630 v4l2_dbg(1, debug, sd, "writing init values\n"); 1631 1632 /* init to 60hz/48khz */ 1633 state->crystal_freq = SAA7115_FREQ_24_576_MHZ; 1634 switch (state->ident) { 1635 case V4L2_IDENT_SAA7111: 1636 case V4L2_IDENT_SAA7111A: 1637 saa711x_writeregs(sd, saa7111_init); 1638 break; 1639 case V4L2_IDENT_SAA7113: 1640 saa711x_writeregs(sd, saa7113_init); 1641 break; 1642 default: 1643 state->crystal_freq = SAA7115_FREQ_32_11_MHZ; 1644 saa711x_writeregs(sd, saa7115_init_auto_input); 1645 } 1646 if (state->ident > V4L2_IDENT_SAA7111A) 1647 saa711x_writeregs(sd, saa7115_init_misc); 1648 saa711x_set_v4lstd(sd, V4L2_STD_NTSC); 1649 v4l2_ctrl_handler_setup(hdl); 1650 1651 v4l2_dbg(1, debug, sd, "status: (1E) 0x%02x, (1F) 0x%02x\n", 1652 saa711x_read(sd, R_1E_STATUS_BYTE_1_VD_DEC), 1653 saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC)); 1654 return 0; 1655} 1656 1657/* ----------------------------------------------------------------------- */ 1658 1659static int saa711x_remove(struct i2c_client *client) 1660{ 1661 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1662 1663 v4l2_device_unregister_subdev(sd); 1664 v4l2_ctrl_handler_free(sd->ctrl_handler); 1665 kfree(to_state(sd)); 1666 return 0; 1667} 1668 1669static const struct i2c_device_id saa7115_id[] = { 1670 { "saa7115_auto", 1 }, /* autodetect */ 1671 { "saa7111", 0 }, 1672 { "saa7113", 0 }, 1673 { "saa7114", 0 }, 1674 { "saa7115", 0 }, 1675 { "saa7118", 0 }, 1676 { } 1677}; 1678MODULE_DEVICE_TABLE(i2c, saa7115_id); 1679 1680static struct v4l2_i2c_driver_data v4l2_i2c_data = { 1681 .name = "saa7115", 1682 .probe = saa711x_probe, 1683 .remove = saa711x_remove, 1684 .id_table = saa7115_id, 1685}; 1686