1/* 2 * drivers/media/video/omap24xxcam.h 3 * 4 * Copyright (C) 2004 MontaVista Software, Inc. 5 * Copyright (C) 2004 Texas Instruments. 6 * Copyright (C) 2007 Nokia Corporation. 7 * 8 * Contact: Sakari Ailus <sakari.ailus@nokia.com> 9 * 10 * Based on code from Andy Lowe <source@mvista.com>. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License 14 * version 2 as published by the Free Software Foundation. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 24 * 02110-1301 USA 25 */ 26 27#ifndef OMAP24XXCAM_H 28#define OMAP24XXCAM_H 29 30#include <media/videobuf-dma-sg.h> 31#include <media/v4l2-int-device.h> 32 33/* 34 * 35 * General driver related definitions. 36 * 37 */ 38 39#define CAM_NAME "omap24xxcam" 40 41#define CAM_MCLK 96000000 42 43/* number of bytes transferred per DMA request */ 44#define DMA_THRESHOLD 32 45 46/* 47 * NUM_CAMDMA_CHANNELS is the number of logical channels provided by 48 * the camera DMA controller. 49 */ 50#define NUM_CAMDMA_CHANNELS 4 51 52/* 53 * NUM_SG_DMA is the number of scatter-gather DMA transfers that can 54 * be queued. (We don't have any overlay sglists now.) 55 */ 56#define NUM_SG_DMA (VIDEO_MAX_FRAME) 57 58/* 59 * 60 * Register definitions. 61 * 62 */ 63 64/* subsystem register block offsets */ 65#define CC_REG_OFFSET 0x00000400 66#define CAMDMA_REG_OFFSET 0x00000800 67#define CAMMMU_REG_OFFSET 0x00000C00 68 69/* define camera subsystem register offsets */ 70#define CAM_REVISION 0x000 71#define CAM_SYSCONFIG 0x010 72#define CAM_SYSSTATUS 0x014 73#define CAM_IRQSTATUS 0x018 74#define CAM_GPO 0x040 75#define CAM_GPI 0x050 76 77/* define camera core register offsets */ 78#define CC_REVISION 0x000 79#define CC_SYSCONFIG 0x010 80#define CC_SYSSTATUS 0x014 81#define CC_IRQSTATUS 0x018 82#define CC_IRQENABLE 0x01C 83#define CC_CTRL 0x040 84#define CC_CTRL_DMA 0x044 85#define CC_CTRL_XCLK 0x048 86#define CC_FIFODATA 0x04C 87#define CC_TEST 0x050 88#define CC_GENPAR 0x054 89#define CC_CCPFSCR 0x058 90#define CC_CCPFECR 0x05C 91#define CC_CCPLSCR 0x060 92#define CC_CCPLECR 0x064 93#define CC_CCPDFR 0x068 94 95/* define camera dma register offsets */ 96#define CAMDMA_REVISION 0x000 97#define CAMDMA_IRQSTATUS_L0 0x008 98#define CAMDMA_IRQSTATUS_L1 0x00C 99#define CAMDMA_IRQSTATUS_L2 0x010 100#define CAMDMA_IRQSTATUS_L3 0x014 101#define CAMDMA_IRQENABLE_L0 0x018 102#define CAMDMA_IRQENABLE_L1 0x01C 103#define CAMDMA_IRQENABLE_L2 0x020 104#define CAMDMA_IRQENABLE_L3 0x024 105#define CAMDMA_SYSSTATUS 0x028 106#define CAMDMA_OCP_SYSCONFIG 0x02C 107#define CAMDMA_CAPS_0 0x064 108#define CAMDMA_CAPS_2 0x06C 109#define CAMDMA_CAPS_3 0x070 110#define CAMDMA_CAPS_4 0x074 111#define CAMDMA_GCR 0x078 112#define CAMDMA_CCR(n) (0x080 + (n)*0x60) 113#define CAMDMA_CLNK_CTRL(n) (0x084 + (n)*0x60) 114#define CAMDMA_CICR(n) (0x088 + (n)*0x60) 115#define CAMDMA_CSR(n) (0x08C + (n)*0x60) 116#define CAMDMA_CSDP(n) (0x090 + (n)*0x60) 117#define CAMDMA_CEN(n) (0x094 + (n)*0x60) 118#define CAMDMA_CFN(n) (0x098 + (n)*0x60) 119#define CAMDMA_CSSA(n) (0x09C + (n)*0x60) 120#define CAMDMA_CDSA(n) (0x0A0 + (n)*0x60) 121#define CAMDMA_CSEI(n) (0x0A4 + (n)*0x60) 122#define CAMDMA_CSFI(n) (0x0A8 + (n)*0x60) 123#define CAMDMA_CDEI(n) (0x0AC + (n)*0x60) 124#define CAMDMA_CDFI(n) (0x0B0 + (n)*0x60) 125#define CAMDMA_CSAC(n) (0x0B4 + (n)*0x60) 126#define CAMDMA_CDAC(n) (0x0B8 + (n)*0x60) 127#define CAMDMA_CCEN(n) (0x0BC + (n)*0x60) 128#define CAMDMA_CCFN(n) (0x0C0 + (n)*0x60) 129#define CAMDMA_COLOR(n) (0x0C4 + (n)*0x60) 130 131/* define camera mmu register offsets */ 132#define CAMMMU_REVISION 0x000 133#define CAMMMU_SYSCONFIG 0x010 134#define CAMMMU_SYSSTATUS 0x014 135#define CAMMMU_IRQSTATUS 0x018 136#define CAMMMU_IRQENABLE 0x01C 137#define CAMMMU_WALKING_ST 0x040 138#define CAMMMU_CNTL 0x044 139#define CAMMMU_FAULT_AD 0x048 140#define CAMMMU_TTB 0x04C 141#define CAMMMU_LOCK 0x050 142#define CAMMMU_LD_TLB 0x054 143#define CAMMMU_CAM 0x058 144#define CAMMMU_RAM 0x05C 145#define CAMMMU_GFLUSH 0x060 146#define CAMMMU_FLUSH_ENTRY 0x064 147#define CAMMMU_READ_CAM 0x068 148#define CAMMMU_READ_RAM 0x06C 149#define CAMMMU_EMU_FAULT_AD 0x070 150 151/* Define bit fields within selected registers */ 152#define CAM_REVISION_MAJOR (15 << 4) 153#define CAM_REVISION_MAJOR_SHIFT 4 154#define CAM_REVISION_MINOR (15 << 0) 155#define CAM_REVISION_MINOR_SHIFT 0 156 157#define CAM_SYSCONFIG_SOFTRESET (1 << 1) 158#define CAM_SYSCONFIG_AUTOIDLE (1 << 0) 159 160#define CAM_SYSSTATUS_RESETDONE (1 << 0) 161 162#define CAM_IRQSTATUS_CC_IRQ (1 << 4) 163#define CAM_IRQSTATUS_MMU_IRQ (1 << 3) 164#define CAM_IRQSTATUS_DMA_IRQ2 (1 << 2) 165#define CAM_IRQSTATUS_DMA_IRQ1 (1 << 1) 166#define CAM_IRQSTATUS_DMA_IRQ0 (1 << 0) 167 168#define CAM_GPO_CAM_S_P_EN (1 << 1) 169#define CAM_GPO_CAM_CCP_MODE (1 << 0) 170 171#define CAM_GPI_CC_DMA_REQ1 (1 << 24) 172#define CAP_GPI_CC_DMA_REQ0 (1 << 23) 173#define CAP_GPI_CAM_MSTANDBY (1 << 21) 174#define CAP_GPI_CAM_WAIT (1 << 20) 175#define CAP_GPI_CAM_S_DATA (1 << 17) 176#define CAP_GPI_CAM_S_CLK (1 << 16) 177#define CAP_GPI_CAM_P_DATA (0xFFF << 3) 178#define CAP_GPI_CAM_P_DATA_SHIFT 3 179#define CAP_GPI_CAM_P_VS (1 << 2) 180#define CAP_GPI_CAM_P_HS (1 << 1) 181#define CAP_GPI_CAM_P_CLK (1 << 0) 182 183#define CC_REVISION_MAJOR (15 << 4) 184#define CC_REVISION_MAJOR_SHIFT 4 185#define CC_REVISION_MINOR (15 << 0) 186#define CC_REVISION_MINOR_SHIFT 0 187 188#define CC_SYSCONFIG_SIDLEMODE (3 << 3) 189#define CC_SYSCONFIG_SIDLEMODE_FIDLE (0 << 3) 190#define CC_SYSCONFIG_SIDLEMODE_NIDLE (1 << 3) 191#define CC_SYSCONFIG_SOFTRESET (1 << 1) 192#define CC_SYSCONFIG_AUTOIDLE (1 << 0) 193 194#define CC_SYSSTATUS_RESETDONE (1 << 0) 195 196#define CC_IRQSTATUS_FS_IRQ (1 << 19) 197#define CC_IRQSTATUS_LE_IRQ (1 << 18) 198#define CC_IRQSTATUS_LS_IRQ (1 << 17) 199#define CC_IRQSTATUS_FE_IRQ (1 << 16) 200#define CC_IRQSTATUS_FW_ERR_IRQ (1 << 10) 201#define CC_IRQSTATUS_FSC_ERR_IRQ (1 << 9) 202#define CC_IRQSTATUS_SSC_ERR_IRQ (1 << 8) 203#define CC_IRQSTATUS_FIFO_NOEMPTY_IRQ (1 << 4) 204#define CC_IRQSTATUS_FIFO_FULL_IRQ (1 << 3) 205#define CC_IRQSTATUS_FIFO_THR_IRQ (1 << 2) 206#define CC_IRQSTATUS_FIFO_OF_IRQ (1 << 1) 207#define CC_IRQSTATUS_FIFO_UF_IRQ (1 << 0) 208 209#define CC_IRQENABLE_FS_IRQ (1 << 19) 210#define CC_IRQENABLE_LE_IRQ (1 << 18) 211#define CC_IRQENABLE_LS_IRQ (1 << 17) 212#define CC_IRQENABLE_FE_IRQ (1 << 16) 213#define CC_IRQENABLE_FW_ERR_IRQ (1 << 10) 214#define CC_IRQENABLE_FSC_ERR_IRQ (1 << 9) 215#define CC_IRQENABLE_SSC_ERR_IRQ (1 << 8) 216#define CC_IRQENABLE_FIFO_NOEMPTY_IRQ (1 << 4) 217#define CC_IRQENABLE_FIFO_FULL_IRQ (1 << 3) 218#define CC_IRQENABLE_FIFO_THR_IRQ (1 << 2) 219#define CC_IRQENABLE_FIFO_OF_IRQ (1 << 1) 220#define CC_IRQENABLE_FIFO_UF_IRQ (1 << 0) 221 222#define CC_CTRL_CC_ONE_SHOT (1 << 20) 223#define CC_CTRL_CC_IF_SYNCHRO (1 << 19) 224#define CC_CTRL_CC_RST (1 << 18) 225#define CC_CTRL_CC_FRAME_TRIG (1 << 17) 226#define CC_CTRL_CC_EN (1 << 16) 227#define CC_CTRL_NOBT_SYNCHRO (1 << 13) 228#define CC_CTRL_BT_CORRECT (1 << 12) 229#define CC_CTRL_PAR_ORDERCAM (1 << 11) 230#define CC_CTRL_PAR_CLK_POL (1 << 10) 231#define CC_CTRL_NOBT_HS_POL (1 << 9) 232#define CC_CTRL_NOBT_VS_POL (1 << 8) 233#define CC_CTRL_PAR_MODE (7 << 1) 234#define CC_CTRL_PAR_MODE_SHIFT 1 235#define CC_CTRL_PAR_MODE_NOBT8 (0 << 1) 236#define CC_CTRL_PAR_MODE_NOBT10 (1 << 1) 237#define CC_CTRL_PAR_MODE_NOBT12 (2 << 1) 238#define CC_CTRL_PAR_MODE_BT8 (4 << 1) 239#define CC_CTRL_PAR_MODE_BT10 (5 << 1) 240#define CC_CTRL_PAR_MODE_FIFOTEST (7 << 1) 241#define CC_CTRL_CCP_MODE (1 << 0) 242 243#define CC_CTRL_DMA_EN (1 << 8) 244#define CC_CTRL_DMA_FIFO_THRESHOLD (0x7F << 0) 245#define CC_CTRL_DMA_FIFO_THRESHOLD_SHIFT 0 246 247#define CC_CTRL_XCLK_DIV (0x1F << 0) 248#define CC_CTRL_XCLK_DIV_SHIFT 0 249#define CC_CTRL_XCLK_DIV_STABLE_LOW (0 << 0) 250#define CC_CTRL_XCLK_DIV_STABLE_HIGH (1 << 0) 251#define CC_CTRL_XCLK_DIV_BYPASS (31 << 0) 252 253#define CC_TEST_FIFO_RD_POINTER (0xFF << 24) 254#define CC_TEST_FIFO_RD_POINTER_SHIFT 24 255#define CC_TEST_FIFO_WR_POINTER (0xFF << 16) 256#define CC_TEST_FIFO_WR_POINTER_SHIFT 16 257#define CC_TEST_FIFO_LEVEL (0xFF << 8) 258#define CC_TEST_FIFO_LEVEL_SHIFT 8 259#define CC_TEST_FIFO_LEVEL_PEAK (0xFF << 0) 260#define CC_TEST_FIFO_LEVEL_PEAK_SHIFT 0 261 262#define CC_GENPAR_FIFO_DEPTH (7 << 0) 263#define CC_GENPAR_FIFO_DEPTH_SHIFT 0 264 265#define CC_CCPDFR_ALPHA (0xFF << 8) 266#define CC_CCPDFR_ALPHA_SHIFT 8 267#define CC_CCPDFR_DATAFORMAT (15 << 0) 268#define CC_CCPDFR_DATAFORMAT_SHIFT 0 269#define CC_CCPDFR_DATAFORMAT_YUV422BE (0 << 0) 270#define CC_CCPDFR_DATAFORMAT_YUV422 (1 << 0) 271#define CC_CCPDFR_DATAFORMAT_YUV420 (2 << 0) 272#define CC_CCPDFR_DATAFORMAT_RGB444 (4 << 0) 273#define CC_CCPDFR_DATAFORMAT_RGB565 (5 << 0) 274#define CC_CCPDFR_DATAFORMAT_RGB888NDE (6 << 0) 275#define CC_CCPDFR_DATAFORMAT_RGB888 (7 << 0) 276#define CC_CCPDFR_DATAFORMAT_RAW8NDE (8 << 0) 277#define CC_CCPDFR_DATAFORMAT_RAW8 (9 << 0) 278#define CC_CCPDFR_DATAFORMAT_RAW10NDE (10 << 0) 279#define CC_CCPDFR_DATAFORMAT_RAW10 (11 << 0) 280#define CC_CCPDFR_DATAFORMAT_RAW12NDE (12 << 0) 281#define CC_CCPDFR_DATAFORMAT_RAW12 (13 << 0) 282#define CC_CCPDFR_DATAFORMAT_JPEG8 (15 << 0) 283 284#define CAMDMA_REVISION_MAJOR (15 << 4) 285#define CAMDMA_REVISION_MAJOR_SHIFT 4 286#define CAMDMA_REVISION_MINOR (15 << 0) 287#define CAMDMA_REVISION_MINOR_SHIFT 0 288 289#define CAMDMA_OCP_SYSCONFIG_MIDLEMODE (3 << 12) 290#define CAMDMA_OCP_SYSCONFIG_MIDLEMODE_FSTANDBY (0 << 12) 291#define CAMDMA_OCP_SYSCONFIG_MIDLEMODE_NSTANDBY (1 << 12) 292#define CAMDMA_OCP_SYSCONFIG_MIDLEMODE_SSTANDBY (2 << 12) 293#define CAMDMA_OCP_SYSCONFIG_FUNC_CLOCK (1 << 9) 294#define CAMDMA_OCP_SYSCONFIG_OCP_CLOCK (1 << 8) 295#define CAMDMA_OCP_SYSCONFIG_EMUFREE (1 << 5) 296#define CAMDMA_OCP_SYSCONFIG_SIDLEMODE (3 << 3) 297#define CAMDMA_OCP_SYSCONFIG_SIDLEMODE_FIDLE (0 << 3) 298#define CAMDMA_OCP_SYSCONFIG_SIDLEMODE_NIDLE (1 << 3) 299#define CAMDMA_OCP_SYSCONFIG_SIDLEMODE_SIDLE (2 << 3) 300#define CAMDMA_OCP_SYSCONFIG_SOFTRESET (1 << 1) 301#define CAMDMA_OCP_SYSCONFIG_AUTOIDLE (1 << 0) 302 303#define CAMDMA_SYSSTATUS_RESETDONE (1 << 0) 304 305#define CAMDMA_GCR_ARBITRATION_RATE (0xFF << 16) 306#define CAMDMA_GCR_ARBITRATION_RATE_SHIFT 16 307#define CAMDMA_GCR_MAX_CHANNEL_FIFO_DEPTH (0xFF << 0) 308#define CAMDMA_GCR_MAX_CHANNEL_FIFO_DEPTH_SHIFT 0 309 310#define CAMDMA_CCR_SEL_SRC_DST_SYNC (1 << 24) 311#define CAMDMA_CCR_PREFETCH (1 << 23) 312#define CAMDMA_CCR_SUPERVISOR (1 << 22) 313#define CAMDMA_CCR_SECURE (1 << 21) 314#define CAMDMA_CCR_BS (1 << 18) 315#define CAMDMA_CCR_TRANSPARENT_COPY_ENABLE (1 << 17) 316#define CAMDMA_CCR_CONSTANT_FILL_ENABLE (1 << 16) 317#define CAMDMA_CCR_DST_AMODE (3 << 14) 318#define CAMDMA_CCR_DST_AMODE_CONST_ADDR (0 << 14) 319#define CAMDMA_CCR_DST_AMODE_POST_INC (1 << 14) 320#define CAMDMA_CCR_DST_AMODE_SGL_IDX (2 << 14) 321#define CAMDMA_CCR_DST_AMODE_DBL_IDX (3 << 14) 322#define CAMDMA_CCR_SRC_AMODE (3 << 12) 323#define CAMDMA_CCR_SRC_AMODE_CONST_ADDR (0 << 12) 324#define CAMDMA_CCR_SRC_AMODE_POST_INC (1 << 12) 325#define CAMDMA_CCR_SRC_AMODE_SGL_IDX (2 << 12) 326#define CAMDMA_CCR_SRC_AMODE_DBL_IDX (3 << 12) 327#define CAMDMA_CCR_WR_ACTIVE (1 << 10) 328#define CAMDMA_CCR_RD_ACTIVE (1 << 9) 329#define CAMDMA_CCR_SUSPEND_SENSITIVE (1 << 8) 330#define CAMDMA_CCR_ENABLE (1 << 7) 331#define CAMDMA_CCR_PRIO (1 << 6) 332#define CAMDMA_CCR_FS (1 << 5) 333#define CAMDMA_CCR_SYNCHRO ((3 << 19) | (31 << 0)) 334#define CAMDMA_CCR_SYNCHRO_CAMERA 0x01 335 336#define CAMDMA_CLNK_CTRL_ENABLE_LNK (1 << 15) 337#define CAMDMA_CLNK_CTRL_NEXTLCH_ID (0x1F << 0) 338#define CAMDMA_CLNK_CTRL_NEXTLCH_ID_SHIFT 0 339 340#define CAMDMA_CICR_MISALIGNED_ERR_IE (1 << 11) 341#define CAMDMA_CICR_SUPERVISOR_ERR_IE (1 << 10) 342#define CAMDMA_CICR_SECURE_ERR_IE (1 << 9) 343#define CAMDMA_CICR_TRANS_ERR_IE (1 << 8) 344#define CAMDMA_CICR_PACKET_IE (1 << 7) 345#define CAMDMA_CICR_BLOCK_IE (1 << 5) 346#define CAMDMA_CICR_LAST_IE (1 << 4) 347#define CAMDMA_CICR_FRAME_IE (1 << 3) 348#define CAMDMA_CICR_HALF_IE (1 << 2) 349#define CAMDMA_CICR_DROP_IE (1 << 1) 350 351#define CAMDMA_CSR_MISALIGNED_ERR (1 << 11) 352#define CAMDMA_CSR_SUPERVISOR_ERR (1 << 10) 353#define CAMDMA_CSR_SECURE_ERR (1 << 9) 354#define CAMDMA_CSR_TRANS_ERR (1 << 8) 355#define CAMDMA_CSR_PACKET (1 << 7) 356#define CAMDMA_CSR_SYNC (1 << 6) 357#define CAMDMA_CSR_BLOCK (1 << 5) 358#define CAMDMA_CSR_LAST (1 << 4) 359#define CAMDMA_CSR_FRAME (1 << 3) 360#define CAMDMA_CSR_HALF (1 << 2) 361#define CAMDMA_CSR_DROP (1 << 1) 362 363#define CAMDMA_CSDP_SRC_ENDIANNESS (1 << 21) 364#define CAMDMA_CSDP_SRC_ENDIANNESS_LOCK (1 << 20) 365#define CAMDMA_CSDP_DST_ENDIANNESS (1 << 19) 366#define CAMDMA_CSDP_DST_ENDIANNESS_LOCK (1 << 18) 367#define CAMDMA_CSDP_WRITE_MODE (3 << 16) 368#define CAMDMA_CSDP_WRITE_MODE_WRNP (0 << 16) 369#define CAMDMA_CSDP_WRITE_MODE_POSTED (1 << 16) 370#define CAMDMA_CSDP_WRITE_MODE_POSTED_LAST_WRNP (2 << 16) 371#define CAMDMA_CSDP_DST_BURST_EN (3 << 14) 372#define CAMDMA_CSDP_DST_BURST_EN_1 (0 << 14) 373#define CAMDMA_CSDP_DST_BURST_EN_16 (1 << 14) 374#define CAMDMA_CSDP_DST_BURST_EN_32 (2 << 14) 375#define CAMDMA_CSDP_DST_BURST_EN_64 (3 << 14) 376#define CAMDMA_CSDP_DST_PACKED (1 << 13) 377#define CAMDMA_CSDP_WR_ADD_TRSLT (15 << 9) 378#define CAMDMA_CSDP_WR_ADD_TRSLT_ENABLE_MREQADD (3 << 9) 379#define CAMDMA_CSDP_SRC_BURST_EN (3 << 7) 380#define CAMDMA_CSDP_SRC_BURST_EN_1 (0 << 7) 381#define CAMDMA_CSDP_SRC_BURST_EN_16 (1 << 7) 382#define CAMDMA_CSDP_SRC_BURST_EN_32 (2 << 7) 383#define CAMDMA_CSDP_SRC_BURST_EN_64 (3 << 7) 384#define CAMDMA_CSDP_SRC_PACKED (1 << 6) 385#define CAMDMA_CSDP_RD_ADD_TRSLT (15 << 2) 386#define CAMDMA_CSDP_RD_ADD_TRSLT_ENABLE_MREQADD (3 << 2) 387#define CAMDMA_CSDP_DATA_TYPE (3 << 0) 388#define CAMDMA_CSDP_DATA_TYPE_8BITS (0 << 0) 389#define CAMDMA_CSDP_DATA_TYPE_16BITS (1 << 0) 390#define CAMDMA_CSDP_DATA_TYPE_32BITS (2 << 0) 391 392#define CAMMMU_SYSCONFIG_AUTOIDLE (1 << 0) 393 394/* 395 * 396 * Declarations. 397 * 398 */ 399 400/* forward declarations */ 401struct omap24xxcam_sgdma; 402struct omap24xxcam_dma; 403 404typedef void (*sgdma_callback_t)(struct omap24xxcam_sgdma *cam, 405 u32 status, void *arg); 406typedef void (*dma_callback_t)(struct omap24xxcam_dma *cam, 407 u32 status, void *arg); 408 409struct channel_state { 410 dma_callback_t callback; 411 void *arg; 412}; 413 414/* sgdma state for each of the possible videobuf_buffers + 2 overlays */ 415struct sgdma_state { 416 const struct scatterlist *sglist; 417 int sglen; /* number of sglist entries */ 418 int next_sglist; /* index of next sglist entry to process */ 419 unsigned int bytes_read; /* number of bytes read */ 420 unsigned int len; /* total length of sglist (excluding 421 * bytes due to page alignment) */ 422 int queued_sglist; /* number of sglist entries queued for DMA */ 423 u32 csr; /* DMA return code */ 424 sgdma_callback_t callback; 425 void *arg; 426}; 427 428/* physical DMA channel management */ 429struct omap24xxcam_dma { 430 spinlock_t lock; /* Lock for the whole structure. */ 431 432 unsigned long base; /* base address for dma controller */ 433 434 /* While dma_stop!=0, an attempt to start a new DMA transfer will 435 * fail. 436 */ 437 atomic_t dma_stop; 438 int free_dmach; /* number of dma channels free */ 439 int next_dmach; /* index of next dma channel to use */ 440 struct channel_state ch_state[NUM_CAMDMA_CHANNELS]; 441}; 442 443/* scatter-gather DMA (scatterlist stuff) management */ 444struct omap24xxcam_sgdma { 445 struct omap24xxcam_dma dma; 446 447 spinlock_t lock; /* Lock for the fields below. */ 448 int free_sgdma; /* number of free sg dma slots */ 449 int next_sgdma; /* index of next sg dma slot to use */ 450 struct sgdma_state sg_state[NUM_SG_DMA]; 451 452 /* Reset timer data */ 453 struct timer_list reset_timer; 454}; 455 456/* per-device data structure */ 457struct omap24xxcam_device { 458 /*** mutex ***/ 459 /* 460 * mutex serialises access to this structure. Also camera 461 * opening and releasing is synchronised by this. 462 */ 463 struct mutex mutex; 464 465 /*** general driver state information ***/ 466 atomic_t users; 467 /* 468 * Lock to serialise core enabling and disabling and access to 469 * sgdma_in_queue. 470 */ 471 spinlock_t core_enable_disable_lock; 472 /* 473 * Number or sgdma requests in scatter-gather queue, protected 474 * by the lock above. 475 */ 476 int sgdma_in_queue; 477 /* 478 * Sensor interface parameters: interface type, CC_CTRL 479 * register value and interface specific data. 480 */ 481 int if_type; 482 union { 483 struct parallel { 484 u32 xclk; 485 } bt656; 486 } if_u; 487 u32 cc_ctrl; 488 489 /*** subsystem structures ***/ 490 struct omap24xxcam_sgdma sgdma; 491 492 /*** hardware resources ***/ 493 unsigned int irq; 494 unsigned long mmio_base; 495 unsigned long mmio_base_phys; 496 unsigned long mmio_size; 497 498 /*** interfaces and device ***/ 499 struct v4l2_int_device *sdev; 500 struct device *dev; 501 struct video_device *vfd; 502 503 /*** camera and sensor reset related stuff ***/ 504 struct work_struct sensor_reset_work; 505 /* 506 * We're in the middle of a reset. Don't enable core if this 507 * is non-zero! This exists to help decisionmaking in a case 508 * where videobuf_qbuf is called while we are in the middle of 509 * a reset. 510 */ 511 atomic_t in_reset; 512 /* 513 * Non-zero if we don't want any resets for now. Used to 514 * prevent reset work to run when we're about to stop 515 * streaming. 516 */ 517 atomic_t reset_disable; 518 519 /*** video device parameters ***/ 520 int capture_mem; 521 522 /*** camera module clocks ***/ 523 struct clk *fck; 524 struct clk *ick; 525 526 /*** capture data ***/ 527 /* file handle, if streaming is on */ 528 struct file *streaming; 529}; 530 531/* Per-file handle data. */ 532struct omap24xxcam_fh { 533 spinlock_t vbq_lock; /* spinlock for the videobuf queue */ 534 struct videobuf_queue vbq; 535 struct v4l2_pix_format pix; /* serialise pix by vbq->lock */ 536 atomic_t field_count; /* field counter for videobuf_buffer */ 537 /* accessing cam here doesn't need serialisation: it's constant */ 538 struct omap24xxcam_device *cam; 539}; 540 541/* 542 * 543 * Register I/O functions. 544 * 545 */ 546 547static inline u32 omap24xxcam_reg_in(unsigned long base, u32 offset) 548{ 549 return readl(base + offset); 550} 551 552static inline u32 omap24xxcam_reg_out(unsigned long base, u32 offset, 553 u32 val) 554{ 555 writel(val, base + offset); 556 return val; 557} 558 559static inline u32 omap24xxcam_reg_merge(unsigned long base, u32 offset, 560 u32 val, u32 mask) 561{ 562 u32 addr = base + offset; 563 u32 new_val = (readl(addr) & ~mask) | (val & mask); 564 565 writel(new_val, addr); 566 return new_val; 567} 568 569/* 570 * 571 * Function prototypes. 572 * 573 */ 574 575/* dma prototypes */ 576 577void omap24xxcam_dma_hwinit(struct omap24xxcam_dma *dma); 578void omap24xxcam_dma_isr(struct omap24xxcam_dma *dma); 579 580/* sgdma prototypes */ 581 582void omap24xxcam_sgdma_process(struct omap24xxcam_sgdma *sgdma); 583int omap24xxcam_sgdma_queue(struct omap24xxcam_sgdma *sgdma, 584 const struct scatterlist *sglist, int sglen, 585 int len, sgdma_callback_t callback, void *arg); 586void omap24xxcam_sgdma_sync(struct omap24xxcam_sgdma *sgdma); 587void omap24xxcam_sgdma_init(struct omap24xxcam_sgdma *sgdma, 588 unsigned long base, 589 void (*reset_callback)(unsigned long data), 590 unsigned long reset_callback_data); 591void omap24xxcam_sgdma_exit(struct omap24xxcam_sgdma *sgdma); 592 593#endif 594