1/* 2 * mt9t112 Camera Driver 3 * 4 * Copyright (C) 2009 Renesas Solutions Corp. 5 * Kuninori Morimoto <morimoto.kuninori@renesas.com> 6 * 7 * Based on ov772x driver, mt9m111 driver, 8 * 9 * Copyright (C) 2008 Kuninori Morimoto <morimoto.kuninori@renesas.com> 10 * Copyright (C) 2008, Robert Jarzmik <robert.jarzmik@free.fr> 11 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net> 12 * Copyright (C) 2008 Magnus Damm 13 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License version 2 as 17 * published by the Free Software Foundation. 18 */ 19 20#include <linux/delay.h> 21#include <linux/i2c.h> 22#include <linux/init.h> 23#include <linux/module.h> 24#include <linux/slab.h> 25#include <linux/videodev2.h> 26 27#include <media/mt9t112.h> 28#include <media/soc_camera.h> 29#include <media/soc_mediabus.h> 30#include <media/v4l2-chip-ident.h> 31#include <media/v4l2-common.h> 32 33/* you can check PLL/clock info */ 34/* #define EXT_CLOCK 24000000 */ 35 36/************************************************************************ 37 38 39 macro 40 41 42************************************************************************/ 43/* 44 * frame size 45 */ 46#define MAX_WIDTH 2048 47#define MAX_HEIGHT 1536 48 49#define VGA_WIDTH 640 50#define VGA_HEIGHT 480 51 52/* 53 * macro of read/write 54 */ 55#define ECHECKER(ret, x) \ 56 do { \ 57 (ret) = (x); \ 58 if ((ret) < 0) \ 59 return (ret); \ 60 } while (0) 61 62#define mt9t112_reg_write(ret, client, a, b) \ 63 ECHECKER(ret, __mt9t112_reg_write(client, a, b)) 64#define mt9t112_mcu_write(ret, client, a, b) \ 65 ECHECKER(ret, __mt9t112_mcu_write(client, a, b)) 66 67#define mt9t112_reg_mask_set(ret, client, a, b, c) \ 68 ECHECKER(ret, __mt9t112_reg_mask_set(client, a, b, c)) 69#define mt9t112_mcu_mask_set(ret, client, a, b, c) \ 70 ECHECKER(ret, __mt9t112_mcu_mask_set(client, a, b, c)) 71 72#define mt9t112_reg_read(ret, client, a) \ 73 ECHECKER(ret, __mt9t112_reg_read(client, a)) 74 75/* 76 * Logical address 77 */ 78#define _VAR(id, offset, base) (base | (id & 0x1f) << 10 | (offset & 0x3ff)) 79#define VAR(id, offset) _VAR(id, offset, 0x0000) 80#define VAR8(id, offset) _VAR(id, offset, 0x8000) 81 82/************************************************************************ 83 84 85 struct 86 87 88************************************************************************/ 89struct mt9t112_frame_size { 90 u16 width; 91 u16 height; 92}; 93 94struct mt9t112_format { 95 enum v4l2_mbus_pixelcode code; 96 enum v4l2_colorspace colorspace; 97 u16 fmt; 98 u16 order; 99}; 100 101struct mt9t112_priv { 102 struct v4l2_subdev subdev; 103 struct mt9t112_camera_info *info; 104 struct i2c_client *client; 105 struct soc_camera_device icd; 106 struct mt9t112_frame_size frame; 107 const struct mt9t112_format *format; 108 int model; 109 u32 flags; 110/* for flags */ 111#define INIT_DONE (1<<0) 112}; 113 114/************************************************************************ 115 116 117 supported format 118 119 120************************************************************************/ 121 122static const struct mt9t112_format mt9t112_cfmts[] = { 123 { 124 .code = V4L2_MBUS_FMT_UYVY8_2X8, 125 .colorspace = V4L2_COLORSPACE_JPEG, 126 .fmt = 1, 127 .order = 0, 128 }, { 129 .code = V4L2_MBUS_FMT_VYUY8_2X8, 130 .colorspace = V4L2_COLORSPACE_JPEG, 131 .fmt = 1, 132 .order = 1, 133 }, { 134 .code = V4L2_MBUS_FMT_YUYV8_2X8, 135 .colorspace = V4L2_COLORSPACE_JPEG, 136 .fmt = 1, 137 .order = 2, 138 }, { 139 .code = V4L2_MBUS_FMT_YVYU8_2X8, 140 .colorspace = V4L2_COLORSPACE_JPEG, 141 .fmt = 1, 142 .order = 3, 143 }, { 144 .code = V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE, 145 .colorspace = V4L2_COLORSPACE_SRGB, 146 .fmt = 8, 147 .order = 2, 148 }, { 149 .code = V4L2_MBUS_FMT_RGB565_2X8_LE, 150 .colorspace = V4L2_COLORSPACE_SRGB, 151 .fmt = 4, 152 .order = 2, 153 }, 154}; 155 156/************************************************************************ 157 158 159 general function 160 161 162************************************************************************/ 163static struct mt9t112_priv *to_mt9t112(const struct i2c_client *client) 164{ 165 return container_of(i2c_get_clientdata(client), 166 struct mt9t112_priv, 167 subdev); 168} 169 170static int __mt9t112_reg_read(const struct i2c_client *client, u16 command) 171{ 172 struct i2c_msg msg[2]; 173 u8 buf[2]; 174 int ret; 175 176 command = swab16(command); 177 178 msg[0].addr = client->addr; 179 msg[0].flags = 0; 180 msg[0].len = 2; 181 msg[0].buf = (u8 *)&command; 182 183 msg[1].addr = client->addr; 184 msg[1].flags = I2C_M_RD; 185 msg[1].len = 2; 186 msg[1].buf = buf; 187 188 /* 189 * if return value of this function is < 0, 190 * it mean error. 191 * else, under 16bit is valid data. 192 */ 193 ret = i2c_transfer(client->adapter, msg, 2); 194 if (ret < 0) 195 return ret; 196 197 memcpy(&ret, buf, 2); 198 return swab16(ret); 199} 200 201static int __mt9t112_reg_write(const struct i2c_client *client, 202 u16 command, u16 data) 203{ 204 struct i2c_msg msg; 205 u8 buf[4]; 206 int ret; 207 208 command = swab16(command); 209 data = swab16(data); 210 211 memcpy(buf + 0, &command, 2); 212 memcpy(buf + 2, &data, 2); 213 214 msg.addr = client->addr; 215 msg.flags = 0; 216 msg.len = 4; 217 msg.buf = buf; 218 219 /* 220 * i2c_transfer return message length, 221 * but this function should return 0 if correct case 222 */ 223 ret = i2c_transfer(client->adapter, &msg, 1); 224 if (ret >= 0) 225 ret = 0; 226 227 return ret; 228} 229 230static int __mt9t112_reg_mask_set(const struct i2c_client *client, 231 u16 command, 232 u16 mask, 233 u16 set) 234{ 235 int val = __mt9t112_reg_read(client, command); 236 if (val < 0) 237 return val; 238 239 val &= ~mask; 240 val |= set & mask; 241 242 return __mt9t112_reg_write(client, command, val); 243} 244 245/* mcu access */ 246static int __mt9t112_mcu_read(const struct i2c_client *client, u16 command) 247{ 248 int ret; 249 250 ret = __mt9t112_reg_write(client, 0x098E, command); 251 if (ret < 0) 252 return ret; 253 254 return __mt9t112_reg_read(client, 0x0990); 255} 256 257static int __mt9t112_mcu_write(const struct i2c_client *client, 258 u16 command, u16 data) 259{ 260 int ret; 261 262 ret = __mt9t112_reg_write(client, 0x098E, command); 263 if (ret < 0) 264 return ret; 265 266 return __mt9t112_reg_write(client, 0x0990, data); 267} 268 269static int __mt9t112_mcu_mask_set(const struct i2c_client *client, 270 u16 command, 271 u16 mask, 272 u16 set) 273{ 274 int val = __mt9t112_mcu_read(client, command); 275 if (val < 0) 276 return val; 277 278 val &= ~mask; 279 val |= set & mask; 280 281 return __mt9t112_mcu_write(client, command, val); 282} 283 284static int mt9t112_reset(const struct i2c_client *client) 285{ 286 int ret; 287 288 mt9t112_reg_mask_set(ret, client, 0x001a, 0x0001, 0x0001); 289 msleep(1); 290 mt9t112_reg_mask_set(ret, client, 0x001a, 0x0001, 0x0000); 291 292 return ret; 293} 294 295#ifndef EXT_CLOCK 296#define CLOCK_INFO(a, b) 297#else 298#define CLOCK_INFO(a, b) mt9t112_clock_info(a, b) 299static int mt9t112_clock_info(const struct i2c_client *client, u32 ext) 300{ 301 int m, n, p1, p2, p3, p4, p5, p6, p7; 302 u32 vco, clk; 303 char *enable; 304 305 ext /= 1000; /* kbyte order */ 306 307 mt9t112_reg_read(n, client, 0x0012); 308 p1 = n & 0x000f; 309 n = n >> 4; 310 p2 = n & 0x000f; 311 n = n >> 4; 312 p3 = n & 0x000f; 313 314 mt9t112_reg_read(n, client, 0x002a); 315 p4 = n & 0x000f; 316 n = n >> 4; 317 p5 = n & 0x000f; 318 n = n >> 4; 319 p6 = n & 0x000f; 320 321 mt9t112_reg_read(n, client, 0x002c); 322 p7 = n & 0x000f; 323 324 mt9t112_reg_read(n, client, 0x0010); 325 m = n & 0x00ff; 326 n = (n >> 8) & 0x003f; 327 328 enable = ((6000 > ext) || (54000 < ext)) ? "X" : ""; 329 dev_info(&client->dev, "EXTCLK : %10u K %s\n", ext, enable); 330 331 vco = 2 * m * ext / (n+1); 332 enable = ((384000 > vco) || (768000 < vco)) ? "X" : ""; 333 dev_info(&client->dev, "VCO : %10u K %s\n", vco, enable); 334 335 clk = vco / (p1+1) / (p2+1); 336 enable = (96000 < clk) ? "X" : ""; 337 dev_info(&client->dev, "PIXCLK : %10u K %s\n", clk, enable); 338 339 clk = vco / (p3+1); 340 enable = (768000 < clk) ? "X" : ""; 341 dev_info(&client->dev, "MIPICLK : %10u K %s\n", clk, enable); 342 343 clk = vco / (p6+1); 344 enable = (96000 < clk) ? "X" : ""; 345 dev_info(&client->dev, "MCU CLK : %10u K %s\n", clk, enable); 346 347 clk = vco / (p5+1); 348 enable = (54000 < clk) ? "X" : ""; 349 dev_info(&client->dev, "SOC CLK : %10u K %s\n", clk, enable); 350 351 clk = vco / (p4+1); 352 enable = (70000 < clk) ? "X" : ""; 353 dev_info(&client->dev, "Sensor CLK : %10u K %s\n", clk, enable); 354 355 clk = vco / (p7+1); 356 dev_info(&client->dev, "External sensor : %10u K\n", clk); 357 358 clk = ext / (n+1); 359 enable = ((2000 > clk) || (24000 < clk)) ? "X" : ""; 360 dev_info(&client->dev, "PFD : %10u K %s\n", clk, enable); 361 362 return 0; 363} 364#endif 365 366static void mt9t112_frame_check(u32 *width, u32 *height) 367{ 368 if (*width > MAX_WIDTH) 369 *width = MAX_WIDTH; 370 371 if (*height > MAX_HEIGHT) 372 *height = MAX_HEIGHT; 373} 374 375static int mt9t112_set_a_frame_size(const struct i2c_client *client, 376 u16 width, 377 u16 height) 378{ 379 int ret; 380 u16 wstart = (MAX_WIDTH - width) / 2; 381 u16 hstart = (MAX_HEIGHT - height) / 2; 382 383 /* (Context A) Image Width/Height */ 384 mt9t112_mcu_write(ret, client, VAR(26, 0), width); 385 mt9t112_mcu_write(ret, client, VAR(26, 2), height); 386 387 /* (Context A) Output Width/Height */ 388 mt9t112_mcu_write(ret, client, VAR(18, 43), 8 + width); 389 mt9t112_mcu_write(ret, client, VAR(18, 45), 8 + height); 390 391 /* (Context A) Start Row/Column */ 392 mt9t112_mcu_write(ret, client, VAR(18, 2), 4 + hstart); 393 mt9t112_mcu_write(ret, client, VAR(18, 4), 4 + wstart); 394 395 /* (Context A) End Row/Column */ 396 mt9t112_mcu_write(ret, client, VAR(18, 6), 11 + height + hstart); 397 mt9t112_mcu_write(ret, client, VAR(18, 8), 11 + width + wstart); 398 399 mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x06); 400 401 return ret; 402} 403 404static int mt9t112_set_pll_dividers(const struct i2c_client *client, 405 u8 m, u8 n, 406 u8 p1, u8 p2, u8 p3, 407 u8 p4, u8 p5, u8 p6, 408 u8 p7) 409{ 410 int ret; 411 u16 val; 412 413 /* N/M */ 414 val = (n << 8) | 415 (m << 0); 416 mt9t112_reg_mask_set(ret, client, 0x0010, 0x3fff, val); 417 418 /* P1/P2/P3 */ 419 val = ((p3 & 0x0F) << 8) | 420 ((p2 & 0x0F) << 4) | 421 ((p1 & 0x0F) << 0); 422 mt9t112_reg_mask_set(ret, client, 0x0012, 0x0fff, val); 423 424 /* P4/P5/P6 */ 425 val = (0x7 << 12) | 426 ((p6 & 0x0F) << 8) | 427 ((p5 & 0x0F) << 4) | 428 ((p4 & 0x0F) << 0); 429 mt9t112_reg_mask_set(ret, client, 0x002A, 0x7fff, val); 430 431 /* P7 */ 432 val = (0x1 << 12) | 433 ((p7 & 0x0F) << 0); 434 mt9t112_reg_mask_set(ret, client, 0x002C, 0x100f, val); 435 436 return ret; 437} 438 439static int mt9t112_init_pll(const struct i2c_client *client) 440{ 441 struct mt9t112_priv *priv = to_mt9t112(client); 442 int data, i, ret; 443 444 mt9t112_reg_mask_set(ret, client, 0x0014, 0x003, 0x0001); 445 446 /* PLL control: BYPASS PLL = 8517 */ 447 mt9t112_reg_write(ret, client, 0x0014, 0x2145); 448 449 /* Replace these registers when new timing parameters are generated */ 450 mt9t112_set_pll_dividers(client, 451 priv->info->divider.m, 452 priv->info->divider.n, 453 priv->info->divider.p1, 454 priv->info->divider.p2, 455 priv->info->divider.p3, 456 priv->info->divider.p4, 457 priv->info->divider.p5, 458 priv->info->divider.p6, 459 priv->info->divider.p7); 460 461 /* 462 * TEST_BYPASS on 463 * PLL_ENABLE on 464 * SEL_LOCK_DET on 465 * TEST_BYPASS off 466 */ 467 mt9t112_reg_write(ret, client, 0x0014, 0x2525); 468 mt9t112_reg_write(ret, client, 0x0014, 0x2527); 469 mt9t112_reg_write(ret, client, 0x0014, 0x3427); 470 mt9t112_reg_write(ret, client, 0x0014, 0x3027); 471 472 mdelay(10); 473 474 /* 475 * PLL_BYPASS off 476 * Reference clock count 477 * I2C Master Clock Divider 478 */ 479 mt9t112_reg_write(ret, client, 0x0014, 0x3046); 480 mt9t112_reg_write(ret, client, 0x0022, 0x0190); 481 mt9t112_reg_write(ret, client, 0x3B84, 0x0212); 482 483 /* External sensor clock is PLL bypass */ 484 mt9t112_reg_write(ret, client, 0x002E, 0x0500); 485 486 mt9t112_reg_mask_set(ret, client, 0x0018, 0x0002, 0x0002); 487 mt9t112_reg_mask_set(ret, client, 0x3B82, 0x0004, 0x0004); 488 489 /* MCU disabled */ 490 mt9t112_reg_mask_set(ret, client, 0x0018, 0x0004, 0x0004); 491 492 /* out of standby */ 493 mt9t112_reg_mask_set(ret, client, 0x0018, 0x0001, 0); 494 495 mdelay(50); 496 497 mt9t112_reg_write(ret, client, 0x0614, 0x0001); 498 mdelay(1); 499 mt9t112_reg_write(ret, client, 0x0614, 0x0001); 500 mdelay(1); 501 mt9t112_reg_write(ret, client, 0x0614, 0x0001); 502 mdelay(1); 503 mt9t112_reg_write(ret, client, 0x0614, 0x0001); 504 mdelay(1); 505 mt9t112_reg_write(ret, client, 0x0614, 0x0001); 506 mdelay(1); 507 mt9t112_reg_write(ret, client, 0x0614, 0x0001); 508 mdelay(1); 509 510 /* poll to verify out of standby. Must Poll this bit */ 511 for (i = 0; i < 100; i++) { 512 mt9t112_reg_read(data, client, 0x0018); 513 if (!(0x4000 & data)) 514 break; 515 516 mdelay(10); 517 } 518 519 return ret; 520} 521 522static int mt9t112_init_setting(const struct i2c_client *client) 523{ 524 525 int ret; 526 527 /* Adaptive Output Clock (A) */ 528 mt9t112_mcu_mask_set(ret, client, VAR(26, 160), 0x0040, 0x0000); 529 530 /* Read Mode (A) */ 531 mt9t112_mcu_write(ret, client, VAR(18, 12), 0x0024); 532 533 /* Fine Correction (A) */ 534 mt9t112_mcu_write(ret, client, VAR(18, 15), 0x00CC); 535 536 /* Fine IT Min (A) */ 537 mt9t112_mcu_write(ret, client, VAR(18, 17), 0x01f1); 538 539 /* Fine IT Max Margin (A) */ 540 mt9t112_mcu_write(ret, client, VAR(18, 19), 0x00fF); 541 542 /* Base Frame Lines (A) */ 543 mt9t112_mcu_write(ret, client, VAR(18, 29), 0x032D); 544 545 /* Min Line Length (A) */ 546 mt9t112_mcu_write(ret, client, VAR(18, 31), 0x073a); 547 548 /* Line Length (A) */ 549 mt9t112_mcu_write(ret, client, VAR(18, 37), 0x07d0); 550 551 /* Adaptive Output Clock (B) */ 552 mt9t112_mcu_mask_set(ret, client, VAR(27, 160), 0x0040, 0x0000); 553 554 /* Row Start (B) */ 555 mt9t112_mcu_write(ret, client, VAR(18, 74), 0x004); 556 557 /* Column Start (B) */ 558 mt9t112_mcu_write(ret, client, VAR(18, 76), 0x004); 559 560 /* Row End (B) */ 561 mt9t112_mcu_write(ret, client, VAR(18, 78), 0x60B); 562 563 /* Column End (B) */ 564 mt9t112_mcu_write(ret, client, VAR(18, 80), 0x80B); 565 566 /* Fine Correction (B) */ 567 mt9t112_mcu_write(ret, client, VAR(18, 87), 0x008C); 568 569 /* Fine IT Min (B) */ 570 mt9t112_mcu_write(ret, client, VAR(18, 89), 0x01F1); 571 572 /* Fine IT Max Margin (B) */ 573 mt9t112_mcu_write(ret, client, VAR(18, 91), 0x00FF); 574 575 /* Base Frame Lines (B) */ 576 mt9t112_mcu_write(ret, client, VAR(18, 101), 0x0668); 577 578 /* Min Line Length (B) */ 579 mt9t112_mcu_write(ret, client, VAR(18, 103), 0x0AF0); 580 581 /* Line Length (B) */ 582 mt9t112_mcu_write(ret, client, VAR(18, 109), 0x0AF0); 583 584 /* 585 * Flicker Dectection registers 586 * This section should be replaced whenever new Timing file is generated 587 * All the following registers need to be replaced 588 * Following registers are generated from Register Wizard but user can 589 * modify them. For detail see auto flicker detection tuning 590 */ 591 592 /* FD_FDPERIOD_SELECT */ 593 mt9t112_mcu_write(ret, client, VAR8(8, 5), 0x01); 594 595 /* PRI_B_CONFIG_FD_ALGO_RUN */ 596 mt9t112_mcu_write(ret, client, VAR(27, 17), 0x0003); 597 598 /* PRI_A_CONFIG_FD_ALGO_RUN */ 599 mt9t112_mcu_write(ret, client, VAR(26, 17), 0x0003); 600 601 /* 602 * AFD range detection tuning registers 603 */ 604 605 /* search_f1_50 */ 606 mt9t112_mcu_write(ret, client, VAR8(18, 165), 0x25); 607 608 /* search_f2_50 */ 609 mt9t112_mcu_write(ret, client, VAR8(18, 166), 0x28); 610 611 /* search_f1_60 */ 612 mt9t112_mcu_write(ret, client, VAR8(18, 167), 0x2C); 613 614 /* search_f2_60 */ 615 mt9t112_mcu_write(ret, client, VAR8(18, 168), 0x2F); 616 617 /* period_50Hz (A) */ 618 mt9t112_mcu_write(ret, client, VAR8(18, 68), 0xBA); 619 620 /* secret register by aptina */ 621 /* period_50Hz (A MSB) */ 622 mt9t112_mcu_write(ret, client, VAR8(18, 303), 0x00); 623 624 /* period_60Hz (A) */ 625 mt9t112_mcu_write(ret, client, VAR8(18, 69), 0x9B); 626 627 /* secret register by aptina */ 628 /* period_60Hz (A MSB) */ 629 mt9t112_mcu_write(ret, client, VAR8(18, 301), 0x00); 630 631 /* period_50Hz (B) */ 632 mt9t112_mcu_write(ret, client, VAR8(18, 140), 0x82); 633 634 /* secret register by aptina */ 635 /* period_50Hz (B) MSB */ 636 mt9t112_mcu_write(ret, client, VAR8(18, 304), 0x00); 637 638 /* period_60Hz (B) */ 639 mt9t112_mcu_write(ret, client, VAR8(18, 141), 0x6D); 640 641 /* secret register by aptina */ 642 /* period_60Hz (B) MSB */ 643 mt9t112_mcu_write(ret, client, VAR8(18, 302), 0x00); 644 645 /* FD Mode */ 646 mt9t112_mcu_write(ret, client, VAR8(8, 2), 0x10); 647 648 /* Stat_min */ 649 mt9t112_mcu_write(ret, client, VAR8(8, 9), 0x02); 650 651 /* Stat_max */ 652 mt9t112_mcu_write(ret, client, VAR8(8, 10), 0x03); 653 654 /* Min_amplitude */ 655 mt9t112_mcu_write(ret, client, VAR8(8, 12), 0x0A); 656 657 /* RX FIFO Watermark (A) */ 658 mt9t112_mcu_write(ret, client, VAR(18, 70), 0x0014); 659 660 /* RX FIFO Watermark (B) */ 661 mt9t112_mcu_write(ret, client, VAR(18, 142), 0x0014); 662 663 /* MCLK: 16MHz 664 * PCLK: 73MHz 665 * CorePixCLK: 36.5 MHz 666 */ 667 mt9t112_mcu_write(ret, client, VAR8(18, 0x0044), 133); 668 mt9t112_mcu_write(ret, client, VAR8(18, 0x0045), 110); 669 mt9t112_mcu_write(ret, client, VAR8(18, 0x008c), 130); 670 mt9t112_mcu_write(ret, client, VAR8(18, 0x008d), 108); 671 672 mt9t112_mcu_write(ret, client, VAR8(18, 0x00A5), 27); 673 mt9t112_mcu_write(ret, client, VAR8(18, 0x00a6), 30); 674 mt9t112_mcu_write(ret, client, VAR8(18, 0x00a7), 32); 675 mt9t112_mcu_write(ret, client, VAR8(18, 0x00a8), 35); 676 677 return ret; 678} 679 680static int mt9t112_auto_focus_setting(const struct i2c_client *client) 681{ 682 int ret; 683 684 mt9t112_mcu_write(ret, client, VAR(12, 13), 0x000F); 685 mt9t112_mcu_write(ret, client, VAR(12, 23), 0x0F0F); 686 mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x06); 687 688 mt9t112_reg_write(ret, client, 0x0614, 0x0000); 689 690 mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x05); 691 mt9t112_mcu_write(ret, client, VAR8(12, 2), 0x02); 692 mt9t112_mcu_write(ret, client, VAR(12, 3), 0x0002); 693 mt9t112_mcu_write(ret, client, VAR(17, 3), 0x8001); 694 mt9t112_mcu_write(ret, client, VAR(17, 11), 0x0025); 695 mt9t112_mcu_write(ret, client, VAR(17, 13), 0x0193); 696 mt9t112_mcu_write(ret, client, VAR8(17, 33), 0x18); 697 mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x05); 698 699 return ret; 700} 701 702static int mt9t112_auto_focus_trigger(const struct i2c_client *client) 703{ 704 int ret; 705 706 mt9t112_mcu_write(ret, client, VAR8(12, 25), 0x01); 707 708 return ret; 709} 710 711static int mt9t112_init_camera(const struct i2c_client *client) 712{ 713 int ret; 714 715 ECHECKER(ret, mt9t112_reset(client)); 716 717 ECHECKER(ret, mt9t112_init_pll(client)); 718 719 ECHECKER(ret, mt9t112_init_setting(client)); 720 721 ECHECKER(ret, mt9t112_auto_focus_setting(client)); 722 723 mt9t112_reg_mask_set(ret, client, 0x0018, 0x0004, 0); 724 725 /* Analog setting B */ 726 mt9t112_reg_write(ret, client, 0x3084, 0x2409); 727 mt9t112_reg_write(ret, client, 0x3092, 0x0A49); 728 mt9t112_reg_write(ret, client, 0x3094, 0x4949); 729 mt9t112_reg_write(ret, client, 0x3096, 0x4950); 730 731 /* 732 * Disable adaptive clock 733 * PRI_A_CONFIG_JPEG_OB_TX_CONTROL_VAR 734 * PRI_B_CONFIG_JPEG_OB_TX_CONTROL_VAR 735 */ 736 mt9t112_mcu_write(ret, client, VAR(26, 160), 0x0A2E); 737 mt9t112_mcu_write(ret, client, VAR(27, 160), 0x0A2E); 738 739 /* Configure STatus in Status_before_length Format and enable header */ 740 /* PRI_B_CONFIG_JPEG_OB_TX_CONTROL_VAR */ 741 mt9t112_mcu_write(ret, client, VAR(27, 144), 0x0CB4); 742 743 /* Enable JPEG in context B */ 744 /* PRI_B_CONFIG_JPEG_OB_TX_CONTROL_VAR */ 745 mt9t112_mcu_write(ret, client, VAR8(27, 142), 0x01); 746 747 /* Disable Dac_TXLO */ 748 mt9t112_reg_write(ret, client, 0x316C, 0x350F); 749 750 /* Set max slew rates */ 751 mt9t112_reg_write(ret, client, 0x1E, 0x777); 752 753 return ret; 754} 755 756/************************************************************************ 757 758 759 soc_camera_ops 760 761 762************************************************************************/ 763static int mt9t112_set_bus_param(struct soc_camera_device *icd, 764 unsigned long flags) 765{ 766 return 0; 767} 768 769static unsigned long mt9t112_query_bus_param(struct soc_camera_device *icd) 770{ 771 struct i2c_client *client = to_i2c_client(to_soc_camera_control(icd)); 772 struct mt9t112_priv *priv = to_mt9t112(client); 773 struct soc_camera_link *icl = to_soc_camera_link(icd); 774 unsigned long flags = SOCAM_MASTER | SOCAM_VSYNC_ACTIVE_HIGH | 775 SOCAM_HSYNC_ACTIVE_HIGH | SOCAM_DATA_ACTIVE_HIGH; 776 777 flags |= (priv->info->flags & MT9T112_FLAG_PCLK_RISING_EDGE) ? 778 SOCAM_PCLK_SAMPLE_RISING : SOCAM_PCLK_SAMPLE_FALLING; 779 780 if (priv->info->flags & MT9T112_FLAG_DATAWIDTH_8) 781 flags |= SOCAM_DATAWIDTH_8; 782 else 783 flags |= SOCAM_DATAWIDTH_10; 784 785 return soc_camera_apply_sensor_flags(icl, flags); 786} 787 788static struct soc_camera_ops mt9t112_ops = { 789 .set_bus_param = mt9t112_set_bus_param, 790 .query_bus_param = mt9t112_query_bus_param, 791}; 792 793/************************************************************************ 794 795 796 v4l2_subdev_core_ops 797 798 799************************************************************************/ 800static int mt9t112_g_chip_ident(struct v4l2_subdev *sd, 801 struct v4l2_dbg_chip_ident *id) 802{ 803 struct i2c_client *client = sd->priv; 804 struct mt9t112_priv *priv = to_mt9t112(client); 805 806 id->ident = priv->model; 807 id->revision = 0; 808 809 return 0; 810} 811 812#ifdef CONFIG_VIDEO_ADV_DEBUG 813static int mt9t112_g_register(struct v4l2_subdev *sd, 814 struct v4l2_dbg_register *reg) 815{ 816 struct i2c_client *client = sd->priv; 817 int ret; 818 819 reg->size = 2; 820 mt9t112_reg_read(ret, client, reg->reg); 821 822 reg->val = (__u64)ret; 823 824 return 0; 825} 826 827static int mt9t112_s_register(struct v4l2_subdev *sd, 828 struct v4l2_dbg_register *reg) 829{ 830 struct i2c_client *client = sd->priv; 831 int ret; 832 833 mt9t112_reg_write(ret, client, reg->reg, reg->val); 834 835 return ret; 836} 837#endif 838 839static struct v4l2_subdev_core_ops mt9t112_subdev_core_ops = { 840 .g_chip_ident = mt9t112_g_chip_ident, 841#ifdef CONFIG_VIDEO_ADV_DEBUG 842 .g_register = mt9t112_g_register, 843 .s_register = mt9t112_s_register, 844#endif 845}; 846 847 848/************************************************************************ 849 850 851 v4l2_subdev_video_ops 852 853 854************************************************************************/ 855static int mt9t112_s_stream(struct v4l2_subdev *sd, int enable) 856{ 857 struct i2c_client *client = sd->priv; 858 struct mt9t112_priv *priv = to_mt9t112(client); 859 int ret = 0; 860 861 if (!enable) { 862 mt9t112_set_a_frame_size(client, VGA_WIDTH, VGA_HEIGHT); 863 return ret; 864 } 865 866 if (!(priv->flags & INIT_DONE)) { 867 u16 param = (MT9T112_FLAG_PCLK_RISING_EDGE & 868 priv->info->flags) ? 0x0001 : 0x0000; 869 870 ECHECKER(ret, mt9t112_init_camera(client)); 871 872 /* Invert PCLK (Data sampled on falling edge of pixclk) */ 873 mt9t112_reg_write(ret, client, 0x3C20, param); 874 875 mdelay(5); 876 877 priv->flags |= INIT_DONE; 878 } 879 880 mt9t112_mcu_write(ret, client, VAR(26, 7), priv->format->fmt); 881 mt9t112_mcu_write(ret, client, VAR(26, 9), priv->format->order); 882 mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x06); 883 884 mt9t112_set_a_frame_size(client, 885 priv->frame.width, 886 priv->frame.height); 887 888 ECHECKER(ret, mt9t112_auto_focus_trigger(client)); 889 890 dev_dbg(&client->dev, "format : %d\n", priv->format->code); 891 dev_dbg(&client->dev, "size : %d x %d\n", 892 priv->frame.width, 893 priv->frame.height); 894 895 CLOCK_INFO(client, EXT_CLOCK); 896 897 return ret; 898} 899 900static int mt9t112_set_params(struct i2c_client *client, u32 width, u32 height, 901 enum v4l2_mbus_pixelcode code) 902{ 903 struct mt9t112_priv *priv = to_mt9t112(client); 904 int i; 905 906 priv->format = NULL; 907 908 /* 909 * frame size check 910 */ 911 mt9t112_frame_check(&width, &height); 912 913 /* 914 * get color format 915 */ 916 for (i = 0; i < ARRAY_SIZE(mt9t112_cfmts); i++) 917 if (mt9t112_cfmts[i].code == code) 918 break; 919 920 if (i == ARRAY_SIZE(mt9t112_cfmts)) 921 return -EINVAL; 922 923 priv->frame.width = (u16)width; 924 priv->frame.height = (u16)height; 925 926 priv->format = mt9t112_cfmts + i; 927 928 return 0; 929} 930 931static int mt9t112_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a) 932{ 933 a->bounds.left = 0; 934 a->bounds.top = 0; 935 a->bounds.width = VGA_WIDTH; 936 a->bounds.height = VGA_HEIGHT; 937 a->defrect = a->bounds; 938 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; 939 a->pixelaspect.numerator = 1; 940 a->pixelaspect.denominator = 1; 941 942 return 0; 943} 944 945static int mt9t112_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a) 946{ 947 a->c.left = 0; 948 a->c.top = 0; 949 a->c.width = VGA_WIDTH; 950 a->c.height = VGA_HEIGHT; 951 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; 952 953 return 0; 954} 955 956static int mt9t112_s_crop(struct v4l2_subdev *sd, struct v4l2_crop *a) 957{ 958 struct i2c_client *client = sd->priv; 959 struct v4l2_rect *rect = &a->c; 960 961 return mt9t112_set_params(client, rect->width, rect->height, 962 V4L2_MBUS_FMT_UYVY8_2X8); 963} 964 965static int mt9t112_g_fmt(struct v4l2_subdev *sd, 966 struct v4l2_mbus_framefmt *mf) 967{ 968 struct i2c_client *client = sd->priv; 969 struct mt9t112_priv *priv = to_mt9t112(client); 970 971 if (!priv->format) { 972 int ret = mt9t112_set_params(client, VGA_WIDTH, VGA_HEIGHT, 973 V4L2_MBUS_FMT_UYVY8_2X8); 974 if (ret < 0) 975 return ret; 976 } 977 978 mf->width = priv->frame.width; 979 mf->height = priv->frame.height; 980 /* TODO: set colorspace */ 981 mf->code = priv->format->code; 982 mf->field = V4L2_FIELD_NONE; 983 984 return 0; 985} 986 987static int mt9t112_s_fmt(struct v4l2_subdev *sd, 988 struct v4l2_mbus_framefmt *mf) 989{ 990 struct i2c_client *client = sd->priv; 991 992 /* TODO: set colorspace */ 993 return mt9t112_set_params(client, mf->width, mf->height, mf->code); 994} 995 996static int mt9t112_try_fmt(struct v4l2_subdev *sd, 997 struct v4l2_mbus_framefmt *mf) 998{ 999 mt9t112_frame_check(&mf->width, &mf->height); 1000 1001 /* TODO: set colorspace */ 1002 mf->field = V4L2_FIELD_NONE; 1003 1004 return 0; 1005} 1006 1007static int mt9t112_enum_fmt(struct v4l2_subdev *sd, unsigned int index, 1008 enum v4l2_mbus_pixelcode *code) 1009{ 1010 if (index >= ARRAY_SIZE(mt9t112_cfmts)) 1011 return -EINVAL; 1012 1013 *code = mt9t112_cfmts[index].code; 1014 return 0; 1015} 1016 1017static struct v4l2_subdev_video_ops mt9t112_subdev_video_ops = { 1018 .s_stream = mt9t112_s_stream, 1019 .g_mbus_fmt = mt9t112_g_fmt, 1020 .s_mbus_fmt = mt9t112_s_fmt, 1021 .try_mbus_fmt = mt9t112_try_fmt, 1022 .cropcap = mt9t112_cropcap, 1023 .g_crop = mt9t112_g_crop, 1024 .s_crop = mt9t112_s_crop, 1025 .enum_mbus_fmt = mt9t112_enum_fmt, 1026}; 1027 1028/************************************************************************ 1029 1030 1031 i2c driver 1032 1033 1034************************************************************************/ 1035static struct v4l2_subdev_ops mt9t112_subdev_ops = { 1036 .core = &mt9t112_subdev_core_ops, 1037 .video = &mt9t112_subdev_video_ops, 1038}; 1039 1040static int mt9t112_camera_probe(struct soc_camera_device *icd, 1041 struct i2c_client *client) 1042{ 1043 struct mt9t112_priv *priv = to_mt9t112(client); 1044 const char *devname; 1045 int chipid; 1046 1047 /* 1048 * We must have a parent by now. And it cannot be a wrong one. 1049 * So this entire test is completely redundant. 1050 */ 1051 if (!icd->dev.parent || 1052 to_soc_camera_host(icd->dev.parent)->nr != icd->iface) 1053 return -ENODEV; 1054 1055 /* 1056 * check and show chip ID 1057 */ 1058 mt9t112_reg_read(chipid, client, 0x0000); 1059 1060 switch (chipid) { 1061 case 0x2680: 1062 devname = "mt9t111"; 1063 priv->model = V4L2_IDENT_MT9T111; 1064 break; 1065 case 0x2682: 1066 devname = "mt9t112"; 1067 priv->model = V4L2_IDENT_MT9T112; 1068 break; 1069 default: 1070 dev_err(&client->dev, "Product ID error %04x\n", chipid); 1071 return -ENODEV; 1072 } 1073 1074 dev_info(&client->dev, "%s chip ID %04x\n", devname, chipid); 1075 1076 return 0; 1077} 1078 1079static int mt9t112_probe(struct i2c_client *client, 1080 const struct i2c_device_id *did) 1081{ 1082 struct mt9t112_priv *priv; 1083 struct soc_camera_device *icd = client->dev.platform_data; 1084 struct soc_camera_link *icl; 1085 int ret; 1086 1087 if (!icd) { 1088 dev_err(&client->dev, "mt9t112: missing soc-camera data!\n"); 1089 return -EINVAL; 1090 } 1091 1092 icl = to_soc_camera_link(icd); 1093 if (!icl || !icl->priv) 1094 return -EINVAL; 1095 1096 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 1097 if (!priv) 1098 return -ENOMEM; 1099 1100 priv->info = icl->priv; 1101 1102 v4l2_i2c_subdev_init(&priv->subdev, client, &mt9t112_subdev_ops); 1103 1104 icd->ops = &mt9t112_ops; 1105 1106 ret = mt9t112_camera_probe(icd, client); 1107 if (ret) { 1108 icd->ops = NULL; 1109 kfree(priv); 1110 } 1111 1112 return ret; 1113} 1114 1115static int mt9t112_remove(struct i2c_client *client) 1116{ 1117 struct mt9t112_priv *priv = to_mt9t112(client); 1118 struct soc_camera_device *icd = client->dev.platform_data; 1119 1120 icd->ops = NULL; 1121 kfree(priv); 1122 return 0; 1123} 1124 1125static const struct i2c_device_id mt9t112_id[] = { 1126 { "mt9t112", 0 }, 1127 { } 1128}; 1129MODULE_DEVICE_TABLE(i2c, mt9t112_id); 1130 1131static struct i2c_driver mt9t112_i2c_driver = { 1132 .driver = { 1133 .name = "mt9t112", 1134 }, 1135 .probe = mt9t112_probe, 1136 .remove = mt9t112_remove, 1137 .id_table = mt9t112_id, 1138}; 1139 1140/************************************************************************ 1141 1142 1143 module function 1144 1145 1146************************************************************************/ 1147static int __init mt9t112_module_init(void) 1148{ 1149 return i2c_add_driver(&mt9t112_i2c_driver); 1150} 1151 1152static void __exit mt9t112_module_exit(void) 1153{ 1154 i2c_del_driver(&mt9t112_i2c_driver); 1155} 1156 1157module_init(mt9t112_module_init); 1158module_exit(mt9t112_module_exit); 1159 1160MODULE_DESCRIPTION("SoC Camera driver for mt9t112"); 1161MODULE_AUTHOR("Kuninori Morimoto"); 1162MODULE_LICENSE("GPL v2"); 1163