1/* 2 * VPIF header file 3 * 4 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation version 2. 9 * 10 * This program is distributed .as is. WITHOUT ANY WARRANTY of any 11 * kind, whether express or implied; without even the implied warranty 12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16#ifndef VPIF_H 17#define VPIF_H 18 19#include <linux/io.h> 20#include <linux/videodev2.h> 21#include <mach/hardware.h> 22#include <mach/dm646x.h> 23 24/* Maximum channel allowed */ 25#define VPIF_NUM_CHANNELS (4) 26#define VPIF_CAPTURE_NUM_CHANNELS (2) 27#define VPIF_DISPLAY_NUM_CHANNELS (2) 28 29/* Macros to read/write registers */ 30extern void __iomem *vpif_base; 31extern spinlock_t vpif_lock; 32 33#define regr(reg) readl((reg) + vpif_base) 34#define regw(value, reg) writel(value, (reg + vpif_base)) 35 36/* Register Addresss Offsets */ 37#define VPIF_PID (0x0000) 38#define VPIF_CH0_CTRL (0x0004) 39#define VPIF_CH1_CTRL (0x0008) 40#define VPIF_CH2_CTRL (0x000C) 41#define VPIF_CH3_CTRL (0x0010) 42 43#define VPIF_INTEN (0x0020) 44#define VPIF_INTEN_SET (0x0024) 45#define VPIF_INTEN_CLR (0x0028) 46#define VPIF_STATUS (0x002C) 47#define VPIF_STATUS_CLR (0x0030) 48#define VPIF_EMULATION_CTRL (0x0034) 49#define VPIF_REQ_SIZE (0x0038) 50 51#define VPIF_CH0_TOP_STRT_ADD_LUMA (0x0040) 52#define VPIF_CH0_BTM_STRT_ADD_LUMA (0x0044) 53#define VPIF_CH0_TOP_STRT_ADD_CHROMA (0x0048) 54#define VPIF_CH0_BTM_STRT_ADD_CHROMA (0x004c) 55#define VPIF_CH0_TOP_STRT_ADD_HANC (0x0050) 56#define VPIF_CH0_BTM_STRT_ADD_HANC (0x0054) 57#define VPIF_CH0_TOP_STRT_ADD_VANC (0x0058) 58#define VPIF_CH0_BTM_STRT_ADD_VANC (0x005c) 59#define VPIF_CH0_SP_CFG (0x0060) 60#define VPIF_CH0_IMG_ADD_OFST (0x0064) 61#define VPIF_CH0_HANC_ADD_OFST (0x0068) 62#define VPIF_CH0_H_CFG (0x006c) 63#define VPIF_CH0_V_CFG_00 (0x0070) 64#define VPIF_CH0_V_CFG_01 (0x0074) 65#define VPIF_CH0_V_CFG_02 (0x0078) 66#define VPIF_CH0_V_CFG_03 (0x007c) 67 68#define VPIF_CH1_TOP_STRT_ADD_LUMA (0x0080) 69#define VPIF_CH1_BTM_STRT_ADD_LUMA (0x0084) 70#define VPIF_CH1_TOP_STRT_ADD_CHROMA (0x0088) 71#define VPIF_CH1_BTM_STRT_ADD_CHROMA (0x008c) 72#define VPIF_CH1_TOP_STRT_ADD_HANC (0x0090) 73#define VPIF_CH1_BTM_STRT_ADD_HANC (0x0094) 74#define VPIF_CH1_TOP_STRT_ADD_VANC (0x0098) 75#define VPIF_CH1_BTM_STRT_ADD_VANC (0x009c) 76#define VPIF_CH1_SP_CFG (0x00a0) 77#define VPIF_CH1_IMG_ADD_OFST (0x00a4) 78#define VPIF_CH1_HANC_ADD_OFST (0x00a8) 79#define VPIF_CH1_H_CFG (0x00ac) 80#define VPIF_CH1_V_CFG_00 (0x00b0) 81#define VPIF_CH1_V_CFG_01 (0x00b4) 82#define VPIF_CH1_V_CFG_02 (0x00b8) 83#define VPIF_CH1_V_CFG_03 (0x00bc) 84 85#define VPIF_CH2_TOP_STRT_ADD_LUMA (0x00c0) 86#define VPIF_CH2_BTM_STRT_ADD_LUMA (0x00c4) 87#define VPIF_CH2_TOP_STRT_ADD_CHROMA (0x00c8) 88#define VPIF_CH2_BTM_STRT_ADD_CHROMA (0x00cc) 89#define VPIF_CH2_TOP_STRT_ADD_HANC (0x00d0) 90#define VPIF_CH2_BTM_STRT_ADD_HANC (0x00d4) 91#define VPIF_CH2_TOP_STRT_ADD_VANC (0x00d8) 92#define VPIF_CH2_BTM_STRT_ADD_VANC (0x00dc) 93#define VPIF_CH2_SP_CFG (0x00e0) 94#define VPIF_CH2_IMG_ADD_OFST (0x00e4) 95#define VPIF_CH2_HANC_ADD_OFST (0x00e8) 96#define VPIF_CH2_H_CFG (0x00ec) 97#define VPIF_CH2_V_CFG_00 (0x00f0) 98#define VPIF_CH2_V_CFG_01 (0x00f4) 99#define VPIF_CH2_V_CFG_02 (0x00f8) 100#define VPIF_CH2_V_CFG_03 (0x00fc) 101#define VPIF_CH2_HANC0_STRT (0x0100) 102#define VPIF_CH2_HANC0_SIZE (0x0104) 103#define VPIF_CH2_HANC1_STRT (0x0108) 104#define VPIF_CH2_HANC1_SIZE (0x010c) 105#define VPIF_CH2_VANC0_STRT (0x0110) 106#define VPIF_CH2_VANC0_SIZE (0x0114) 107#define VPIF_CH2_VANC1_STRT (0x0118) 108#define VPIF_CH2_VANC1_SIZE (0x011c) 109 110#define VPIF_CH3_TOP_STRT_ADD_LUMA (0x0140) 111#define VPIF_CH3_BTM_STRT_ADD_LUMA (0x0144) 112#define VPIF_CH3_TOP_STRT_ADD_CHROMA (0x0148) 113#define VPIF_CH3_BTM_STRT_ADD_CHROMA (0x014c) 114#define VPIF_CH3_TOP_STRT_ADD_HANC (0x0150) 115#define VPIF_CH3_BTM_STRT_ADD_HANC (0x0154) 116#define VPIF_CH3_TOP_STRT_ADD_VANC (0x0158) 117#define VPIF_CH3_BTM_STRT_ADD_VANC (0x015c) 118#define VPIF_CH3_SP_CFG (0x0160) 119#define VPIF_CH3_IMG_ADD_OFST (0x0164) 120#define VPIF_CH3_HANC_ADD_OFST (0x0168) 121#define VPIF_CH3_H_CFG (0x016c) 122#define VPIF_CH3_V_CFG_00 (0x0170) 123#define VPIF_CH3_V_CFG_01 (0x0174) 124#define VPIF_CH3_V_CFG_02 (0x0178) 125#define VPIF_CH3_V_CFG_03 (0x017c) 126#define VPIF_CH3_HANC0_STRT (0x0180) 127#define VPIF_CH3_HANC0_SIZE (0x0184) 128#define VPIF_CH3_HANC1_STRT (0x0188) 129#define VPIF_CH3_HANC1_SIZE (0x018c) 130#define VPIF_CH3_VANC0_STRT (0x0190) 131#define VPIF_CH3_VANC0_SIZE (0x0194) 132#define VPIF_CH3_VANC1_STRT (0x0198) 133#define VPIF_CH3_VANC1_SIZE (0x019c) 134 135#define VPIF_IODFT_CTRL (0x01c0) 136 137/* Functions for bit Manipulation */ 138static inline void vpif_set_bit(u32 reg, u32 bit) 139{ 140 regw((regr(reg)) | (0x01 << bit), reg); 141} 142 143static inline void vpif_clr_bit(u32 reg, u32 bit) 144{ 145 regw(((regr(reg)) & ~(0x01 << bit)), reg); 146} 147 148/* Macro for Generating mask */ 149#ifdef GENERATE_MASK 150#undef GENERATE_MASK 151#endif 152 153#define GENERATE_MASK(bits, pos) \ 154 ((((0xFFFFFFFF) << (32 - bits)) >> (32 - bits)) << pos) 155 156/* Bit positions in the channel control registers */ 157#define VPIF_CH_DATA_MODE_BIT (2) 158#define VPIF_CH_YC_MUX_BIT (3) 159#define VPIF_CH_SDR_FMT_BIT (4) 160#define VPIF_CH_HANC_EN_BIT (8) 161#define VPIF_CH_VANC_EN_BIT (9) 162 163#define VPIF_CAPTURE_CH_NIP (10) 164#define VPIF_DISPLAY_CH_NIP (11) 165 166#define VPIF_DISPLAY_PIX_EN_BIT (10) 167 168#define VPIF_CH_INPUT_FIELD_FRAME_BIT (12) 169 170#define VPIF_CH_FID_POLARITY_BIT (15) 171#define VPIF_CH_V_VALID_POLARITY_BIT (14) 172#define VPIF_CH_H_VALID_POLARITY_BIT (13) 173#define VPIF_CH_DATA_WIDTH_BIT (28) 174 175#define VPIF_CH_CLK_EDGE_CTRL_BIT (31) 176 177/* Mask various length */ 178#define VPIF_CH_EAVSAV_MASK GENERATE_MASK(13, 0) 179#define VPIF_CH_LEN_MASK GENERATE_MASK(12, 0) 180#define VPIF_CH_WIDTH_MASK GENERATE_MASK(13, 0) 181#define VPIF_CH_LEN_SHIFT (16) 182 183/* VPIF masks for registers */ 184#define VPIF_REQ_SIZE_MASK (0x1ff) 185 186/* bit posotion of interrupt vpif_ch_intr register */ 187#define VPIF_INTEN_FRAME_CH0 (0x00000001) 188#define VPIF_INTEN_FRAME_CH1 (0x00000002) 189#define VPIF_INTEN_FRAME_CH2 (0x00000004) 190#define VPIF_INTEN_FRAME_CH3 (0x00000008) 191 192/* bit position of clock and channel enable in vpif_chn_ctrl register */ 193 194#define VPIF_CH0_CLK_EN (0x00000002) 195#define VPIF_CH0_EN (0x00000001) 196#define VPIF_CH1_CLK_EN (0x00000002) 197#define VPIF_CH1_EN (0x00000001) 198#define VPIF_CH2_CLK_EN (0x00000002) 199#define VPIF_CH2_EN (0x00000001) 200#define VPIF_CH3_CLK_EN (0x00000002) 201#define VPIF_CH3_EN (0x00000001) 202#define VPIF_CH_CLK_EN (0x00000002) 203#define VPIF_CH_EN (0x00000001) 204 205#define VPIF_INT_TOP (0x00) 206#define VPIF_INT_BOTTOM (0x01) 207#define VPIF_INT_BOTH (0x02) 208 209#define VPIF_CH0_INT_CTRL_SHIFT (6) 210#define VPIF_CH1_INT_CTRL_SHIFT (6) 211#define VPIF_CH2_INT_CTRL_SHIFT (6) 212#define VPIF_CH3_INT_CTRL_SHIFT (6) 213#define VPIF_CH_INT_CTRL_SHIFT (6) 214 215/* enabled interrupt on both the fields on vpid_ch0_ctrl register */ 216#define channel0_intr_assert() (regw((regr(VPIF_CH0_CTRL)|\ 217 (VPIF_INT_BOTH << VPIF_CH0_INT_CTRL_SHIFT)), VPIF_CH0_CTRL)) 218 219/* enabled interrupt on both the fields on vpid_ch1_ctrl register */ 220#define channel1_intr_assert() (regw((regr(VPIF_CH1_CTRL)|\ 221 (VPIF_INT_BOTH << VPIF_CH1_INT_CTRL_SHIFT)), VPIF_CH1_CTRL)) 222 223/* enabled interrupt on both the fields on vpid_ch0_ctrl register */ 224#define channel2_intr_assert() (regw((regr(VPIF_CH2_CTRL)|\ 225 (VPIF_INT_BOTH << VPIF_CH2_INT_CTRL_SHIFT)), VPIF_CH2_CTRL)) 226 227/* enabled interrupt on both the fields on vpid_ch1_ctrl register */ 228#define channel3_intr_assert() (regw((regr(VPIF_CH3_CTRL)|\ 229 (VPIF_INT_BOTH << VPIF_CH3_INT_CTRL_SHIFT)), VPIF_CH3_CTRL)) 230 231#define VPIF_CH_FID_MASK (0x20) 232#define VPIF_CH_FID_SHIFT (5) 233 234#define VPIF_NTSC_VBI_START_FIELD0 (1) 235#define VPIF_NTSC_VBI_START_FIELD1 (263) 236#define VPIF_PAL_VBI_START_FIELD0 (624) 237#define VPIF_PAL_VBI_START_FIELD1 (311) 238 239#define VPIF_NTSC_HBI_START_FIELD0 (1) 240#define VPIF_NTSC_HBI_START_FIELD1 (263) 241#define VPIF_PAL_HBI_START_FIELD0 (624) 242#define VPIF_PAL_HBI_START_FIELD1 (311) 243 244#define VPIF_NTSC_VBI_COUNT_FIELD0 (20) 245#define VPIF_NTSC_VBI_COUNT_FIELD1 (19) 246#define VPIF_PAL_VBI_COUNT_FIELD0 (24) 247#define VPIF_PAL_VBI_COUNT_FIELD1 (25) 248 249#define VPIF_NTSC_HBI_COUNT_FIELD0 (263) 250#define VPIF_NTSC_HBI_COUNT_FIELD1 (262) 251#define VPIF_PAL_HBI_COUNT_FIELD0 (312) 252#define VPIF_PAL_HBI_COUNT_FIELD1 (313) 253 254#define VPIF_NTSC_VBI_SAMPLES_PER_LINE (720) 255#define VPIF_PAL_VBI_SAMPLES_PER_LINE (720) 256#define VPIF_NTSC_HBI_SAMPLES_PER_LINE (268) 257#define VPIF_PAL_HBI_SAMPLES_PER_LINE (280) 258 259#define VPIF_CH_VANC_EN (0x20) 260#define VPIF_DMA_REQ_SIZE (0x080) 261#define VPIF_EMULATION_DISABLE (0x01) 262 263extern u8 irq_vpif_capture_channel[VPIF_NUM_CHANNELS]; 264 265/* inline function to enable/disable channel0 */ 266static inline void enable_channel0(int enable) 267{ 268 if (enable) 269 regw((regr(VPIF_CH0_CTRL) | (VPIF_CH0_EN)), VPIF_CH0_CTRL); 270 else 271 regw((regr(VPIF_CH0_CTRL) & (~VPIF_CH0_EN)), VPIF_CH0_CTRL); 272} 273 274/* inline function to enable/disable channel1 */ 275static inline void enable_channel1(int enable) 276{ 277 if (enable) 278 regw((regr(VPIF_CH1_CTRL) | (VPIF_CH1_EN)), VPIF_CH1_CTRL); 279 else 280 regw((regr(VPIF_CH1_CTRL) & (~VPIF_CH1_EN)), VPIF_CH1_CTRL); 281} 282 283/* inline function to enable interrupt for channel0 */ 284static inline void channel0_intr_enable(int enable) 285{ 286 unsigned long flags; 287 288 spin_lock_irqsave(&vpif_lock, flags); 289 290 if (enable) { 291 regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN); 292 regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET); 293 294 regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH0), VPIF_INTEN); 295 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH0), 296 VPIF_INTEN_SET); 297 } else { 298 regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH0)), VPIF_INTEN); 299 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH0), 300 VPIF_INTEN_SET); 301 } 302 spin_unlock_irqrestore(&vpif_lock, flags); 303} 304 305/* inline function to enable interrupt for channel1 */ 306static inline void channel1_intr_enable(int enable) 307{ 308 unsigned long flags; 309 310 spin_lock_irqsave(&vpif_lock, flags); 311 312 if (enable) { 313 regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN); 314 regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET); 315 316 regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH1), VPIF_INTEN); 317 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH1), 318 VPIF_INTEN_SET); 319 } else { 320 regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH1)), VPIF_INTEN); 321 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH1), 322 VPIF_INTEN_SET); 323 } 324 spin_unlock_irqrestore(&vpif_lock, flags); 325} 326 327/* inline function to set buffer addresses in case of Y/C non mux mode */ 328static inline void ch0_set_videobuf_addr_yc_nmux(unsigned long top_strt_luma, 329 unsigned long btm_strt_luma, 330 unsigned long top_strt_chroma, 331 unsigned long btm_strt_chroma) 332{ 333 regw(top_strt_luma, VPIF_CH0_TOP_STRT_ADD_LUMA); 334 regw(btm_strt_luma, VPIF_CH0_BTM_STRT_ADD_LUMA); 335 regw(top_strt_chroma, VPIF_CH1_TOP_STRT_ADD_CHROMA); 336 regw(btm_strt_chroma, VPIF_CH1_BTM_STRT_ADD_CHROMA); 337} 338 339/* inline function to set buffer addresses in VPIF registers for video data */ 340static inline void ch0_set_videobuf_addr(unsigned long top_strt_luma, 341 unsigned long btm_strt_luma, 342 unsigned long top_strt_chroma, 343 unsigned long btm_strt_chroma) 344{ 345 regw(top_strt_luma, VPIF_CH0_TOP_STRT_ADD_LUMA); 346 regw(btm_strt_luma, VPIF_CH0_BTM_STRT_ADD_LUMA); 347 regw(top_strt_chroma, VPIF_CH0_TOP_STRT_ADD_CHROMA); 348 regw(btm_strt_chroma, VPIF_CH0_BTM_STRT_ADD_CHROMA); 349} 350 351static inline void ch1_set_videobuf_addr(unsigned long top_strt_luma, 352 unsigned long btm_strt_luma, 353 unsigned long top_strt_chroma, 354 unsigned long btm_strt_chroma) 355{ 356 357 regw(top_strt_luma, VPIF_CH1_TOP_STRT_ADD_LUMA); 358 regw(btm_strt_luma, VPIF_CH1_BTM_STRT_ADD_LUMA); 359 regw(top_strt_chroma, VPIF_CH1_TOP_STRT_ADD_CHROMA); 360 regw(btm_strt_chroma, VPIF_CH1_BTM_STRT_ADD_CHROMA); 361} 362 363static inline void ch0_set_vbi_addr(unsigned long top_vbi, 364 unsigned long btm_vbi, unsigned long a, unsigned long b) 365{ 366 regw(top_vbi, VPIF_CH0_TOP_STRT_ADD_VANC); 367 regw(btm_vbi, VPIF_CH0_BTM_STRT_ADD_VANC); 368} 369 370static inline void ch0_set_hbi_addr(unsigned long top_vbi, 371 unsigned long btm_vbi, unsigned long a, unsigned long b) 372{ 373 regw(top_vbi, VPIF_CH0_TOP_STRT_ADD_HANC); 374 regw(btm_vbi, VPIF_CH0_BTM_STRT_ADD_HANC); 375} 376 377static inline void ch1_set_vbi_addr(unsigned long top_vbi, 378 unsigned long btm_vbi, unsigned long a, unsigned long b) 379{ 380 regw(top_vbi, VPIF_CH1_TOP_STRT_ADD_VANC); 381 regw(btm_vbi, VPIF_CH1_BTM_STRT_ADD_VANC); 382} 383 384static inline void ch1_set_hbi_addr(unsigned long top_vbi, 385 unsigned long btm_vbi, unsigned long a, unsigned long b) 386{ 387 regw(top_vbi, VPIF_CH1_TOP_STRT_ADD_HANC); 388 regw(btm_vbi, VPIF_CH1_BTM_STRT_ADD_HANC); 389} 390 391/* Inline function to enable raw vbi in the given channel */ 392static inline void disable_raw_feature(u8 channel_id, u8 index) 393{ 394 u32 ctrl_reg; 395 if (0 == channel_id) 396 ctrl_reg = VPIF_CH0_CTRL; 397 else 398 ctrl_reg = VPIF_CH1_CTRL; 399 400 if (1 == index) 401 vpif_clr_bit(ctrl_reg, VPIF_CH_VANC_EN_BIT); 402 else 403 vpif_clr_bit(ctrl_reg, VPIF_CH_HANC_EN_BIT); 404} 405 406static inline void enable_raw_feature(u8 channel_id, u8 index) 407{ 408 u32 ctrl_reg; 409 if (0 == channel_id) 410 ctrl_reg = VPIF_CH0_CTRL; 411 else 412 ctrl_reg = VPIF_CH1_CTRL; 413 414 if (1 == index) 415 vpif_set_bit(ctrl_reg, VPIF_CH_VANC_EN_BIT); 416 else 417 vpif_set_bit(ctrl_reg, VPIF_CH_HANC_EN_BIT); 418} 419 420/* inline function to enable/disable channel2 */ 421static inline void enable_channel2(int enable) 422{ 423 if (enable) { 424 regw((regr(VPIF_CH2_CTRL) | (VPIF_CH2_CLK_EN)), VPIF_CH2_CTRL); 425 regw((regr(VPIF_CH2_CTRL) | (VPIF_CH2_EN)), VPIF_CH2_CTRL); 426 } else { 427 regw((regr(VPIF_CH2_CTRL) & (~VPIF_CH2_CLK_EN)), VPIF_CH2_CTRL); 428 regw((regr(VPIF_CH2_CTRL) & (~VPIF_CH2_EN)), VPIF_CH2_CTRL); 429 } 430} 431 432/* inline function to enable/disable channel3 */ 433static inline void enable_channel3(int enable) 434{ 435 if (enable) { 436 regw((regr(VPIF_CH3_CTRL) | (VPIF_CH3_CLK_EN)), VPIF_CH3_CTRL); 437 regw((regr(VPIF_CH3_CTRL) | (VPIF_CH3_EN)), VPIF_CH3_CTRL); 438 } else { 439 regw((regr(VPIF_CH3_CTRL) & (~VPIF_CH3_CLK_EN)), VPIF_CH3_CTRL); 440 regw((regr(VPIF_CH3_CTRL) & (~VPIF_CH3_EN)), VPIF_CH3_CTRL); 441 } 442} 443 444/* inline function to enable interrupt for channel2 */ 445static inline void channel2_intr_enable(int enable) 446{ 447 unsigned long flags; 448 449 spin_lock_irqsave(&vpif_lock, flags); 450 451 if (enable) { 452 regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN); 453 regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET); 454 regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH2), VPIF_INTEN); 455 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH2), 456 VPIF_INTEN_SET); 457 } else { 458 regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH2)), VPIF_INTEN); 459 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH2), 460 VPIF_INTEN_SET); 461 } 462 spin_unlock_irqrestore(&vpif_lock, flags); 463} 464 465/* inline function to enable interrupt for channel3 */ 466static inline void channel3_intr_enable(int enable) 467{ 468 unsigned long flags; 469 470 spin_lock_irqsave(&vpif_lock, flags); 471 472 if (enable) { 473 regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN); 474 regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET); 475 476 regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH3), VPIF_INTEN); 477 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH3), 478 VPIF_INTEN_SET); 479 } else { 480 regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH3)), VPIF_INTEN); 481 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH3), 482 VPIF_INTEN_SET); 483 } 484 spin_unlock_irqrestore(&vpif_lock, flags); 485} 486 487/* inline function to enable raw vbi data for channel2 */ 488static inline void channel2_raw_enable(int enable, u8 index) 489{ 490 u32 mask; 491 492 if (1 == index) 493 mask = VPIF_CH_VANC_EN_BIT; 494 else 495 mask = VPIF_CH_HANC_EN_BIT; 496 497 if (enable) 498 vpif_set_bit(VPIF_CH2_CTRL, mask); 499 else 500 vpif_clr_bit(VPIF_CH2_CTRL, mask); 501} 502 503/* inline function to enable raw vbi data for channel3*/ 504static inline void channel3_raw_enable(int enable, u8 index) 505{ 506 u32 mask; 507 508 if (1 == index) 509 mask = VPIF_CH_VANC_EN_BIT; 510 else 511 mask = VPIF_CH_HANC_EN_BIT; 512 513 if (enable) 514 vpif_set_bit(VPIF_CH3_CTRL, mask); 515 else 516 vpif_clr_bit(VPIF_CH3_CTRL, mask); 517} 518 519/* inline function to set buffer addresses in case of Y/C non mux mode */ 520static inline void ch2_set_videobuf_addr_yc_nmux(unsigned long top_strt_luma, 521 unsigned long btm_strt_luma, 522 unsigned long top_strt_chroma, 523 unsigned long btm_strt_chroma) 524{ 525 regw(top_strt_luma, VPIF_CH2_TOP_STRT_ADD_LUMA); 526 regw(btm_strt_luma, VPIF_CH2_BTM_STRT_ADD_LUMA); 527 regw(top_strt_chroma, VPIF_CH3_TOP_STRT_ADD_CHROMA); 528 regw(btm_strt_chroma, VPIF_CH3_BTM_STRT_ADD_CHROMA); 529} 530 531/* inline function to set buffer addresses in VPIF registers for video data */ 532static inline void ch2_set_videobuf_addr(unsigned long top_strt_luma, 533 unsigned long btm_strt_luma, 534 unsigned long top_strt_chroma, 535 unsigned long btm_strt_chroma) 536{ 537 regw(top_strt_luma, VPIF_CH2_TOP_STRT_ADD_LUMA); 538 regw(btm_strt_luma, VPIF_CH2_BTM_STRT_ADD_LUMA); 539 regw(top_strt_chroma, VPIF_CH2_TOP_STRT_ADD_CHROMA); 540 regw(btm_strt_chroma, VPIF_CH2_BTM_STRT_ADD_CHROMA); 541} 542 543static inline void ch3_set_videobuf_addr(unsigned long top_strt_luma, 544 unsigned long btm_strt_luma, 545 unsigned long top_strt_chroma, 546 unsigned long btm_strt_chroma) 547{ 548 regw(top_strt_luma, VPIF_CH3_TOP_STRT_ADD_LUMA); 549 regw(btm_strt_luma, VPIF_CH3_BTM_STRT_ADD_LUMA); 550 regw(top_strt_chroma, VPIF_CH3_TOP_STRT_ADD_CHROMA); 551 regw(btm_strt_chroma, VPIF_CH3_BTM_STRT_ADD_CHROMA); 552} 553 554/* inline function to set buffer addresses in VPIF registers for vbi data */ 555static inline void ch2_set_vbi_addr(unsigned long top_strt_luma, 556 unsigned long btm_strt_luma, 557 unsigned long top_strt_chroma, 558 unsigned long btm_strt_chroma) 559{ 560 regw(top_strt_luma, VPIF_CH2_TOP_STRT_ADD_VANC); 561 regw(btm_strt_luma, VPIF_CH2_BTM_STRT_ADD_VANC); 562} 563 564static inline void ch3_set_vbi_addr(unsigned long top_strt_luma, 565 unsigned long btm_strt_luma, 566 unsigned long top_strt_chroma, 567 unsigned long btm_strt_chroma) 568{ 569 regw(top_strt_luma, VPIF_CH3_TOP_STRT_ADD_VANC); 570 regw(btm_strt_luma, VPIF_CH3_BTM_STRT_ADD_VANC); 571} 572 573#define VPIF_MAX_NAME (30) 574 575/* This structure will store size parameters as per the mode selected by user */ 576struct vpif_channel_config_params { 577 char name[VPIF_MAX_NAME]; /* Name of the mode */ 578 u16 width; /* Indicates width of the image */ 579 u16 height; /* Indicates height of the image */ 580 u8 fps; 581 u8 frm_fmt; /* Indicates whether this is interlaced 582 * or progressive format */ 583 u8 ycmux_mode; /* Indicates whether this mode requires 584 * single or two channels */ 585 u16 eav2sav; /* length of sav 2 eav */ 586 u16 sav2eav; /* length of sav 2 eav */ 587 u16 l1, l3, l5, l7, l9, l11; /* Other parameter configurations */ 588 u16 vsize; /* Vertical size of the image */ 589 u8 capture_format; /* Indicates whether capture format 590 * is in BT or in CCD/CMOS */ 591 u8 vbi_supported; /* Indicates whether this mode 592 * supports capturing vbi or not */ 593 u8 hd_sd; 594 v4l2_std_id stdid; 595}; 596 597struct vpif_video_params; 598struct vpif_params; 599struct vpif_vbi_params; 600 601int vpif_set_video_params(struct vpif_params *vpifparams, u8 channel_id); 602void vpif_set_vbi_display_params(struct vpif_vbi_params *vbiparams, 603 u8 channel_id); 604int vpif_channel_getfid(u8 channel_id); 605 606enum data_size { 607 _8BITS = 0, 608 _10BITS, 609 _12BITS, 610}; 611 612/* Structure for vpif parameters for raw vbi data */ 613struct vpif_vbi_params { 614 __u32 hstart0; /* Horizontal start of raw vbi data for first field */ 615 __u32 vstart0; /* Vertical start of raw vbi data for first field */ 616 __u32 hsize0; /* Horizontal size of raw vbi data for first field */ 617 __u32 vsize0; /* Vertical size of raw vbi data for first field */ 618 __u32 hstart1; /* Horizontal start of raw vbi data for second field */ 619 __u32 vstart1; /* Vertical start of raw vbi data for second field */ 620 __u32 hsize1; /* Horizontal size of raw vbi data for second field */ 621 __u32 vsize1; /* Vertical size of raw vbi data for second field */ 622}; 623 624/* structure for vpif parameters */ 625struct vpif_video_params { 626 __u8 storage_mode; /* Indicates field or frame mode */ 627 unsigned long hpitch; 628 v4l2_std_id stdid; 629}; 630 631struct vpif_params { 632 struct vpif_interface iface; 633 struct vpif_video_params video_params; 634 struct vpif_channel_config_params std_info; 635 union param { 636 struct vpif_vbi_params vbi_params; 637 enum data_size data_sz; 638 } params; 639}; 640 641#endif /* End of #ifndef VPIF_H */ 642