1/* 2 * Driver for the Conexant CX2584x Audio/Video decoder chip and related cores 3 * 4 * Integrated Consumer Infrared Controller 5 * 6 * Copyright (C) 2010 Andy Walls <awalls@md.metrocast.net> 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * as published by the Free Software Foundation; either version 2 11 * of the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 21 * 02110-1301, USA. 22 */ 23 24#include <linux/slab.h> 25#include <linux/kfifo.h> 26#include <media/cx25840.h> 27#include <media/ir-core.h> 28 29#include "cx25840-core.h" 30 31static unsigned int ir_debug; 32module_param(ir_debug, int, 0644); 33MODULE_PARM_DESC(ir_debug, "enable integrated IR debug messages"); 34 35#define CX25840_IR_REG_BASE 0x200 36 37#define CX25840_IR_CNTRL_REG 0x200 38#define CNTRL_WIN_3_3 0x00000000 39#define CNTRL_WIN_4_3 0x00000001 40#define CNTRL_WIN_3_4 0x00000002 41#define CNTRL_WIN_4_4 0x00000003 42#define CNTRL_WIN 0x00000003 43#define CNTRL_EDG_NONE 0x00000000 44#define CNTRL_EDG_FALL 0x00000004 45#define CNTRL_EDG_RISE 0x00000008 46#define CNTRL_EDG_BOTH 0x0000000C 47#define CNTRL_EDG 0x0000000C 48#define CNTRL_DMD 0x00000010 49#define CNTRL_MOD 0x00000020 50#define CNTRL_RFE 0x00000040 51#define CNTRL_TFE 0x00000080 52#define CNTRL_RXE 0x00000100 53#define CNTRL_TXE 0x00000200 54#define CNTRL_RIC 0x00000400 55#define CNTRL_TIC 0x00000800 56#define CNTRL_CPL 0x00001000 57#define CNTRL_LBM 0x00002000 58#define CNTRL_R 0x00004000 59 60#define CX25840_IR_TXCLK_REG 0x204 61#define TXCLK_TCD 0x0000FFFF 62 63#define CX25840_IR_RXCLK_REG 0x208 64#define RXCLK_RCD 0x0000FFFF 65 66#define CX25840_IR_CDUTY_REG 0x20C 67#define CDUTY_CDC 0x0000000F 68 69#define CX25840_IR_STATS_REG 0x210 70#define STATS_RTO 0x00000001 71#define STATS_ROR 0x00000002 72#define STATS_RBY 0x00000004 73#define STATS_TBY 0x00000008 74#define STATS_RSR 0x00000010 75#define STATS_TSR 0x00000020 76 77#define CX25840_IR_IRQEN_REG 0x214 78#define IRQEN_RTE 0x00000001 79#define IRQEN_ROE 0x00000002 80#define IRQEN_RSE 0x00000010 81#define IRQEN_TSE 0x00000020 82#define IRQEN_MSK 0x00000033 83 84#define CX25840_IR_FILTR_REG 0x218 85#define FILTR_LPF 0x0000FFFF 86 87#define CX25840_IR_FIFO_REG 0x23C 88#define FIFO_RXTX 0x0000FFFF 89#define FIFO_RXTX_LVL 0x00010000 90#define FIFO_RXTX_RTO 0x0001FFFF 91#define FIFO_RX_NDV 0x00020000 92#define FIFO_RX_DEPTH 8 93#define FIFO_TX_DEPTH 8 94 95#define CX25840_VIDCLK_FREQ 108000000 /* 108 MHz, BT.656 */ 96#define CX25840_IR_REFCLK_FREQ (CX25840_VIDCLK_FREQ / 2) 97 98/* 99 * We use this union internally for convenience, but callers to tx_write 100 * and rx_read will be expecting records of type struct ir_raw_event. 101 * Always ensure the size of this union is dictated by struct ir_raw_event. 102 */ 103union cx25840_ir_fifo_rec { 104 u32 hw_fifo_data; 105 struct ir_raw_event ir_core_data; 106}; 107 108#define CX25840_IR_RX_KFIFO_SIZE (256 * sizeof(union cx25840_ir_fifo_rec)) 109#define CX25840_IR_TX_KFIFO_SIZE (256 * sizeof(union cx25840_ir_fifo_rec)) 110 111struct cx25840_ir_state { 112 struct i2c_client *c; 113 114 struct v4l2_subdev_ir_parameters rx_params; 115 struct mutex rx_params_lock; /* protects Rx parameter settings cache */ 116 atomic_t rxclk_divider; 117 atomic_t rx_invert; 118 119 struct kfifo rx_kfifo; 120 spinlock_t rx_kfifo_lock; /* protect Rx data kfifo */ 121 122 struct v4l2_subdev_ir_parameters tx_params; 123 struct mutex tx_params_lock; /* protects Tx parameter settings cache */ 124 atomic_t txclk_divider; 125}; 126 127static inline struct cx25840_ir_state *to_ir_state(struct v4l2_subdev *sd) 128{ 129 struct cx25840_state *state = to_state(sd); 130 return state ? state->ir_state : NULL; 131} 132 133 134/* 135 * Rx and Tx Clock Divider register computations 136 * 137 * Note the largest clock divider value of 0xffff corresponds to: 138 * (0xffff + 1) * 1000 / 108/2 MHz = 1,213,629.629... ns 139 * which fits in 21 bits, so we'll use unsigned int for time arguments. 140 */ 141static inline u16 count_to_clock_divider(unsigned int d) 142{ 143 if (d > RXCLK_RCD + 1) 144 d = RXCLK_RCD; 145 else if (d < 2) 146 d = 1; 147 else 148 d--; 149 return (u16) d; 150} 151 152static inline u16 ns_to_clock_divider(unsigned int ns) 153{ 154 return count_to_clock_divider( 155 DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ / 1000000 * ns, 1000)); 156} 157 158static inline unsigned int clock_divider_to_ns(unsigned int divider) 159{ 160 /* Period of the Rx or Tx clock in ns */ 161 return DIV_ROUND_CLOSEST((divider + 1) * 1000, 162 CX25840_IR_REFCLK_FREQ / 1000000); 163} 164 165static inline u16 carrier_freq_to_clock_divider(unsigned int freq) 166{ 167 return count_to_clock_divider( 168 DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ, freq * 16)); 169} 170 171static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider) 172{ 173 return DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ, (divider + 1) * 16); 174} 175 176static inline u16 freq_to_clock_divider(unsigned int freq, 177 unsigned int rollovers) 178{ 179 return count_to_clock_divider( 180 DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ, freq * rollovers)); 181} 182 183static inline unsigned int clock_divider_to_freq(unsigned int divider, 184 unsigned int rollovers) 185{ 186 return DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ, 187 (divider + 1) * rollovers); 188} 189 190/* 191 * Low Pass Filter register calculations 192 * 193 * Note the largest count value of 0xffff corresponds to: 194 * 0xffff * 1000 / 108/2 MHz = 1,213,611.11... ns 195 * which fits in 21 bits, so we'll use unsigned int for time arguments. 196 */ 197static inline u16 count_to_lpf_count(unsigned int d) 198{ 199 if (d > FILTR_LPF) 200 d = FILTR_LPF; 201 else if (d < 4) 202 d = 0; 203 return (u16) d; 204} 205 206static inline u16 ns_to_lpf_count(unsigned int ns) 207{ 208 return count_to_lpf_count( 209 DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ / 1000000 * ns, 1000)); 210} 211 212static inline unsigned int lpf_count_to_ns(unsigned int count) 213{ 214 /* Duration of the Low Pass Filter rejection window in ns */ 215 return DIV_ROUND_CLOSEST(count * 1000, 216 CX25840_IR_REFCLK_FREQ / 1000000); 217} 218 219static inline unsigned int lpf_count_to_us(unsigned int count) 220{ 221 /* Duration of the Low Pass Filter rejection window in us */ 222 return DIV_ROUND_CLOSEST(count, CX25840_IR_REFCLK_FREQ / 1000000); 223} 224 225/* 226 * FIFO register pulse width count compuations 227 */ 228static u32 clock_divider_to_resolution(u16 divider) 229{ 230 /* 231 * Resolution is the duration of 1 tick of the readable portion of 232 * of the pulse width counter as read from the FIFO. The two lsb's are 233 * not readable, hence the << 2. This function returns ns. 234 */ 235 return DIV_ROUND_CLOSEST((1 << 2) * ((u32) divider + 1) * 1000, 236 CX25840_IR_REFCLK_FREQ / 1000000); 237} 238 239static u64 pulse_width_count_to_ns(u16 count, u16 divider) 240{ 241 u64 n; 242 u32 rem; 243 244 /* 245 * The 2 lsb's of the pulse width timer count are not readable, hence 246 * the (count << 2) | 0x3 247 */ 248 n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */ 249 rem = do_div(n, CX25840_IR_REFCLK_FREQ / 1000000); /* / MHz => ns */ 250 if (rem >= CX25840_IR_REFCLK_FREQ / 1000000 / 2) 251 n++; 252 return n; 253} 254 255static unsigned int pulse_width_count_to_us(u16 count, u16 divider) 256{ 257 u64 n; 258 u32 rem; 259 260 /* 261 * The 2 lsb's of the pulse width timer count are not readable, hence 262 * the (count << 2) | 0x3 263 */ 264 n = (((u64) count << 2) | 0x3) * (divider + 1); /* cycles */ 265 rem = do_div(n, CX25840_IR_REFCLK_FREQ / 1000000); /* / MHz => us */ 266 if (rem >= CX25840_IR_REFCLK_FREQ / 1000000 / 2) 267 n++; 268 return (unsigned int) n; 269} 270 271/* 272 * Pulse Clocks computations: Combined Pulse Width Count & Rx Clock Counts 273 * 274 * The total pulse clock count is an 18 bit pulse width timer count as the most 275 * significant part and (up to) 16 bit clock divider count as a modulus. 276 * When the Rx clock divider ticks down to 0, it increments the 18 bit pulse 277 * width timer count's least significant bit. 278 */ 279static u64 ns_to_pulse_clocks(u32 ns) 280{ 281 u64 clocks; 282 u32 rem; 283 clocks = CX25840_IR_REFCLK_FREQ / 1000000 * (u64) ns; /* millicycles */ 284 rem = do_div(clocks, 1000); /* /1000 = cycles */ 285 if (rem >= 1000 / 2) 286 clocks++; 287 return clocks; 288} 289 290static u16 pulse_clocks_to_clock_divider(u64 count) 291{ 292 u32 rem; 293 294 rem = do_div(count, (FIFO_RXTX << 2) | 0x3); 295 296 /* net result needs to be rounded down and decremented by 1 */ 297 if (count > RXCLK_RCD + 1) 298 count = RXCLK_RCD; 299 else if (count < 2) 300 count = 1; 301 else 302 count--; 303 return (u16) count; 304} 305 306/* 307 * IR Control Register helpers 308 */ 309enum tx_fifo_watermark { 310 TX_FIFO_HALF_EMPTY = 0, 311 TX_FIFO_EMPTY = CNTRL_TIC, 312}; 313 314enum rx_fifo_watermark { 315 RX_FIFO_HALF_FULL = 0, 316 RX_FIFO_NOT_EMPTY = CNTRL_RIC, 317}; 318 319static inline void control_tx_irq_watermark(struct i2c_client *c, 320 enum tx_fifo_watermark level) 321{ 322 cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_TIC, level); 323} 324 325static inline void control_rx_irq_watermark(struct i2c_client *c, 326 enum rx_fifo_watermark level) 327{ 328 cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_RIC, level); 329} 330 331static inline void control_tx_enable(struct i2c_client *c, bool enable) 332{ 333 cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~(CNTRL_TXE | CNTRL_TFE), 334 enable ? (CNTRL_TXE | CNTRL_TFE) : 0); 335} 336 337static inline void control_rx_enable(struct i2c_client *c, bool enable) 338{ 339 cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~(CNTRL_RXE | CNTRL_RFE), 340 enable ? (CNTRL_RXE | CNTRL_RFE) : 0); 341} 342 343static inline void control_tx_modulation_enable(struct i2c_client *c, 344 bool enable) 345{ 346 cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_MOD, 347 enable ? CNTRL_MOD : 0); 348} 349 350static inline void control_rx_demodulation_enable(struct i2c_client *c, 351 bool enable) 352{ 353 cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_DMD, 354 enable ? CNTRL_DMD : 0); 355} 356 357static inline void control_rx_s_edge_detection(struct i2c_client *c, 358 u32 edge_types) 359{ 360 cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_EDG_BOTH, 361 edge_types & CNTRL_EDG_BOTH); 362} 363 364static void control_rx_s_carrier_window(struct i2c_client *c, 365 unsigned int carrier, 366 unsigned int *carrier_range_low, 367 unsigned int *carrier_range_high) 368{ 369 u32 v; 370 unsigned int c16 = carrier * 16; 371 372 if (*carrier_range_low < DIV_ROUND_CLOSEST(c16, 16 + 3)) { 373 v = CNTRL_WIN_3_4; 374 *carrier_range_low = DIV_ROUND_CLOSEST(c16, 16 + 4); 375 } else { 376 v = CNTRL_WIN_3_3; 377 *carrier_range_low = DIV_ROUND_CLOSEST(c16, 16 + 3); 378 } 379 380 if (*carrier_range_high > DIV_ROUND_CLOSEST(c16, 16 - 3)) { 381 v |= CNTRL_WIN_4_3; 382 *carrier_range_high = DIV_ROUND_CLOSEST(c16, 16 - 4); 383 } else { 384 v |= CNTRL_WIN_3_3; 385 *carrier_range_high = DIV_ROUND_CLOSEST(c16, 16 - 3); 386 } 387 cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_WIN, v); 388} 389 390static inline void control_tx_polarity_invert(struct i2c_client *c, 391 bool invert) 392{ 393 cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_CPL, 394 invert ? CNTRL_CPL : 0); 395} 396 397/* 398 * IR Rx & Tx Clock Register helpers 399 */ 400static unsigned int txclk_tx_s_carrier(struct i2c_client *c, 401 unsigned int freq, 402 u16 *divider) 403{ 404 *divider = carrier_freq_to_clock_divider(freq); 405 cx25840_write4(c, CX25840_IR_TXCLK_REG, *divider); 406 return clock_divider_to_carrier_freq(*divider); 407} 408 409static unsigned int rxclk_rx_s_carrier(struct i2c_client *c, 410 unsigned int freq, 411 u16 *divider) 412{ 413 *divider = carrier_freq_to_clock_divider(freq); 414 cx25840_write4(c, CX25840_IR_RXCLK_REG, *divider); 415 return clock_divider_to_carrier_freq(*divider); 416} 417 418static u32 txclk_tx_s_max_pulse_width(struct i2c_client *c, u32 ns, 419 u16 *divider) 420{ 421 u64 pulse_clocks; 422 423 if (ns > IR_MAX_DURATION) 424 ns = IR_MAX_DURATION; 425 pulse_clocks = ns_to_pulse_clocks(ns); 426 *divider = pulse_clocks_to_clock_divider(pulse_clocks); 427 cx25840_write4(c, CX25840_IR_TXCLK_REG, *divider); 428 return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider); 429} 430 431static u32 rxclk_rx_s_max_pulse_width(struct i2c_client *c, u32 ns, 432 u16 *divider) 433{ 434 u64 pulse_clocks; 435 436 if (ns > IR_MAX_DURATION) 437 ns = IR_MAX_DURATION; 438 pulse_clocks = ns_to_pulse_clocks(ns); 439 *divider = pulse_clocks_to_clock_divider(pulse_clocks); 440 cx25840_write4(c, CX25840_IR_RXCLK_REG, *divider); 441 return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider); 442} 443 444/* 445 * IR Tx Carrier Duty Cycle register helpers 446 */ 447static unsigned int cduty_tx_s_duty_cycle(struct i2c_client *c, 448 unsigned int duty_cycle) 449{ 450 u32 n; 451 n = DIV_ROUND_CLOSEST(duty_cycle * 100, 625); /* 16ths of 100% */ 452 if (n != 0) 453 n--; 454 if (n > 15) 455 n = 15; 456 cx25840_write4(c, CX25840_IR_CDUTY_REG, n); 457 return DIV_ROUND_CLOSEST((n + 1) * 100, 16); 458} 459 460/* 461 * IR Filter Register helpers 462 */ 463static u32 filter_rx_s_min_width(struct i2c_client *c, u32 min_width_ns) 464{ 465 u32 count = ns_to_lpf_count(min_width_ns); 466 cx25840_write4(c, CX25840_IR_FILTR_REG, count); 467 return lpf_count_to_ns(count); 468} 469 470/* 471 * IR IRQ Enable Register helpers 472 */ 473static inline void irqenable_rx(struct v4l2_subdev *sd, u32 mask) 474{ 475 struct cx25840_state *state = to_state(sd); 476 477 if (is_cx23885(state) || is_cx23887(state)) 478 mask ^= IRQEN_MSK; 479 mask &= (IRQEN_RTE | IRQEN_ROE | IRQEN_RSE); 480 cx25840_and_or4(state->c, CX25840_IR_IRQEN_REG, 481 ~(IRQEN_RTE | IRQEN_ROE | IRQEN_RSE), mask); 482} 483 484static inline void irqenable_tx(struct v4l2_subdev *sd, u32 mask) 485{ 486 struct cx25840_state *state = to_state(sd); 487 488 if (is_cx23885(state) || is_cx23887(state)) 489 mask ^= IRQEN_MSK; 490 mask &= IRQEN_TSE; 491 cx25840_and_or4(state->c, CX25840_IR_IRQEN_REG, ~IRQEN_TSE, mask); 492} 493 494/* 495 * V4L2 Subdevice IR Ops 496 */ 497int cx25840_ir_irq_handler(struct v4l2_subdev *sd, u32 status, bool *handled) 498{ 499 struct cx25840_state *state = to_state(sd); 500 struct cx25840_ir_state *ir_state = to_ir_state(sd); 501 struct i2c_client *c = NULL; 502 unsigned long flags; 503 504 union cx25840_ir_fifo_rec rx_data[FIFO_RX_DEPTH]; 505 unsigned int i, j, k; 506 u32 events, v; 507 int tsr, rsr, rto, ror, tse, rse, rte, roe, kror; 508 u32 cntrl, irqen, stats; 509 510 *handled = false; 511 if (ir_state == NULL) 512 return -ENODEV; 513 514 c = ir_state->c; 515 516 /* Only support the IR controller for the CX2388[57] AV Core for now */ 517 if (!(is_cx23885(state) || is_cx23887(state))) 518 return -ENODEV; 519 520 cntrl = cx25840_read4(c, CX25840_IR_CNTRL_REG); 521 irqen = cx25840_read4(c, CX25840_IR_IRQEN_REG); 522 if (is_cx23885(state) || is_cx23887(state)) 523 irqen ^= IRQEN_MSK; 524 stats = cx25840_read4(c, CX25840_IR_STATS_REG); 525 526 tsr = stats & STATS_TSR; /* Tx FIFO Service Request */ 527 rsr = stats & STATS_RSR; /* Rx FIFO Service Request */ 528 rto = stats & STATS_RTO; /* Rx Pulse Width Timer Time Out */ 529 ror = stats & STATS_ROR; /* Rx FIFO Over Run */ 530 531 tse = irqen & IRQEN_TSE; /* Tx FIFO Service Request IRQ Enable */ 532 rse = irqen & IRQEN_RSE; /* Rx FIFO Service Reuqest IRQ Enable */ 533 rte = irqen & IRQEN_RTE; /* Rx Pulse Width Timer Time Out IRQ Enable */ 534 roe = irqen & IRQEN_ROE; /* Rx FIFO Over Run IRQ Enable */ 535 536 v4l2_dbg(2, ir_debug, sd, "IR IRQ Status: %s %s %s %s %s %s\n", 537 tsr ? "tsr" : " ", rsr ? "rsr" : " ", 538 rto ? "rto" : " ", ror ? "ror" : " ", 539 stats & STATS_TBY ? "tby" : " ", 540 stats & STATS_RBY ? "rby" : " "); 541 542 v4l2_dbg(2, ir_debug, sd, "IR IRQ Enables: %s %s %s %s\n", 543 tse ? "tse" : " ", rse ? "rse" : " ", 544 rte ? "rte" : " ", roe ? "roe" : " "); 545 546 /* 547 * Transmitter interrupt service 548 */ 549 if (tse && tsr) { 550 /* 551 * TODO: 552 * Check the watermark threshold setting 553 * Pull FIFO_TX_DEPTH or FIFO_TX_DEPTH/2 entries from tx_kfifo 554 * Push the data to the hardware FIFO. 555 * If there was nothing more to send in the tx_kfifo, disable 556 * the TSR IRQ and notify the v4l2_device. 557 * If there was something in the tx_kfifo, check the tx_kfifo 558 * level and notify the v4l2_device, if it is low. 559 */ 560 /* For now, inhibit TSR interrupt until Tx is implemented */ 561 irqenable_tx(sd, 0); 562 events = V4L2_SUBDEV_IR_TX_FIFO_SERVICE_REQ; 563 v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_TX_NOTIFY, &events); 564 *handled = true; 565 } 566 567 /* 568 * Receiver interrupt service 569 */ 570 kror = 0; 571 if ((rse && rsr) || (rte && rto)) { 572 /* 573 * Receive data on RSR to clear the STATS_RSR. 574 * Receive data on RTO, since we may not have yet hit the RSR 575 * watermark when we receive the RTO. 576 */ 577 for (i = 0, v = FIFO_RX_NDV; 578 (v & FIFO_RX_NDV) && !kror; i = 0) { 579 for (j = 0; 580 (v & FIFO_RX_NDV) && j < FIFO_RX_DEPTH; j++) { 581 v = cx25840_read4(c, CX25840_IR_FIFO_REG); 582 rx_data[i].hw_fifo_data = v & ~FIFO_RX_NDV; 583 i++; 584 } 585 if (i == 0) 586 break; 587 j = i * sizeof(union cx25840_ir_fifo_rec); 588 k = kfifo_in_locked(&ir_state->rx_kfifo, 589 (unsigned char *) rx_data, j, 590 &ir_state->rx_kfifo_lock); 591 if (k != j) 592 kror++; /* rx_kfifo over run */ 593 } 594 *handled = true; 595 } 596 597 events = 0; 598 v = 0; 599 if (kror) { 600 events |= V4L2_SUBDEV_IR_RX_SW_FIFO_OVERRUN; 601 v4l2_err(sd, "IR receiver software FIFO overrun\n"); 602 } 603 if (roe && ror) { 604 /* 605 * The RX FIFO Enable (CNTRL_RFE) must be toggled to clear 606 * the Rx FIFO Over Run status (STATS_ROR) 607 */ 608 v |= CNTRL_RFE; 609 events |= V4L2_SUBDEV_IR_RX_HW_FIFO_OVERRUN; 610 v4l2_err(sd, "IR receiver hardware FIFO overrun\n"); 611 } 612 if (rte && rto) { 613 /* 614 * The IR Receiver Enable (CNTRL_RXE) must be toggled to clear 615 * the Rx Pulse Width Timer Time Out (STATS_RTO) 616 */ 617 v |= CNTRL_RXE; 618 events |= V4L2_SUBDEV_IR_RX_END_OF_RX_DETECTED; 619 } 620 if (v) { 621 /* Clear STATS_ROR & STATS_RTO as needed by reseting hardware */ 622 cx25840_write4(c, CX25840_IR_CNTRL_REG, cntrl & ~v); 623 cx25840_write4(c, CX25840_IR_CNTRL_REG, cntrl); 624 *handled = true; 625 } 626 spin_lock_irqsave(&ir_state->rx_kfifo_lock, flags); 627 if (kfifo_len(&ir_state->rx_kfifo) >= CX25840_IR_RX_KFIFO_SIZE / 2) 628 events |= V4L2_SUBDEV_IR_RX_FIFO_SERVICE_REQ; 629 spin_unlock_irqrestore(&ir_state->rx_kfifo_lock, flags); 630 631 if (events) 632 v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_RX_NOTIFY, &events); 633 return 0; 634} 635 636/* Receiver */ 637static int cx25840_ir_rx_read(struct v4l2_subdev *sd, u8 *buf, size_t count, 638 ssize_t *num) 639{ 640 struct cx25840_ir_state *ir_state = to_ir_state(sd); 641 bool invert; 642 u16 divider; 643 unsigned int i, n; 644 union cx25840_ir_fifo_rec *p; 645 unsigned u, v; 646 647 if (ir_state == NULL) 648 return -ENODEV; 649 650 invert = (bool) atomic_read(&ir_state->rx_invert); 651 divider = (u16) atomic_read(&ir_state->rxclk_divider); 652 653 n = count / sizeof(union cx25840_ir_fifo_rec) 654 * sizeof(union cx25840_ir_fifo_rec); 655 if (n == 0) { 656 *num = 0; 657 return 0; 658 } 659 660 n = kfifo_out_locked(&ir_state->rx_kfifo, buf, n, 661 &ir_state->rx_kfifo_lock); 662 663 n /= sizeof(union cx25840_ir_fifo_rec); 664 *num = n * sizeof(union cx25840_ir_fifo_rec); 665 666 for (p = (union cx25840_ir_fifo_rec *) buf, i = 0; i < n; p++, i++) { 667 668 if ((p->hw_fifo_data & FIFO_RXTX_RTO) == FIFO_RXTX_RTO) { 669 /* Assume RTO was because of no IR light input */ 670 u = 0; 671 v4l2_dbg(2, ir_debug, sd, "rx read: end of rx\n"); 672 } else { 673 u = (p->hw_fifo_data & FIFO_RXTX_LVL) ? 1 : 0; 674 if (invert) 675 u = u ? 0 : 1; 676 } 677 678 v = (unsigned) pulse_width_count_to_ns( 679 (u16) (p->hw_fifo_data & FIFO_RXTX), divider); 680 if (v > IR_MAX_DURATION) 681 v = IR_MAX_DURATION; 682 683 p->ir_core_data.pulse = u; 684 p->ir_core_data.duration = v; 685 686 v4l2_dbg(2, ir_debug, sd, "rx read: %10u ns %s\n", 687 v, u ? "mark" : "space"); 688 } 689 return 0; 690} 691 692static int cx25840_ir_rx_g_parameters(struct v4l2_subdev *sd, 693 struct v4l2_subdev_ir_parameters *p) 694{ 695 struct cx25840_ir_state *ir_state = to_ir_state(sd); 696 697 if (ir_state == NULL) 698 return -ENODEV; 699 700 mutex_lock(&ir_state->rx_params_lock); 701 memcpy(p, &ir_state->rx_params, 702 sizeof(struct v4l2_subdev_ir_parameters)); 703 mutex_unlock(&ir_state->rx_params_lock); 704 return 0; 705} 706 707static int cx25840_ir_rx_shutdown(struct v4l2_subdev *sd) 708{ 709 struct cx25840_ir_state *ir_state = to_ir_state(sd); 710 struct i2c_client *c; 711 712 if (ir_state == NULL) 713 return -ENODEV; 714 715 c = ir_state->c; 716 mutex_lock(&ir_state->rx_params_lock); 717 718 /* Disable or slow down all IR Rx circuits and counters */ 719 irqenable_rx(sd, 0); 720 control_rx_enable(c, false); 721 control_rx_demodulation_enable(c, false); 722 control_rx_s_edge_detection(c, CNTRL_EDG_NONE); 723 filter_rx_s_min_width(c, 0); 724 cx25840_write4(c, CX25840_IR_RXCLK_REG, RXCLK_RCD); 725 726 ir_state->rx_params.shutdown = true; 727 728 mutex_unlock(&ir_state->rx_params_lock); 729 return 0; 730} 731 732static int cx25840_ir_rx_s_parameters(struct v4l2_subdev *sd, 733 struct v4l2_subdev_ir_parameters *p) 734{ 735 struct cx25840_ir_state *ir_state = to_ir_state(sd); 736 struct i2c_client *c; 737 struct v4l2_subdev_ir_parameters *o; 738 u16 rxclk_divider; 739 740 if (ir_state == NULL) 741 return -ENODEV; 742 743 if (p->shutdown) 744 return cx25840_ir_rx_shutdown(sd); 745 746 if (p->mode != V4L2_SUBDEV_IR_MODE_PULSE_WIDTH) 747 return -ENOSYS; 748 749 c = ir_state->c; 750 o = &ir_state->rx_params; 751 752 mutex_lock(&ir_state->rx_params_lock); 753 754 o->shutdown = p->shutdown; 755 756 p->mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH; 757 o->mode = p->mode; 758 759 p->bytes_per_data_element = sizeof(union cx25840_ir_fifo_rec); 760 o->bytes_per_data_element = p->bytes_per_data_element; 761 762 /* Before we tweak the hardware, we have to disable the receiver */ 763 irqenable_rx(sd, 0); 764 control_rx_enable(c, false); 765 766 control_rx_demodulation_enable(c, p->modulation); 767 o->modulation = p->modulation; 768 769 if (p->modulation) { 770 p->carrier_freq = rxclk_rx_s_carrier(c, p->carrier_freq, 771 &rxclk_divider); 772 773 o->carrier_freq = p->carrier_freq; 774 775 p->duty_cycle = 50; 776 o->duty_cycle = p->duty_cycle; 777 778 control_rx_s_carrier_window(c, p->carrier_freq, 779 &p->carrier_range_lower, 780 &p->carrier_range_upper); 781 o->carrier_range_lower = p->carrier_range_lower; 782 o->carrier_range_upper = p->carrier_range_upper; 783 784 p->max_pulse_width = 785 (u32) pulse_width_count_to_ns(FIFO_RXTX, rxclk_divider); 786 } else { 787 p->max_pulse_width = 788 rxclk_rx_s_max_pulse_width(c, p->max_pulse_width, 789 &rxclk_divider); 790 } 791 o->max_pulse_width = p->max_pulse_width; 792 atomic_set(&ir_state->rxclk_divider, rxclk_divider); 793 794 p->noise_filter_min_width = 795 filter_rx_s_min_width(c, p->noise_filter_min_width); 796 o->noise_filter_min_width = p->noise_filter_min_width; 797 798 p->resolution = clock_divider_to_resolution(rxclk_divider); 799 o->resolution = p->resolution; 800 801 control_rx_irq_watermark(c, RX_FIFO_HALF_FULL); 802 803 control_rx_s_edge_detection(c, CNTRL_EDG_BOTH); 804 805 o->invert_level = p->invert_level; 806 atomic_set(&ir_state->rx_invert, p->invert_level); 807 808 o->interrupt_enable = p->interrupt_enable; 809 o->enable = p->enable; 810 if (p->enable) { 811 unsigned long flags; 812 813 spin_lock_irqsave(&ir_state->rx_kfifo_lock, flags); 814 kfifo_reset(&ir_state->rx_kfifo); 815 spin_unlock_irqrestore(&ir_state->rx_kfifo_lock, flags); 816 if (p->interrupt_enable) 817 irqenable_rx(sd, IRQEN_RSE | IRQEN_RTE | IRQEN_ROE); 818 control_rx_enable(c, p->enable); 819 } 820 821 mutex_unlock(&ir_state->rx_params_lock); 822 return 0; 823} 824 825/* Transmitter */ 826static int cx25840_ir_tx_write(struct v4l2_subdev *sd, u8 *buf, size_t count, 827 ssize_t *num) 828{ 829 struct cx25840_ir_state *ir_state = to_ir_state(sd); 830 struct i2c_client *c; 831 832 if (ir_state == NULL) 833 return -ENODEV; 834 835 c = ir_state->c; 836 /* For now enable the Tx FIFO Service interrupt & pretend we did work */ 837 irqenable_tx(sd, IRQEN_TSE); 838 *num = count; 839 return 0; 840} 841 842static int cx25840_ir_tx_g_parameters(struct v4l2_subdev *sd, 843 struct v4l2_subdev_ir_parameters *p) 844{ 845 struct cx25840_ir_state *ir_state = to_ir_state(sd); 846 847 if (ir_state == NULL) 848 return -ENODEV; 849 850 mutex_lock(&ir_state->tx_params_lock); 851 memcpy(p, &ir_state->tx_params, 852 sizeof(struct v4l2_subdev_ir_parameters)); 853 mutex_unlock(&ir_state->tx_params_lock); 854 return 0; 855} 856 857static int cx25840_ir_tx_shutdown(struct v4l2_subdev *sd) 858{ 859 struct cx25840_ir_state *ir_state = to_ir_state(sd); 860 struct i2c_client *c; 861 862 if (ir_state == NULL) 863 return -ENODEV; 864 865 c = ir_state->c; 866 mutex_lock(&ir_state->tx_params_lock); 867 868 /* Disable or slow down all IR Tx circuits and counters */ 869 irqenable_tx(sd, 0); 870 control_tx_enable(c, false); 871 control_tx_modulation_enable(c, false); 872 cx25840_write4(c, CX25840_IR_TXCLK_REG, TXCLK_TCD); 873 874 ir_state->tx_params.shutdown = true; 875 876 mutex_unlock(&ir_state->tx_params_lock); 877 return 0; 878} 879 880static int cx25840_ir_tx_s_parameters(struct v4l2_subdev *sd, 881 struct v4l2_subdev_ir_parameters *p) 882{ 883 struct cx25840_ir_state *ir_state = to_ir_state(sd); 884 struct i2c_client *c; 885 struct v4l2_subdev_ir_parameters *o; 886 u16 txclk_divider; 887 888 if (ir_state == NULL) 889 return -ENODEV; 890 891 if (p->shutdown) 892 return cx25840_ir_tx_shutdown(sd); 893 894 if (p->mode != V4L2_SUBDEV_IR_MODE_PULSE_WIDTH) 895 return -ENOSYS; 896 897 c = ir_state->c; 898 o = &ir_state->tx_params; 899 mutex_lock(&ir_state->tx_params_lock); 900 901 o->shutdown = p->shutdown; 902 903 p->mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH; 904 o->mode = p->mode; 905 906 p->bytes_per_data_element = sizeof(union cx25840_ir_fifo_rec); 907 o->bytes_per_data_element = p->bytes_per_data_element; 908 909 /* Before we tweak the hardware, we have to disable the transmitter */ 910 irqenable_tx(sd, 0); 911 control_tx_enable(c, false); 912 913 control_tx_modulation_enable(c, p->modulation); 914 o->modulation = p->modulation; 915 916 if (p->modulation) { 917 p->carrier_freq = txclk_tx_s_carrier(c, p->carrier_freq, 918 &txclk_divider); 919 o->carrier_freq = p->carrier_freq; 920 921 p->duty_cycle = cduty_tx_s_duty_cycle(c, p->duty_cycle); 922 o->duty_cycle = p->duty_cycle; 923 924 p->max_pulse_width = 925 (u32) pulse_width_count_to_ns(FIFO_RXTX, txclk_divider); 926 } else { 927 p->max_pulse_width = 928 txclk_tx_s_max_pulse_width(c, p->max_pulse_width, 929 &txclk_divider); 930 } 931 o->max_pulse_width = p->max_pulse_width; 932 atomic_set(&ir_state->txclk_divider, txclk_divider); 933 934 p->resolution = clock_divider_to_resolution(txclk_divider); 935 o->resolution = p->resolution; 936 937 control_tx_irq_watermark(c, TX_FIFO_HALF_EMPTY); 938 939 control_tx_polarity_invert(c, p->invert_carrier_sense); 940 o->invert_carrier_sense = p->invert_carrier_sense; 941 942 o->invert_level = p->invert_level; 943 944 o->interrupt_enable = p->interrupt_enable; 945 o->enable = p->enable; 946 if (p->enable) { 947 /* reset tx_fifo here */ 948 if (p->interrupt_enable) 949 irqenable_tx(sd, IRQEN_TSE); 950 control_tx_enable(c, p->enable); 951 } 952 953 mutex_unlock(&ir_state->tx_params_lock); 954 return 0; 955} 956 957 958/* 959 * V4L2 Subdevice Core Ops support 960 */ 961int cx25840_ir_log_status(struct v4l2_subdev *sd) 962{ 963 struct cx25840_state *state = to_state(sd); 964 struct i2c_client *c = state->c; 965 char *s; 966 int i, j; 967 u32 cntrl, txclk, rxclk, cduty, stats, irqen, filtr; 968 969 /* The CX23888 chip doesn't have an IR controller on the A/V core */ 970 if (is_cx23888(state)) 971 return 0; 972 973 cntrl = cx25840_read4(c, CX25840_IR_CNTRL_REG); 974 txclk = cx25840_read4(c, CX25840_IR_TXCLK_REG) & TXCLK_TCD; 975 rxclk = cx25840_read4(c, CX25840_IR_RXCLK_REG) & RXCLK_RCD; 976 cduty = cx25840_read4(c, CX25840_IR_CDUTY_REG) & CDUTY_CDC; 977 stats = cx25840_read4(c, CX25840_IR_STATS_REG); 978 irqen = cx25840_read4(c, CX25840_IR_IRQEN_REG); 979 if (is_cx23885(state) || is_cx23887(state)) 980 irqen ^= IRQEN_MSK; 981 filtr = cx25840_read4(c, CX25840_IR_FILTR_REG) & FILTR_LPF; 982 983 v4l2_info(sd, "IR Receiver:\n"); 984 v4l2_info(sd, "\tEnabled: %s\n", 985 cntrl & CNTRL_RXE ? "yes" : "no"); 986 v4l2_info(sd, "\tDemodulation from a carrier: %s\n", 987 cntrl & CNTRL_DMD ? "enabled" : "disabled"); 988 v4l2_info(sd, "\tFIFO: %s\n", 989 cntrl & CNTRL_RFE ? "enabled" : "disabled"); 990 switch (cntrl & CNTRL_EDG) { 991 case CNTRL_EDG_NONE: 992 s = "disabled"; 993 break; 994 case CNTRL_EDG_FALL: 995 s = "falling edge"; 996 break; 997 case CNTRL_EDG_RISE: 998 s = "rising edge"; 999 break; 1000 case CNTRL_EDG_BOTH: 1001 s = "rising & falling edges"; 1002 break; 1003 default: 1004 s = "??? edge"; 1005 break; 1006 } 1007 v4l2_info(sd, "\tPulse timers' start/stop trigger: %s\n", s); 1008 v4l2_info(sd, "\tFIFO data on pulse timer overflow: %s\n", 1009 cntrl & CNTRL_R ? "not loaded" : "overflow marker"); 1010 v4l2_info(sd, "\tFIFO interrupt watermark: %s\n", 1011 cntrl & CNTRL_RIC ? "not empty" : "half full or greater"); 1012 v4l2_info(sd, "\tLoopback mode: %s\n", 1013 cntrl & CNTRL_LBM ? "loopback active" : "normal receive"); 1014 if (cntrl & CNTRL_DMD) { 1015 v4l2_info(sd, "\tExpected carrier (16 clocks): %u Hz\n", 1016 clock_divider_to_carrier_freq(rxclk)); 1017 switch (cntrl & CNTRL_WIN) { 1018 case CNTRL_WIN_3_3: 1019 i = 3; 1020 j = 3; 1021 break; 1022 case CNTRL_WIN_4_3: 1023 i = 4; 1024 j = 3; 1025 break; 1026 case CNTRL_WIN_3_4: 1027 i = 3; 1028 j = 4; 1029 break; 1030 case CNTRL_WIN_4_4: 1031 i = 4; 1032 j = 4; 1033 break; 1034 default: 1035 i = 0; 1036 j = 0; 1037 break; 1038 } 1039 v4l2_info(sd, "\tNext carrier edge window: 16 clocks " 1040 "-%1d/+%1d, %u to %u Hz\n", i, j, 1041 clock_divider_to_freq(rxclk, 16 + j), 1042 clock_divider_to_freq(rxclk, 16 - i)); 1043 } 1044 v4l2_info(sd, "\tMax measurable pulse width: %u us, %llu ns\n", 1045 pulse_width_count_to_us(FIFO_RXTX, rxclk), 1046 pulse_width_count_to_ns(FIFO_RXTX, rxclk)); 1047 v4l2_info(sd, "\tLow pass filter: %s\n", 1048 filtr ? "enabled" : "disabled"); 1049 if (filtr) 1050 v4l2_info(sd, "\tMin acceptable pulse width (LPF): %u us, " 1051 "%u ns\n", 1052 lpf_count_to_us(filtr), 1053 lpf_count_to_ns(filtr)); 1054 v4l2_info(sd, "\tPulse width timer timed-out: %s\n", 1055 stats & STATS_RTO ? "yes" : "no"); 1056 v4l2_info(sd, "\tPulse width timer time-out intr: %s\n", 1057 irqen & IRQEN_RTE ? "enabled" : "disabled"); 1058 v4l2_info(sd, "\tFIFO overrun: %s\n", 1059 stats & STATS_ROR ? "yes" : "no"); 1060 v4l2_info(sd, "\tFIFO overrun interrupt: %s\n", 1061 irqen & IRQEN_ROE ? "enabled" : "disabled"); 1062 v4l2_info(sd, "\tBusy: %s\n", 1063 stats & STATS_RBY ? "yes" : "no"); 1064 v4l2_info(sd, "\tFIFO service requested: %s\n", 1065 stats & STATS_RSR ? "yes" : "no"); 1066 v4l2_info(sd, "\tFIFO service request interrupt: %s\n", 1067 irqen & IRQEN_RSE ? "enabled" : "disabled"); 1068 1069 v4l2_info(sd, "IR Transmitter:\n"); 1070 v4l2_info(sd, "\tEnabled: %s\n", 1071 cntrl & CNTRL_TXE ? "yes" : "no"); 1072 v4l2_info(sd, "\tModulation onto a carrier: %s\n", 1073 cntrl & CNTRL_MOD ? "enabled" : "disabled"); 1074 v4l2_info(sd, "\tFIFO: %s\n", 1075 cntrl & CNTRL_TFE ? "enabled" : "disabled"); 1076 v4l2_info(sd, "\tFIFO interrupt watermark: %s\n", 1077 cntrl & CNTRL_TIC ? "not empty" : "half full or less"); 1078 v4l2_info(sd, "\tCarrier polarity: %s\n", 1079 cntrl & CNTRL_CPL ? "space:burst mark:noburst" 1080 : "space:noburst mark:burst"); 1081 if (cntrl & CNTRL_MOD) { 1082 v4l2_info(sd, "\tCarrier (16 clocks): %u Hz\n", 1083 clock_divider_to_carrier_freq(txclk)); 1084 v4l2_info(sd, "\tCarrier duty cycle: %2u/16\n", 1085 cduty + 1); 1086 } 1087 v4l2_info(sd, "\tMax pulse width: %u us, %llu ns\n", 1088 pulse_width_count_to_us(FIFO_RXTX, txclk), 1089 pulse_width_count_to_ns(FIFO_RXTX, txclk)); 1090 v4l2_info(sd, "\tBusy: %s\n", 1091 stats & STATS_TBY ? "yes" : "no"); 1092 v4l2_info(sd, "\tFIFO service requested: %s\n", 1093 stats & STATS_TSR ? "yes" : "no"); 1094 v4l2_info(sd, "\tFIFO service request interrupt: %s\n", 1095 irqen & IRQEN_TSE ? "enabled" : "disabled"); 1096 1097 return 0; 1098} 1099 1100 1101const struct v4l2_subdev_ir_ops cx25840_ir_ops = { 1102 .rx_read = cx25840_ir_rx_read, 1103 .rx_g_parameters = cx25840_ir_rx_g_parameters, 1104 .rx_s_parameters = cx25840_ir_rx_s_parameters, 1105 1106 .tx_write = cx25840_ir_tx_write, 1107 .tx_g_parameters = cx25840_ir_tx_g_parameters, 1108 .tx_s_parameters = cx25840_ir_tx_s_parameters, 1109}; 1110 1111 1112static const struct v4l2_subdev_ir_parameters default_rx_params = { 1113 .bytes_per_data_element = sizeof(union cx25840_ir_fifo_rec), 1114 .mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH, 1115 1116 .enable = false, 1117 .interrupt_enable = false, 1118 .shutdown = true, 1119 1120 .modulation = true, 1121 .carrier_freq = 36000, /* 36 kHz - RC-5, and RC-6 carrier */ 1122 1123 /* RC-5: 666,667 ns = 1/36 kHz * 32 cycles * 1 mark * 0.75 */ 1124 /* RC-6: 333,333 ns = 1/36 kHz * 16 cycles * 1 mark * 0.75 */ 1125 .noise_filter_min_width = 333333, /* ns */ 1126 .carrier_range_lower = 35000, 1127 .carrier_range_upper = 37000, 1128 .invert_level = false, 1129}; 1130 1131static const struct v4l2_subdev_ir_parameters default_tx_params = { 1132 .bytes_per_data_element = sizeof(union cx25840_ir_fifo_rec), 1133 .mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH, 1134 1135 .enable = false, 1136 .interrupt_enable = false, 1137 .shutdown = true, 1138 1139 .modulation = true, 1140 .carrier_freq = 36000, /* 36 kHz - RC-5 carrier */ 1141 .duty_cycle = 25, /* 25 % - RC-5 carrier */ 1142 .invert_level = false, 1143 .invert_carrier_sense = false, 1144}; 1145 1146int cx25840_ir_probe(struct v4l2_subdev *sd) 1147{ 1148 struct cx25840_state *state = to_state(sd); 1149 struct cx25840_ir_state *ir_state; 1150 struct v4l2_subdev_ir_parameters default_params; 1151 1152 /* Only init the IR controller for the CX2388[57] AV Core for now */ 1153 if (!(is_cx23885(state) || is_cx23887(state))) 1154 return 0; 1155 1156 ir_state = kzalloc(sizeof(struct cx25840_ir_state), GFP_KERNEL); 1157 if (ir_state == NULL) 1158 return -ENOMEM; 1159 1160 spin_lock_init(&ir_state->rx_kfifo_lock); 1161 if (kfifo_alloc(&ir_state->rx_kfifo, 1162 CX25840_IR_RX_KFIFO_SIZE, GFP_KERNEL)) { 1163 kfree(ir_state); 1164 return -ENOMEM; 1165 } 1166 1167 ir_state->c = state->c; 1168 state->ir_state = ir_state; 1169 1170 /* Ensure no interrupts arrive yet */ 1171 if (is_cx23885(state) || is_cx23887(state)) 1172 cx25840_write4(ir_state->c, CX25840_IR_IRQEN_REG, IRQEN_MSK); 1173 else 1174 cx25840_write4(ir_state->c, CX25840_IR_IRQEN_REG, 0); 1175 1176 mutex_init(&ir_state->rx_params_lock); 1177 memcpy(&default_params, &default_rx_params, 1178 sizeof(struct v4l2_subdev_ir_parameters)); 1179 v4l2_subdev_call(sd, ir, rx_s_parameters, &default_params); 1180 1181 mutex_init(&ir_state->tx_params_lock); 1182 memcpy(&default_params, &default_tx_params, 1183 sizeof(struct v4l2_subdev_ir_parameters)); 1184 v4l2_subdev_call(sd, ir, tx_s_parameters, &default_params); 1185 1186 return 0; 1187} 1188 1189int cx25840_ir_remove(struct v4l2_subdev *sd) 1190{ 1191 struct cx25840_state *state = to_state(sd); 1192 struct cx25840_ir_state *ir_state = to_ir_state(sd); 1193 1194 if (ir_state == NULL) 1195 return -ENODEV; 1196 1197 cx25840_ir_rx_shutdown(sd); 1198 cx25840_ir_tx_shutdown(sd); 1199 1200 kfifo_free(&ir_state->rx_kfifo); 1201 kfree(ir_state); 1202 state->ir_state = NULL; 1203 return 0; 1204} 1205