1/* 2 * Support for LG Electronics LGDT3304 and LGDT3305 - VSB/QAM 3 * 4 * Copyright (C) 2008, 2009, 2010 Michael Krufky <mkrufky@linuxtv.org> 5 * 6 * LGDT3304 support by Jarod Wilson <jarod@redhat.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 * 22 */ 23 24#include <asm/div64.h> 25#include <linux/dvb/frontend.h> 26#include <linux/slab.h> 27#include "dvb_math.h" 28#include "lgdt3305.h" 29 30static int debug; 31module_param(debug, int, 0644); 32MODULE_PARM_DESC(debug, "set debug level (info=1, reg=2 (or-able))"); 33 34#define DBG_INFO 1 35#define DBG_REG 2 36 37#define lg_printk(kern, fmt, arg...) \ 38 printk(kern "%s: " fmt, __func__, ##arg) 39 40#define lg_info(fmt, arg...) printk(KERN_INFO "lgdt3305: " fmt, ##arg) 41#define lg_warn(fmt, arg...) lg_printk(KERN_WARNING, fmt, ##arg) 42#define lg_err(fmt, arg...) lg_printk(KERN_ERR, fmt, ##arg) 43#define lg_dbg(fmt, arg...) if (debug & DBG_INFO) \ 44 lg_printk(KERN_DEBUG, fmt, ##arg) 45#define lg_reg(fmt, arg...) if (debug & DBG_REG) \ 46 lg_printk(KERN_DEBUG, fmt, ##arg) 47 48#define lg_fail(ret) \ 49({ \ 50 int __ret; \ 51 __ret = (ret < 0); \ 52 if (__ret) \ 53 lg_err("error %d on line %d\n", ret, __LINE__); \ 54 __ret; \ 55}) 56 57struct lgdt3305_state { 58 struct i2c_adapter *i2c_adap; 59 const struct lgdt3305_config *cfg; 60 61 struct dvb_frontend frontend; 62 63 fe_modulation_t current_modulation; 64 u32 current_frequency; 65 u32 snr; 66}; 67 68/* ------------------------------------------------------------------------ */ 69 70 71#define LGDT3305_GEN_CTRL_1 0x0000 72#define LGDT3305_GEN_CTRL_2 0x0001 73#define LGDT3305_GEN_CTRL_3 0x0002 74#define LGDT3305_GEN_STATUS 0x0003 75#define LGDT3305_GEN_CONTROL 0x0007 76#define LGDT3305_GEN_CTRL_4 0x000a 77#define LGDT3305_DGTL_AGC_REF_1 0x0012 78#define LGDT3305_DGTL_AGC_REF_2 0x0013 79#define LGDT3305_CR_CTR_FREQ_1 0x0106 80#define LGDT3305_CR_CTR_FREQ_2 0x0107 81#define LGDT3305_CR_CTR_FREQ_3 0x0108 82#define LGDT3305_CR_CTR_FREQ_4 0x0109 83#define LGDT3305_CR_MSE_1 0x011b 84#define LGDT3305_CR_MSE_2 0x011c 85#define LGDT3305_CR_LOCK_STATUS 0x011d 86#define LGDT3305_CR_CTRL_7 0x0126 87#define LGDT3305_AGC_POWER_REF_1 0x0300 88#define LGDT3305_AGC_POWER_REF_2 0x0301 89#define LGDT3305_AGC_DELAY_PT_1 0x0302 90#define LGDT3305_AGC_DELAY_PT_2 0x0303 91#define LGDT3305_RFAGC_LOOP_FLTR_BW_1 0x0306 92#define LGDT3305_RFAGC_LOOP_FLTR_BW_2 0x0307 93#define LGDT3305_IFBW_1 0x0308 94#define LGDT3305_IFBW_2 0x0309 95#define LGDT3305_AGC_CTRL_1 0x030c 96#define LGDT3305_AGC_CTRL_4 0x0314 97#define LGDT3305_EQ_MSE_1 0x0413 98#define LGDT3305_EQ_MSE_2 0x0414 99#define LGDT3305_EQ_MSE_3 0x0415 100#define LGDT3305_PT_MSE_1 0x0417 101#define LGDT3305_PT_MSE_2 0x0418 102#define LGDT3305_PT_MSE_3 0x0419 103#define LGDT3305_FEC_BLOCK_CTRL 0x0504 104#define LGDT3305_FEC_LOCK_STATUS 0x050a 105#define LGDT3305_FEC_PKT_ERR_1 0x050c 106#define LGDT3305_FEC_PKT_ERR_2 0x050d 107#define LGDT3305_TP_CTRL_1 0x050e 108#define LGDT3305_BERT_PERIOD 0x0801 109#define LGDT3305_BERT_ERROR_COUNT_1 0x080a 110#define LGDT3305_BERT_ERROR_COUNT_2 0x080b 111#define LGDT3305_BERT_ERROR_COUNT_3 0x080c 112#define LGDT3305_BERT_ERROR_COUNT_4 0x080d 113 114static int lgdt3305_write_reg(struct lgdt3305_state *state, u16 reg, u8 val) 115{ 116 int ret; 117 u8 buf[] = { reg >> 8, reg & 0xff, val }; 118 struct i2c_msg msg = { 119 .addr = state->cfg->i2c_addr, .flags = 0, 120 .buf = buf, .len = 3, 121 }; 122 123 lg_reg("reg: 0x%04x, val: 0x%02x\n", reg, val); 124 125 ret = i2c_transfer(state->i2c_adap, &msg, 1); 126 127 if (ret != 1) { 128 lg_err("error (addr %02x %02x <- %02x, err = %i)\n", 129 msg.buf[0], msg.buf[1], msg.buf[2], ret); 130 if (ret < 0) 131 return ret; 132 else 133 return -EREMOTEIO; 134 } 135 return 0; 136} 137 138static int lgdt3305_read_reg(struct lgdt3305_state *state, u16 reg, u8 *val) 139{ 140 int ret; 141 u8 reg_buf[] = { reg >> 8, reg & 0xff }; 142 struct i2c_msg msg[] = { 143 { .addr = state->cfg->i2c_addr, 144 .flags = 0, .buf = reg_buf, .len = 2 }, 145 { .addr = state->cfg->i2c_addr, 146 .flags = I2C_M_RD, .buf = val, .len = 1 }, 147 }; 148 149 lg_reg("reg: 0x%04x\n", reg); 150 151 ret = i2c_transfer(state->i2c_adap, msg, 2); 152 153 if (ret != 2) { 154 lg_err("error (addr %02x reg %04x error (ret == %i)\n", 155 state->cfg->i2c_addr, reg, ret); 156 if (ret < 0) 157 return ret; 158 else 159 return -EREMOTEIO; 160 } 161 return 0; 162} 163 164#define read_reg(state, reg) \ 165({ \ 166 u8 __val; \ 167 int ret = lgdt3305_read_reg(state, reg, &__val); \ 168 if (lg_fail(ret)) \ 169 __val = 0; \ 170 __val; \ 171}) 172 173static int lgdt3305_set_reg_bit(struct lgdt3305_state *state, 174 u16 reg, int bit, int onoff) 175{ 176 u8 val; 177 int ret; 178 179 lg_reg("reg: 0x%04x, bit: %d, level: %d\n", reg, bit, onoff); 180 181 ret = lgdt3305_read_reg(state, reg, &val); 182 if (lg_fail(ret)) 183 goto fail; 184 185 val &= ~(1 << bit); 186 val |= (onoff & 1) << bit; 187 188 ret = lgdt3305_write_reg(state, reg, val); 189fail: 190 return ret; 191} 192 193struct lgdt3305_reg { 194 u16 reg; 195 u8 val; 196}; 197 198static int lgdt3305_write_regs(struct lgdt3305_state *state, 199 struct lgdt3305_reg *regs, int len) 200{ 201 int i, ret; 202 203 lg_reg("writing %d registers...\n", len); 204 205 for (i = 0; i < len - 1; i++) { 206 ret = lgdt3305_write_reg(state, regs[i].reg, regs[i].val); 207 if (lg_fail(ret)) 208 return ret; 209 } 210 return 0; 211} 212 213/* ------------------------------------------------------------------------ */ 214 215static int lgdt3305_soft_reset(struct lgdt3305_state *state) 216{ 217 int ret; 218 219 lg_dbg("\n"); 220 221 ret = lgdt3305_set_reg_bit(state, LGDT3305_GEN_CTRL_3, 0, 0); 222 if (lg_fail(ret)) 223 goto fail; 224 225 msleep(20); 226 ret = lgdt3305_set_reg_bit(state, LGDT3305_GEN_CTRL_3, 0, 1); 227fail: 228 return ret; 229} 230 231static inline int lgdt3305_mpeg_mode(struct lgdt3305_state *state, 232 enum lgdt3305_mpeg_mode mode) 233{ 234 lg_dbg("(%d)\n", mode); 235 return lgdt3305_set_reg_bit(state, LGDT3305_TP_CTRL_1, 5, mode); 236} 237 238static int lgdt3305_mpeg_mode_polarity(struct lgdt3305_state *state, 239 enum lgdt3305_tp_clock_edge edge, 240 enum lgdt3305_tp_valid_polarity valid) 241{ 242 u8 val; 243 int ret; 244 245 lg_dbg("edge = %d, valid = %d\n", edge, valid); 246 247 ret = lgdt3305_read_reg(state, LGDT3305_TP_CTRL_1, &val); 248 if (lg_fail(ret)) 249 goto fail; 250 251 val &= ~0x09; 252 253 if (edge) 254 val |= 0x08; 255 if (valid) 256 val |= 0x01; 257 258 ret = lgdt3305_write_reg(state, LGDT3305_TP_CTRL_1, val); 259 if (lg_fail(ret)) 260 goto fail; 261 262 ret = lgdt3305_soft_reset(state); 263fail: 264 return ret; 265} 266 267static int lgdt3305_set_modulation(struct lgdt3305_state *state, 268 struct dvb_frontend_parameters *param) 269{ 270 u8 opermode; 271 int ret; 272 273 lg_dbg("\n"); 274 275 ret = lgdt3305_read_reg(state, LGDT3305_GEN_CTRL_1, &opermode); 276 if (lg_fail(ret)) 277 goto fail; 278 279 opermode &= ~0x03; 280 281 switch (param->u.vsb.modulation) { 282 case VSB_8: 283 opermode |= 0x03; 284 break; 285 case QAM_64: 286 opermode |= 0x00; 287 break; 288 case QAM_256: 289 opermode |= 0x01; 290 break; 291 default: 292 return -EINVAL; 293 } 294 ret = lgdt3305_write_reg(state, LGDT3305_GEN_CTRL_1, opermode); 295fail: 296 return ret; 297} 298 299static int lgdt3305_set_filter_extension(struct lgdt3305_state *state, 300 struct dvb_frontend_parameters *param) 301{ 302 int val; 303 304 switch (param->u.vsb.modulation) { 305 case VSB_8: 306 val = 0; 307 break; 308 case QAM_64: 309 case QAM_256: 310 val = 1; 311 break; 312 default: 313 return -EINVAL; 314 } 315 lg_dbg("val = %d\n", val); 316 317 return lgdt3305_set_reg_bit(state, 0x043f, 2, val); 318} 319 320/* ------------------------------------------------------------------------ */ 321 322static int lgdt3305_passband_digital_agc(struct lgdt3305_state *state, 323 struct dvb_frontend_parameters *param) 324{ 325 u16 agc_ref; 326 327 switch (param->u.vsb.modulation) { 328 case VSB_8: 329 agc_ref = 0x32c4; 330 break; 331 case QAM_64: 332 agc_ref = 0x2a00; 333 break; 334 case QAM_256: 335 agc_ref = 0x2a80; 336 break; 337 default: 338 return -EINVAL; 339 } 340 341 lg_dbg("agc ref: 0x%04x\n", agc_ref); 342 343 lgdt3305_write_reg(state, LGDT3305_DGTL_AGC_REF_1, agc_ref >> 8); 344 lgdt3305_write_reg(state, LGDT3305_DGTL_AGC_REF_2, agc_ref & 0xff); 345 346 return 0; 347} 348 349static int lgdt3305_rfagc_loop(struct lgdt3305_state *state, 350 struct dvb_frontend_parameters *param) 351{ 352 u16 ifbw, rfbw, agcdelay; 353 354 switch (param->u.vsb.modulation) { 355 case VSB_8: 356 agcdelay = 0x04c0; 357 rfbw = 0x8000; 358 ifbw = 0x8000; 359 break; 360 case QAM_64: 361 case QAM_256: 362 agcdelay = 0x046b; 363 rfbw = 0x8889; 364 if (state->cfg->demod_chip == LGDT3304) 365 ifbw = 0x6666; 366 else /* (state->cfg->demod_chip == LGDT3305) */ 367 ifbw = 0x8888; 368 break; 369 default: 370 return -EINVAL; 371 } 372 373 if (state->cfg->rf_agc_loop) { 374 lg_dbg("agcdelay: 0x%04x, rfbw: 0x%04x\n", agcdelay, rfbw); 375 376 /* rf agc loop filter bandwidth */ 377 lgdt3305_write_reg(state, LGDT3305_AGC_DELAY_PT_1, 378 agcdelay >> 8); 379 lgdt3305_write_reg(state, LGDT3305_AGC_DELAY_PT_2, 380 agcdelay & 0xff); 381 382 lgdt3305_write_reg(state, LGDT3305_RFAGC_LOOP_FLTR_BW_1, 383 rfbw >> 8); 384 lgdt3305_write_reg(state, LGDT3305_RFAGC_LOOP_FLTR_BW_2, 385 rfbw & 0xff); 386 } else { 387 lg_dbg("ifbw: 0x%04x\n", ifbw); 388 389 /* if agc loop filter bandwidth */ 390 lgdt3305_write_reg(state, LGDT3305_IFBW_1, ifbw >> 8); 391 lgdt3305_write_reg(state, LGDT3305_IFBW_2, ifbw & 0xff); 392 } 393 394 return 0; 395} 396 397static int lgdt3305_agc_setup(struct lgdt3305_state *state, 398 struct dvb_frontend_parameters *param) 399{ 400 int lockdten, acqen; 401 402 switch (param->u.vsb.modulation) { 403 case VSB_8: 404 lockdten = 0; 405 acqen = 0; 406 break; 407 case QAM_64: 408 case QAM_256: 409 lockdten = 1; 410 acqen = 1; 411 break; 412 default: 413 return -EINVAL; 414 } 415 416 lg_dbg("lockdten = %d, acqen = %d\n", lockdten, acqen); 417 418 /* control agc function */ 419 switch (state->cfg->demod_chip) { 420 case LGDT3304: 421 lgdt3305_write_reg(state, 0x0314, 0xe1 | lockdten << 1); 422 lgdt3305_set_reg_bit(state, 0x030e, 2, acqen); 423 break; 424 case LGDT3305: 425 lgdt3305_write_reg(state, LGDT3305_AGC_CTRL_4, 0xe1 | lockdten << 1); 426 lgdt3305_set_reg_bit(state, LGDT3305_AGC_CTRL_1, 2, acqen); 427 break; 428 default: 429 return -EINVAL; 430 } 431 432 return lgdt3305_rfagc_loop(state, param); 433} 434 435static int lgdt3305_set_agc_power_ref(struct lgdt3305_state *state, 436 struct dvb_frontend_parameters *param) 437{ 438 u16 usref = 0; 439 440 switch (param->u.vsb.modulation) { 441 case VSB_8: 442 if (state->cfg->usref_8vsb) 443 usref = state->cfg->usref_8vsb; 444 break; 445 case QAM_64: 446 if (state->cfg->usref_qam64) 447 usref = state->cfg->usref_qam64; 448 break; 449 case QAM_256: 450 if (state->cfg->usref_qam256) 451 usref = state->cfg->usref_qam256; 452 break; 453 default: 454 return -EINVAL; 455 } 456 457 if (usref) { 458 lg_dbg("set manual mode: 0x%04x\n", usref); 459 460 lgdt3305_set_reg_bit(state, LGDT3305_AGC_CTRL_1, 3, 1); 461 462 lgdt3305_write_reg(state, LGDT3305_AGC_POWER_REF_1, 463 0xff & (usref >> 8)); 464 lgdt3305_write_reg(state, LGDT3305_AGC_POWER_REF_2, 465 0xff & (usref >> 0)); 466 } 467 return 0; 468} 469 470/* ------------------------------------------------------------------------ */ 471 472static int lgdt3305_spectral_inversion(struct lgdt3305_state *state, 473 struct dvb_frontend_parameters *param, 474 int inversion) 475{ 476 int ret; 477 478 lg_dbg("(%d)\n", inversion); 479 480 switch (param->u.vsb.modulation) { 481 case VSB_8: 482 ret = lgdt3305_write_reg(state, LGDT3305_CR_CTRL_7, 483 inversion ? 0xf9 : 0x79); 484 break; 485 case QAM_64: 486 case QAM_256: 487 ret = lgdt3305_write_reg(state, LGDT3305_FEC_BLOCK_CTRL, 488 inversion ? 0xfd : 0xff); 489 break; 490 default: 491 ret = -EINVAL; 492 } 493 return ret; 494} 495 496static int lgdt3305_set_if(struct lgdt3305_state *state, 497 struct dvb_frontend_parameters *param) 498{ 499 u16 if_freq_khz; 500 u8 nco1, nco2, nco3, nco4; 501 u64 nco; 502 503 switch (param->u.vsb.modulation) { 504 case VSB_8: 505 if_freq_khz = state->cfg->vsb_if_khz; 506 break; 507 case QAM_64: 508 case QAM_256: 509 if_freq_khz = state->cfg->qam_if_khz; 510 break; 511 default: 512 return -EINVAL; 513 } 514 515 nco = if_freq_khz / 10; 516 517 switch (param->u.vsb.modulation) { 518 case VSB_8: 519 nco <<= 24; 520 do_div(nco, 625); 521 break; 522 case QAM_64: 523 case QAM_256: 524 nco <<= 28; 525 do_div(nco, 625); 526 break; 527 default: 528 return -EINVAL; 529 } 530 531 nco1 = (nco >> 24) & 0x3f; 532 nco1 |= 0x40; 533 nco2 = (nco >> 16) & 0xff; 534 nco3 = (nco >> 8) & 0xff; 535 nco4 = nco & 0xff; 536 537 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_1, nco1); 538 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_2, nco2); 539 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_3, nco3); 540 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_4, nco4); 541 542 lg_dbg("%d KHz -> [%02x%02x%02x%02x]\n", 543 if_freq_khz, nco1, nco2, nco3, nco4); 544 545 return 0; 546} 547 548/* ------------------------------------------------------------------------ */ 549 550static int lgdt3305_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) 551{ 552 struct lgdt3305_state *state = fe->demodulator_priv; 553 554 if (state->cfg->deny_i2c_rptr) 555 return 0; 556 557 lg_dbg("(%d)\n", enable); 558 559 return lgdt3305_set_reg_bit(state, LGDT3305_GEN_CTRL_2, 5, 560 enable ? 0 : 1); 561} 562 563static int lgdt3305_sleep(struct dvb_frontend *fe) 564{ 565 struct lgdt3305_state *state = fe->demodulator_priv; 566 u8 gen_ctrl_3, gen_ctrl_4; 567 568 lg_dbg("\n"); 569 570 gen_ctrl_3 = read_reg(state, LGDT3305_GEN_CTRL_3); 571 gen_ctrl_4 = read_reg(state, LGDT3305_GEN_CTRL_4); 572 573 /* hold in software reset while sleeping */ 574 gen_ctrl_3 &= ~0x01; 575 /* tristate the IF-AGC pin */ 576 gen_ctrl_3 |= 0x02; 577 /* tristate the RF-AGC pin */ 578 gen_ctrl_3 |= 0x04; 579 580 /* disable vsb/qam module */ 581 gen_ctrl_4 &= ~0x01; 582 /* disable adc module */ 583 gen_ctrl_4 &= ~0x02; 584 585 lgdt3305_write_reg(state, LGDT3305_GEN_CTRL_3, gen_ctrl_3); 586 lgdt3305_write_reg(state, LGDT3305_GEN_CTRL_4, gen_ctrl_4); 587 588 return 0; 589} 590 591static int lgdt3305_init(struct dvb_frontend *fe) 592{ 593 struct lgdt3305_state *state = fe->demodulator_priv; 594 int ret; 595 596 static struct lgdt3305_reg lgdt3304_init_data[] = { 597 { .reg = LGDT3305_GEN_CTRL_1, .val = 0x03, }, 598 { .reg = 0x000d, .val = 0x02, }, 599 { .reg = 0x000e, .val = 0x02, }, 600 { .reg = LGDT3305_DGTL_AGC_REF_1, .val = 0x32, }, 601 { .reg = LGDT3305_DGTL_AGC_REF_2, .val = 0xc4, }, 602 { .reg = LGDT3305_CR_CTR_FREQ_1, .val = 0x00, }, 603 { .reg = LGDT3305_CR_CTR_FREQ_2, .val = 0x00, }, 604 { .reg = LGDT3305_CR_CTR_FREQ_3, .val = 0x00, }, 605 { .reg = LGDT3305_CR_CTR_FREQ_4, .val = 0x00, }, 606 { .reg = LGDT3305_CR_CTRL_7, .val = 0xf9, }, 607 { .reg = 0x0112, .val = 0x17, }, 608 { .reg = 0x0113, .val = 0x15, }, 609 { .reg = 0x0114, .val = 0x18, }, 610 { .reg = 0x0115, .val = 0xff, }, 611 { .reg = 0x0116, .val = 0x3c, }, 612 { .reg = 0x0214, .val = 0x67, }, 613 { .reg = 0x0424, .val = 0x8d, }, 614 { .reg = 0x0427, .val = 0x12, }, 615 { .reg = 0x0428, .val = 0x4f, }, 616 { .reg = LGDT3305_IFBW_1, .val = 0x80, }, 617 { .reg = LGDT3305_IFBW_2, .val = 0x00, }, 618 { .reg = 0x030a, .val = 0x08, }, 619 { .reg = 0x030b, .val = 0x9b, }, 620 { .reg = 0x030d, .val = 0x00, }, 621 { .reg = 0x030e, .val = 0x1c, }, 622 { .reg = 0x0314, .val = 0xe1, }, 623 { .reg = 0x000d, .val = 0x82, }, 624 { .reg = LGDT3305_TP_CTRL_1, .val = 0x5b, }, 625 { .reg = LGDT3305_TP_CTRL_1, .val = 0x5b, }, 626 }; 627 628 static struct lgdt3305_reg lgdt3305_init_data[] = { 629 { .reg = LGDT3305_GEN_CTRL_1, .val = 0x03, }, 630 { .reg = LGDT3305_GEN_CTRL_2, .val = 0xb0, }, 631 { .reg = LGDT3305_GEN_CTRL_3, .val = 0x01, }, 632 { .reg = LGDT3305_GEN_CONTROL, .val = 0x6f, }, 633 { .reg = LGDT3305_GEN_CTRL_4, .val = 0x03, }, 634 { .reg = LGDT3305_DGTL_AGC_REF_1, .val = 0x32, }, 635 { .reg = LGDT3305_DGTL_AGC_REF_2, .val = 0xc4, }, 636 { .reg = LGDT3305_CR_CTR_FREQ_1, .val = 0x00, }, 637 { .reg = LGDT3305_CR_CTR_FREQ_2, .val = 0x00, }, 638 { .reg = LGDT3305_CR_CTR_FREQ_3, .val = 0x00, }, 639 { .reg = LGDT3305_CR_CTR_FREQ_4, .val = 0x00, }, 640 { .reg = LGDT3305_CR_CTRL_7, .val = 0x79, }, 641 { .reg = LGDT3305_AGC_POWER_REF_1, .val = 0x32, }, 642 { .reg = LGDT3305_AGC_POWER_REF_2, .val = 0xc4, }, 643 { .reg = LGDT3305_AGC_DELAY_PT_1, .val = 0x0d, }, 644 { .reg = LGDT3305_AGC_DELAY_PT_2, .val = 0x30, }, 645 { .reg = LGDT3305_RFAGC_LOOP_FLTR_BW_1, .val = 0x80, }, 646 { .reg = LGDT3305_RFAGC_LOOP_FLTR_BW_2, .val = 0x00, }, 647 { .reg = LGDT3305_IFBW_1, .val = 0x80, }, 648 { .reg = LGDT3305_IFBW_2, .val = 0x00, }, 649 { .reg = LGDT3305_AGC_CTRL_1, .val = 0x30, }, 650 { .reg = LGDT3305_AGC_CTRL_4, .val = 0x61, }, 651 { .reg = LGDT3305_FEC_BLOCK_CTRL, .val = 0xff, }, 652 { .reg = LGDT3305_TP_CTRL_1, .val = 0x1b, }, 653 }; 654 655 lg_dbg("\n"); 656 657 switch (state->cfg->demod_chip) { 658 case LGDT3304: 659 ret = lgdt3305_write_regs(state, lgdt3304_init_data, 660 ARRAY_SIZE(lgdt3304_init_data)); 661 break; 662 case LGDT3305: 663 ret = lgdt3305_write_regs(state, lgdt3305_init_data, 664 ARRAY_SIZE(lgdt3305_init_data)); 665 break; 666 default: 667 ret = -EINVAL; 668 } 669 if (lg_fail(ret)) 670 goto fail; 671 672 ret = lgdt3305_soft_reset(state); 673fail: 674 return ret; 675} 676 677static int lgdt3304_set_parameters(struct dvb_frontend *fe, 678 struct dvb_frontend_parameters *param) 679{ 680 struct lgdt3305_state *state = fe->demodulator_priv; 681 int ret; 682 683 lg_dbg("(%d, %d)\n", param->frequency, param->u.vsb.modulation); 684 685 if (fe->ops.tuner_ops.set_params) { 686 ret = fe->ops.tuner_ops.set_params(fe, param); 687 if (fe->ops.i2c_gate_ctrl) 688 fe->ops.i2c_gate_ctrl(fe, 0); 689 if (lg_fail(ret)) 690 goto fail; 691 state->current_frequency = param->frequency; 692 } 693 694 ret = lgdt3305_set_modulation(state, param); 695 if (lg_fail(ret)) 696 goto fail; 697 698 ret = lgdt3305_passband_digital_agc(state, param); 699 if (lg_fail(ret)) 700 goto fail; 701 702 ret = lgdt3305_agc_setup(state, param); 703 if (lg_fail(ret)) 704 goto fail; 705 706 /* reg 0x030d is 3304-only... seen in vsb and qam usbsnoops... */ 707 switch (param->u.vsb.modulation) { 708 case VSB_8: 709 lgdt3305_write_reg(state, 0x030d, 0x00); 710 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_1, 0x4f); 711 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_2, 0x0c); 712 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_3, 0xac); 713 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_4, 0xba); 714 break; 715 case QAM_64: 716 case QAM_256: 717 lgdt3305_write_reg(state, 0x030d, 0x14); 718 ret = lgdt3305_set_if(state, param); 719 if (lg_fail(ret)) 720 goto fail; 721 break; 722 default: 723 return -EINVAL; 724 } 725 726 727 ret = lgdt3305_spectral_inversion(state, param, 728 state->cfg->spectral_inversion 729 ? 1 : 0); 730 if (lg_fail(ret)) 731 goto fail; 732 733 state->current_modulation = param->u.vsb.modulation; 734 735 ret = lgdt3305_mpeg_mode(state, state->cfg->mpeg_mode); 736 if (lg_fail(ret)) 737 goto fail; 738 739 /* lgdt3305_mpeg_mode_polarity calls lgdt3305_soft_reset */ 740 ret = lgdt3305_mpeg_mode_polarity(state, 741 state->cfg->tpclk_edge, 742 state->cfg->tpvalid_polarity); 743fail: 744 return ret; 745} 746 747static int lgdt3305_set_parameters(struct dvb_frontend *fe, 748 struct dvb_frontend_parameters *param) 749{ 750 struct lgdt3305_state *state = fe->demodulator_priv; 751 int ret; 752 753 lg_dbg("(%d, %d)\n", param->frequency, param->u.vsb.modulation); 754 755 if (fe->ops.tuner_ops.set_params) { 756 ret = fe->ops.tuner_ops.set_params(fe, param); 757 if (fe->ops.i2c_gate_ctrl) 758 fe->ops.i2c_gate_ctrl(fe, 0); 759 if (lg_fail(ret)) 760 goto fail; 761 state->current_frequency = param->frequency; 762 } 763 764 ret = lgdt3305_set_modulation(state, param); 765 if (lg_fail(ret)) 766 goto fail; 767 768 ret = lgdt3305_passband_digital_agc(state, param); 769 if (lg_fail(ret)) 770 goto fail; 771 ret = lgdt3305_set_agc_power_ref(state, param); 772 if (lg_fail(ret)) 773 goto fail; 774 ret = lgdt3305_agc_setup(state, param); 775 if (lg_fail(ret)) 776 goto fail; 777 778 /* low if */ 779 ret = lgdt3305_write_reg(state, LGDT3305_GEN_CONTROL, 0x2f); 780 if (lg_fail(ret)) 781 goto fail; 782 ret = lgdt3305_set_reg_bit(state, LGDT3305_CR_CTR_FREQ_1, 6, 1); 783 if (lg_fail(ret)) 784 goto fail; 785 786 ret = lgdt3305_set_if(state, param); 787 if (lg_fail(ret)) 788 goto fail; 789 ret = lgdt3305_spectral_inversion(state, param, 790 state->cfg->spectral_inversion 791 ? 1 : 0); 792 if (lg_fail(ret)) 793 goto fail; 794 795 ret = lgdt3305_set_filter_extension(state, param); 796 if (lg_fail(ret)) 797 goto fail; 798 799 state->current_modulation = param->u.vsb.modulation; 800 801 ret = lgdt3305_mpeg_mode(state, state->cfg->mpeg_mode); 802 if (lg_fail(ret)) 803 goto fail; 804 805 /* lgdt3305_mpeg_mode_polarity calls lgdt3305_soft_reset */ 806 ret = lgdt3305_mpeg_mode_polarity(state, 807 state->cfg->tpclk_edge, 808 state->cfg->tpvalid_polarity); 809fail: 810 return ret; 811} 812 813static int lgdt3305_get_frontend(struct dvb_frontend *fe, 814 struct dvb_frontend_parameters *param) 815{ 816 struct lgdt3305_state *state = fe->demodulator_priv; 817 818 lg_dbg("\n"); 819 820 param->u.vsb.modulation = state->current_modulation; 821 param->frequency = state->current_frequency; 822 return 0; 823} 824 825/* ------------------------------------------------------------------------ */ 826 827static int lgdt3305_read_cr_lock_status(struct lgdt3305_state *state, 828 int *locked) 829{ 830 u8 val; 831 int ret; 832 char *cr_lock_state = ""; 833 834 *locked = 0; 835 836 ret = lgdt3305_read_reg(state, LGDT3305_CR_LOCK_STATUS, &val); 837 if (lg_fail(ret)) 838 goto fail; 839 840 switch (state->current_modulation) { 841 case QAM_256: 842 case QAM_64: 843 if (val & (1 << 1)) 844 *locked = 1; 845 846 switch (val & 0x07) { 847 case 0: 848 cr_lock_state = "QAM UNLOCK"; 849 break; 850 case 4: 851 cr_lock_state = "QAM 1stLock"; 852 break; 853 case 6: 854 cr_lock_state = "QAM 2ndLock"; 855 break; 856 case 7: 857 cr_lock_state = "QAM FinalLock"; 858 break; 859 default: 860 cr_lock_state = "CLOCKQAM-INVALID!"; 861 break; 862 } 863 break; 864 case VSB_8: 865 if (val & (1 << 7)) { 866 *locked = 1; 867 cr_lock_state = "CLOCKVSB"; 868 } 869 break; 870 default: 871 ret = -EINVAL; 872 } 873 lg_dbg("(%d) %s\n", *locked, cr_lock_state); 874fail: 875 return ret; 876} 877 878static int lgdt3305_read_fec_lock_status(struct lgdt3305_state *state, 879 int *locked) 880{ 881 u8 val; 882 int ret, mpeg_lock, fec_lock, viterbi_lock; 883 884 *locked = 0; 885 886 switch (state->current_modulation) { 887 case QAM_256: 888 case QAM_64: 889 ret = lgdt3305_read_reg(state, 890 LGDT3305_FEC_LOCK_STATUS, &val); 891 if (lg_fail(ret)) 892 goto fail; 893 894 mpeg_lock = (val & (1 << 0)) ? 1 : 0; 895 fec_lock = (val & (1 << 2)) ? 1 : 0; 896 viterbi_lock = (val & (1 << 3)) ? 1 : 0; 897 898 *locked = mpeg_lock && fec_lock && viterbi_lock; 899 900 lg_dbg("(%d) %s%s%s\n", *locked, 901 mpeg_lock ? "mpeg lock " : "", 902 fec_lock ? "fec lock " : "", 903 viterbi_lock ? "viterbi lock" : ""); 904 break; 905 case VSB_8: 906 default: 907 ret = -EINVAL; 908 } 909fail: 910 return ret; 911} 912 913static int lgdt3305_read_status(struct dvb_frontend *fe, fe_status_t *status) 914{ 915 struct lgdt3305_state *state = fe->demodulator_priv; 916 u8 val; 917 int ret, signal, inlock, nofecerr, snrgood, 918 cr_lock, fec_lock, sync_lock; 919 920 *status = 0; 921 922 ret = lgdt3305_read_reg(state, LGDT3305_GEN_STATUS, &val); 923 if (lg_fail(ret)) 924 goto fail; 925 926 signal = (val & (1 << 4)) ? 1 : 0; 927 inlock = (val & (1 << 3)) ? 0 : 1; 928 sync_lock = (val & (1 << 2)) ? 1 : 0; 929 nofecerr = (val & (1 << 1)) ? 1 : 0; 930 snrgood = (val & (1 << 0)) ? 1 : 0; 931 932 lg_dbg("%s%s%s%s%s\n", 933 signal ? "SIGNALEXIST " : "", 934 inlock ? "INLOCK " : "", 935 sync_lock ? "SYNCLOCK " : "", 936 nofecerr ? "NOFECERR " : "", 937 snrgood ? "SNRGOOD " : ""); 938 939 ret = lgdt3305_read_cr_lock_status(state, &cr_lock); 940 if (lg_fail(ret)) 941 goto fail; 942 943 if (signal) 944 *status |= FE_HAS_SIGNAL; 945 if (cr_lock) 946 *status |= FE_HAS_CARRIER; 947 if (nofecerr) 948 *status |= FE_HAS_VITERBI; 949 if (sync_lock) 950 *status |= FE_HAS_SYNC; 951 952 switch (state->current_modulation) { 953 case QAM_256: 954 case QAM_64: 955 /* signal bit is unreliable on the DT3304 in QAM mode */ 956 if (((LGDT3304 == state->cfg->demod_chip)) && (cr_lock)) 957 *status |= FE_HAS_SIGNAL; 958 959 ret = lgdt3305_read_fec_lock_status(state, &fec_lock); 960 if (lg_fail(ret)) 961 goto fail; 962 963 if (fec_lock) 964 *status |= FE_HAS_LOCK; 965 break; 966 case VSB_8: 967 if (inlock) 968 *status |= FE_HAS_LOCK; 969 break; 970 default: 971 ret = -EINVAL; 972 } 973fail: 974 return ret; 975} 976 977/* ------------------------------------------------------------------------ */ 978 979/* borrowed from lgdt330x.c */ 980static u32 calculate_snr(u32 mse, u32 c) 981{ 982 if (mse == 0) /* no signal */ 983 return 0; 984 985 mse = intlog10(mse); 986 if (mse > c) { 987 /* Negative SNR, which is possible, but realisticly the 988 demod will lose lock before the signal gets this bad. The 989 API only allows for unsigned values, so just return 0 */ 990 return 0; 991 } 992 return 10*(c - mse); 993} 994 995static int lgdt3305_read_snr(struct dvb_frontend *fe, u16 *snr) 996{ 997 struct lgdt3305_state *state = fe->demodulator_priv; 998 u32 noise; /* noise value */ 999 u32 c; /* per-modulation SNR calculation constant */ 1000 1001 switch (state->current_modulation) { 1002 case VSB_8: 1003#ifdef USE_PTMSE 1004 /* Use Phase Tracker Mean-Square Error Register */ 1005 /* SNR for ranges from -13.11 to +44.08 */ 1006 noise = ((read_reg(state, LGDT3305_PT_MSE_1) & 0x07) << 16) | 1007 (read_reg(state, LGDT3305_PT_MSE_2) << 8) | 1008 (read_reg(state, LGDT3305_PT_MSE_3) & 0xff); 1009 c = 73957994; /* log10(25*32^2)*2^24 */ 1010#else 1011 /* Use Equalizer Mean-Square Error Register */ 1012 /* SNR for ranges from -16.12 to +44.08 */ 1013 noise = ((read_reg(state, LGDT3305_EQ_MSE_1) & 0x0f) << 16) | 1014 (read_reg(state, LGDT3305_EQ_MSE_2) << 8) | 1015 (read_reg(state, LGDT3305_EQ_MSE_3) & 0xff); 1016 c = 73957994; /* log10(25*32^2)*2^24 */ 1017#endif 1018 break; 1019 case QAM_64: 1020 case QAM_256: 1021 noise = (read_reg(state, LGDT3305_CR_MSE_1) << 8) | 1022 (read_reg(state, LGDT3305_CR_MSE_2) & 0xff); 1023 1024 c = (state->current_modulation == QAM_64) ? 1025 97939837 : 98026066; 1026 /* log10(688128)*2^24 and log10(696320)*2^24 */ 1027 break; 1028 default: 1029 return -EINVAL; 1030 } 1031 state->snr = calculate_snr(noise, c); 1032 /* report SNR in dB * 10 */ 1033 *snr = (state->snr / ((1 << 24) / 10)); 1034 lg_dbg("noise = 0x%08x, snr = %d.%02d dB\n", noise, 1035 state->snr >> 24, (((state->snr >> 8) & 0xffff) * 100) >> 16); 1036 1037 return 0; 1038} 1039 1040static int lgdt3305_read_signal_strength(struct dvb_frontend *fe, 1041 u16 *strength) 1042{ 1043 /* borrowed from lgdt330x.c 1044 * 1045 * Calculate strength from SNR up to 35dB 1046 * Even though the SNR can go higher than 35dB, 1047 * there is some comfort factor in having a range of 1048 * strong signals that can show at 100% 1049 */ 1050 struct lgdt3305_state *state = fe->demodulator_priv; 1051 u16 snr; 1052 int ret; 1053 1054 *strength = 0; 1055 1056 ret = fe->ops.read_snr(fe, &snr); 1057 if (lg_fail(ret)) 1058 goto fail; 1059 /* Rather than use the 8.8 value snr, use state->snr which is 8.24 */ 1060 /* scale the range 0 - 35*2^24 into 0 - 65535 */ 1061 if (state->snr >= 8960 * 0x10000) 1062 *strength = 0xffff; 1063 else 1064 *strength = state->snr / 8960; 1065fail: 1066 return ret; 1067} 1068 1069/* ------------------------------------------------------------------------ */ 1070 1071static int lgdt3305_read_ber(struct dvb_frontend *fe, u32 *ber) 1072{ 1073 *ber = 0; 1074 return 0; 1075} 1076 1077static int lgdt3305_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) 1078{ 1079 struct lgdt3305_state *state = fe->demodulator_priv; 1080 1081 *ucblocks = 1082 (read_reg(state, LGDT3305_FEC_PKT_ERR_1) << 8) | 1083 (read_reg(state, LGDT3305_FEC_PKT_ERR_2) & 0xff); 1084 1085 return 0; 1086} 1087 1088static int lgdt3305_get_tune_settings(struct dvb_frontend *fe, 1089 struct dvb_frontend_tune_settings 1090 *fe_tune_settings) 1091{ 1092 fe_tune_settings->min_delay_ms = 500; 1093 lg_dbg("\n"); 1094 return 0; 1095} 1096 1097static void lgdt3305_release(struct dvb_frontend *fe) 1098{ 1099 struct lgdt3305_state *state = fe->demodulator_priv; 1100 lg_dbg("\n"); 1101 kfree(state); 1102} 1103 1104static struct dvb_frontend_ops lgdt3304_ops; 1105static struct dvb_frontend_ops lgdt3305_ops; 1106 1107struct dvb_frontend *lgdt3305_attach(const struct lgdt3305_config *config, 1108 struct i2c_adapter *i2c_adap) 1109{ 1110 struct lgdt3305_state *state = NULL; 1111 int ret; 1112 u8 val; 1113 1114 lg_dbg("(%d-%04x)\n", 1115 i2c_adap ? i2c_adapter_id(i2c_adap) : 0, 1116 config ? config->i2c_addr : 0); 1117 1118 state = kzalloc(sizeof(struct lgdt3305_state), GFP_KERNEL); 1119 if (state == NULL) 1120 goto fail; 1121 1122 state->cfg = config; 1123 state->i2c_adap = i2c_adap; 1124 1125 switch (config->demod_chip) { 1126 case LGDT3304: 1127 memcpy(&state->frontend.ops, &lgdt3304_ops, 1128 sizeof(struct dvb_frontend_ops)); 1129 break; 1130 case LGDT3305: 1131 memcpy(&state->frontend.ops, &lgdt3305_ops, 1132 sizeof(struct dvb_frontend_ops)); 1133 break; 1134 default: 1135 goto fail; 1136 } 1137 state->frontend.demodulator_priv = state; 1138 1139 /* verify that we're talking to a lg dt3304/5 */ 1140 ret = lgdt3305_read_reg(state, LGDT3305_GEN_CTRL_2, &val); 1141 if ((lg_fail(ret)) | (val == 0)) 1142 goto fail; 1143 ret = lgdt3305_write_reg(state, 0x0808, 0x80); 1144 if (lg_fail(ret)) 1145 goto fail; 1146 ret = lgdt3305_read_reg(state, 0x0808, &val); 1147 if ((lg_fail(ret)) | (val != 0x80)) 1148 goto fail; 1149 ret = lgdt3305_write_reg(state, 0x0808, 0x00); 1150 if (lg_fail(ret)) 1151 goto fail; 1152 1153 state->current_frequency = -1; 1154 state->current_modulation = -1; 1155 1156 return &state->frontend; 1157fail: 1158 lg_warn("unable to detect %s hardware\n", 1159 config->demod_chip ? "LGDT3304" : "LGDT3305"); 1160 kfree(state); 1161 return NULL; 1162} 1163EXPORT_SYMBOL(lgdt3305_attach); 1164 1165static struct dvb_frontend_ops lgdt3304_ops = { 1166 .info = { 1167 .name = "LG Electronics LGDT3304 VSB/QAM Frontend", 1168 .type = FE_ATSC, 1169 .frequency_min = 54000000, 1170 .frequency_max = 858000000, 1171 .frequency_stepsize = 62500, 1172 .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB 1173 }, 1174 .i2c_gate_ctrl = lgdt3305_i2c_gate_ctrl, 1175 .init = lgdt3305_init, 1176 .set_frontend = lgdt3304_set_parameters, 1177 .get_frontend = lgdt3305_get_frontend, 1178 .get_tune_settings = lgdt3305_get_tune_settings, 1179 .read_status = lgdt3305_read_status, 1180 .read_ber = lgdt3305_read_ber, 1181 .read_signal_strength = lgdt3305_read_signal_strength, 1182 .read_snr = lgdt3305_read_snr, 1183 .read_ucblocks = lgdt3305_read_ucblocks, 1184 .release = lgdt3305_release, 1185}; 1186 1187static struct dvb_frontend_ops lgdt3305_ops = { 1188 .info = { 1189 .name = "LG Electronics LGDT3305 VSB/QAM Frontend", 1190 .type = FE_ATSC, 1191 .frequency_min = 54000000, 1192 .frequency_max = 858000000, 1193 .frequency_stepsize = 62500, 1194 .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB 1195 }, 1196 .i2c_gate_ctrl = lgdt3305_i2c_gate_ctrl, 1197 .init = lgdt3305_init, 1198 .sleep = lgdt3305_sleep, 1199 .set_frontend = lgdt3305_set_parameters, 1200 .get_frontend = lgdt3305_get_frontend, 1201 .get_tune_settings = lgdt3305_get_tune_settings, 1202 .read_status = lgdt3305_read_status, 1203 .read_ber = lgdt3305_read_ber, 1204 .read_signal_strength = lgdt3305_read_signal_strength, 1205 .read_snr = lgdt3305_read_snr, 1206 .read_ucblocks = lgdt3305_read_ucblocks, 1207 .release = lgdt3305_release, 1208}; 1209 1210MODULE_DESCRIPTION("LG Electronics LGDT3304/5 ATSC/QAM-B Demodulator Driver"); 1211MODULE_AUTHOR("Michael Krufky <mkrufky@linuxtv.org>"); 1212MODULE_LICENSE("GPL"); 1213MODULE_VERSION("0.2"); 1214 1215/* 1216 * Local variables: 1217 * c-basic-offset: 8 1218 * End: 1219 */ 1220