1/* 2 * video1394.c - video driver for OHCI 1394 boards 3 * Copyright (C)1999,2000 Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au> 4 * Peter Schlaile <udbz@rz.uni-karlsruhe.de> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software Foundation, 18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 19 * 20 * NOTES: 21 * 22 * ioctl return codes: 23 * EFAULT is only for invalid address for the argp 24 * EINVAL for out of range values 25 * EBUSY when trying to use an already used resource 26 * ESRCH when trying to free/stop a not used resource 27 * EAGAIN for resource allocation failure that could perhaps succeed later 28 * ENOTTY for unsupported ioctl request 29 * 30 */ 31#include <linux/kernel.h> 32#include <linux/list.h> 33#include <linux/sched.h> 34#include <linux/slab.h> 35#include <linux/interrupt.h> 36#include <linux/wait.h> 37#include <linux/errno.h> 38#include <linux/module.h> 39#include <linux/init.h> 40#include <linux/pci.h> 41#include <linux/fs.h> 42#include <linux/poll.h> 43#include <linux/delay.h> 44#include <linux/bitops.h> 45#include <linux/types.h> 46#include <linux/vmalloc.h> 47#include <linux/timex.h> 48#include <linux/mm.h> 49#include <linux/compat.h> 50#include <linux/cdev.h> 51 52#include "dma.h" 53#include "highlevel.h" 54#include "hosts.h" 55#include "ieee1394.h" 56#include "ieee1394_core.h" 57#include "ieee1394_hotplug.h" 58#include "ieee1394_types.h" 59#include "nodemgr.h" 60#include "ohci1394.h" 61#include "video1394.h" 62 63#define ISO_CHANNELS 64 64 65struct it_dma_prg { 66 struct dma_cmd begin; 67 quadlet_t data[4]; 68 struct dma_cmd end; 69 quadlet_t pad[4]; 70}; 71 72struct dma_iso_ctx { 73 struct ti_ohci *ohci; 74 int type; /* OHCI_ISO_TRANSMIT or OHCI_ISO_RECEIVE */ 75 struct ohci1394_iso_tasklet iso_tasklet; 76 int channel; 77 int ctx; 78 int last_buffer; 79 int * next_buffer; /* For ISO Transmit of video packets 80 to write the correct SYT field 81 into the next block */ 82 unsigned int num_desc; 83 unsigned int buf_size; 84 unsigned int frame_size; 85 unsigned int packet_size; 86 unsigned int left_size; 87 unsigned int nb_cmd; 88 89 struct dma_region dma; 90 91 struct dma_prog_region *prg_reg; 92 93 struct dma_cmd **ir_prg; 94 struct it_dma_prg **it_prg; 95 96 unsigned int *buffer_status; 97 unsigned int *buffer_prg_assignment; 98 struct timeval *buffer_time; /* time when the buffer was received */ 99 unsigned int *last_used_cmd; /* For ISO Transmit with 100 variable sized packets only ! */ 101 int ctrlClear; 102 int ctrlSet; 103 int cmdPtr; 104 int ctxMatch; 105 wait_queue_head_t waitq; 106 spinlock_t lock; 107 unsigned int syt_offset; 108 int flags; 109 110 struct list_head link; 111}; 112 113 114struct file_ctx { 115 struct ti_ohci *ohci; 116 struct list_head context_list; 117 struct dma_iso_ctx *current_ctx; 118}; 119 120#ifdef CONFIG_IEEE1394_VERBOSEDEBUG 121#define VIDEO1394_DEBUG 122#endif 123 124#ifdef DBGMSG 125#undef DBGMSG 126#endif 127 128#ifdef VIDEO1394_DEBUG 129#define DBGMSG(card, fmt, args...) \ 130printk(KERN_INFO "video1394_%d: " fmt "\n" , card , ## args) 131#else 132#define DBGMSG(card, fmt, args...) do {} while (0) 133#endif 134 135/* print general (card independent) information */ 136#define PRINT_G(level, fmt, args...) \ 137printk(level "video1394: " fmt "\n" , ## args) 138 139/* print card specific information */ 140#define PRINT(level, card, fmt, args...) \ 141printk(level "video1394_%d: " fmt "\n" , card , ## args) 142 143static void wakeup_dma_ir_ctx(unsigned long l); 144static void wakeup_dma_it_ctx(unsigned long l); 145 146static struct hpsb_highlevel video1394_highlevel; 147 148static int free_dma_iso_ctx(struct dma_iso_ctx *d) 149{ 150 int i; 151 152 DBGMSG(d->ohci->host->id, "Freeing dma_iso_ctx %d", d->ctx); 153 154 ohci1394_stop_context(d->ohci, d->ctrlClear, NULL); 155 if (d->iso_tasklet.link.next != NULL) 156 ohci1394_unregister_iso_tasklet(d->ohci, &d->iso_tasklet); 157 158 dma_region_free(&d->dma); 159 160 if (d->prg_reg) { 161 for (i = 0; i < d->num_desc; i++) 162 dma_prog_region_free(&d->prg_reg[i]); 163 kfree(d->prg_reg); 164 } 165 166 kfree(d->ir_prg); 167 kfree(d->it_prg); 168 kfree(d->buffer_status); 169 kfree(d->buffer_prg_assignment); 170 kfree(d->buffer_time); 171 kfree(d->last_used_cmd); 172 kfree(d->next_buffer); 173 list_del(&d->link); 174 kfree(d); 175 176 return 0; 177} 178 179static struct dma_iso_ctx * 180alloc_dma_iso_ctx(struct ti_ohci *ohci, int type, int num_desc, 181 int buf_size, int channel, unsigned int packet_size) 182{ 183 struct dma_iso_ctx *d; 184 int i; 185 186 d = kzalloc(sizeof(*d), GFP_KERNEL); 187 if (!d) { 188 PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma_iso_ctx"); 189 return NULL; 190 } 191 192 d->ohci = ohci; 193 d->type = type; 194 d->channel = channel; 195 d->num_desc = num_desc; 196 d->frame_size = buf_size; 197 d->buf_size = PAGE_ALIGN(buf_size); 198 d->last_buffer = -1; 199 INIT_LIST_HEAD(&d->link); 200 init_waitqueue_head(&d->waitq); 201 202 /* Init the regions for easy cleanup */ 203 dma_region_init(&d->dma); 204 205 if (dma_region_alloc(&d->dma, (d->num_desc - 1) * d->buf_size, ohci->dev, 206 PCI_DMA_BIDIRECTIONAL)) { 207 PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma buffer"); 208 free_dma_iso_ctx(d); 209 return NULL; 210 } 211 212 if (type == OHCI_ISO_RECEIVE) 213 ohci1394_init_iso_tasklet(&d->iso_tasklet, type, 214 wakeup_dma_ir_ctx, 215 (unsigned long) d); 216 else 217 ohci1394_init_iso_tasklet(&d->iso_tasklet, type, 218 wakeup_dma_it_ctx, 219 (unsigned long) d); 220 221 if (ohci1394_register_iso_tasklet(ohci, &d->iso_tasklet) < 0) { 222 PRINT(KERN_ERR, ohci->host->id, "no free iso %s contexts", 223 type == OHCI_ISO_RECEIVE ? "receive" : "transmit"); 224 free_dma_iso_ctx(d); 225 return NULL; 226 } 227 d->ctx = d->iso_tasklet.context; 228 229 d->prg_reg = kmalloc(d->num_desc * sizeof(*d->prg_reg), GFP_KERNEL); 230 if (!d->prg_reg) { 231 PRINT(KERN_ERR, ohci->host->id, "Failed to allocate ir prg regs"); 232 free_dma_iso_ctx(d); 233 return NULL; 234 } 235 /* Makes for easier cleanup */ 236 for (i = 0; i < d->num_desc; i++) 237 dma_prog_region_init(&d->prg_reg[i]); 238 239 if (type == OHCI_ISO_RECEIVE) { 240 d->ctrlSet = OHCI1394_IsoRcvContextControlSet+32*d->ctx; 241 d->ctrlClear = OHCI1394_IsoRcvContextControlClear+32*d->ctx; 242 d->cmdPtr = OHCI1394_IsoRcvCommandPtr+32*d->ctx; 243 d->ctxMatch = OHCI1394_IsoRcvContextMatch+32*d->ctx; 244 245 d->ir_prg = kzalloc(d->num_desc * sizeof(*d->ir_prg), 246 GFP_KERNEL); 247 248 if (!d->ir_prg) { 249 PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma ir prg"); 250 free_dma_iso_ctx(d); 251 return NULL; 252 } 253 254 d->nb_cmd = d->buf_size / PAGE_SIZE + 1; 255 d->left_size = (d->frame_size % PAGE_SIZE) ? 256 d->frame_size % PAGE_SIZE : PAGE_SIZE; 257 258 for (i = 0;i < d->num_desc; i++) { 259 if (dma_prog_region_alloc(&d->prg_reg[i], d->nb_cmd * 260 sizeof(struct dma_cmd), ohci->dev)) { 261 PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma ir prg"); 262 free_dma_iso_ctx(d); 263 return NULL; 264 } 265 d->ir_prg[i] = (struct dma_cmd *)d->prg_reg[i].kvirt; 266 } 267 268 } else { /* OHCI_ISO_TRANSMIT */ 269 d->ctrlSet = OHCI1394_IsoXmitContextControlSet+16*d->ctx; 270 d->ctrlClear = OHCI1394_IsoXmitContextControlClear+16*d->ctx; 271 d->cmdPtr = OHCI1394_IsoXmitCommandPtr+16*d->ctx; 272 273 d->it_prg = kzalloc(d->num_desc * sizeof(*d->it_prg), 274 GFP_KERNEL); 275 276 if (!d->it_prg) { 277 PRINT(KERN_ERR, ohci->host->id, 278 "Failed to allocate dma it prg"); 279 free_dma_iso_ctx(d); 280 return NULL; 281 } 282 283 d->packet_size = packet_size; 284 285 if (PAGE_SIZE % packet_size || packet_size>4096) { 286 PRINT(KERN_ERR, ohci->host->id, 287 "Packet size %d (page_size: %ld) " 288 "not yet supported\n", 289 packet_size, PAGE_SIZE); 290 free_dma_iso_ctx(d); 291 return NULL; 292 } 293 294 d->nb_cmd = d->frame_size / d->packet_size; 295 if (d->frame_size % d->packet_size) { 296 d->nb_cmd++; 297 d->left_size = d->frame_size % d->packet_size; 298 } else 299 d->left_size = d->packet_size; 300 301 for (i = 0; i < d->num_desc; i++) { 302 if (dma_prog_region_alloc(&d->prg_reg[i], d->nb_cmd * 303 sizeof(struct it_dma_prg), ohci->dev)) { 304 PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma it prg"); 305 free_dma_iso_ctx(d); 306 return NULL; 307 } 308 d->it_prg[i] = (struct it_dma_prg *)d->prg_reg[i].kvirt; 309 } 310 } 311 312 d->buffer_status = 313 kzalloc(d->num_desc * sizeof(*d->buffer_status), GFP_KERNEL); 314 d->buffer_prg_assignment = 315 kzalloc(d->num_desc * sizeof(*d->buffer_prg_assignment), GFP_KERNEL); 316 d->buffer_time = 317 kzalloc(d->num_desc * sizeof(*d->buffer_time), GFP_KERNEL); 318 d->last_used_cmd = 319 kzalloc(d->num_desc * sizeof(*d->last_used_cmd), GFP_KERNEL); 320 d->next_buffer = 321 kzalloc(d->num_desc * sizeof(*d->next_buffer), GFP_KERNEL); 322 323 if (!d->buffer_status || !d->buffer_prg_assignment || !d->buffer_time || 324 !d->last_used_cmd || !d->next_buffer) { 325 PRINT(KERN_ERR, ohci->host->id, 326 "Failed to allocate dma_iso_ctx member"); 327 free_dma_iso_ctx(d); 328 return NULL; 329 } 330 331 spin_lock_init(&d->lock); 332 333 DBGMSG(ohci->host->id, "Iso %s DMA: %d buffers " 334 "of size %d allocated for a frame size %d, each with %d prgs", 335 (type == OHCI_ISO_RECEIVE) ? "receive" : "transmit", 336 d->num_desc - 1, d->buf_size, d->frame_size, d->nb_cmd); 337 338 return d; 339} 340 341static void reset_ir_status(struct dma_iso_ctx *d, int n) 342{ 343 int i; 344 d->ir_prg[n][0].status = cpu_to_le32(4); 345 d->ir_prg[n][1].status = cpu_to_le32(PAGE_SIZE-4); 346 for (i = 2; i < d->nb_cmd - 1; i++) 347 d->ir_prg[n][i].status = cpu_to_le32(PAGE_SIZE); 348 d->ir_prg[n][i].status = cpu_to_le32(d->left_size); 349} 350 351static void reprogram_dma_ir_prg(struct dma_iso_ctx *d, int n, int buffer, int flags) 352{ 353 struct dma_cmd *ir_prg = d->ir_prg[n]; 354 unsigned long buf = (unsigned long)d->dma.kvirt + buffer * d->buf_size; 355 int i; 356 357 d->buffer_prg_assignment[n] = buffer; 358 359 ir_prg[0].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma, buf - 360 (unsigned long)d->dma.kvirt)); 361 ir_prg[1].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma, 362 (buf + 4) - (unsigned long)d->dma.kvirt)); 363 364 for (i=2;i<d->nb_cmd-1;i++) { 365 ir_prg[i].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma, 366 (buf+(i-1)*PAGE_SIZE) - 367 (unsigned long)d->dma.kvirt)); 368 } 369 370 ir_prg[i].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE | 371 DMA_CTL_IRQ | DMA_CTL_BRANCH | d->left_size); 372 ir_prg[i].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma, 373 (buf+(i-1)*PAGE_SIZE) - (unsigned long)d->dma.kvirt)); 374} 375 376static void initialize_dma_ir_prg(struct dma_iso_ctx *d, int n, int flags) 377{ 378 struct dma_cmd *ir_prg = d->ir_prg[n]; 379 struct dma_prog_region *ir_reg = &d->prg_reg[n]; 380 unsigned long buf = (unsigned long)d->dma.kvirt; 381 int i; 382 383 /* the first descriptor will read only 4 bytes */ 384 ir_prg[0].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE | 385 DMA_CTL_BRANCH | 4); 386 387 /* set the sync flag */ 388 if (flags & VIDEO1394_SYNC_FRAMES) 389 ir_prg[0].control |= cpu_to_le32(DMA_CTL_WAIT); 390 391 ir_prg[0].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma, buf - 392 (unsigned long)d->dma.kvirt)); 393 ir_prg[0].branchAddress = cpu_to_le32((dma_prog_region_offset_to_bus(ir_reg, 394 1 * sizeof(struct dma_cmd)) & 0xfffffff0) | 0x1); 395 396 /* If there is *not* only one DMA page per frame (hence, d->nb_cmd==2) */ 397 if (d->nb_cmd > 2) { 398 /* The second descriptor will read PAGE_SIZE-4 bytes */ 399 ir_prg[1].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE | 400 DMA_CTL_BRANCH | (PAGE_SIZE-4)); 401 ir_prg[1].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma, (buf + 4) - 402 (unsigned long)d->dma.kvirt)); 403 ir_prg[1].branchAddress = cpu_to_le32((dma_prog_region_offset_to_bus(ir_reg, 404 2 * sizeof(struct dma_cmd)) & 0xfffffff0) | 0x1); 405 406 for (i = 2; i < d->nb_cmd - 1; i++) { 407 ir_prg[i].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE | 408 DMA_CTL_BRANCH | PAGE_SIZE); 409 ir_prg[i].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma, 410 (buf+(i-1)*PAGE_SIZE) - 411 (unsigned long)d->dma.kvirt)); 412 413 ir_prg[i].branchAddress = 414 cpu_to_le32((dma_prog_region_offset_to_bus(ir_reg, 415 (i + 1) * sizeof(struct dma_cmd)) & 0xfffffff0) | 0x1); 416 } 417 418 /* The last descriptor will generate an interrupt */ 419 ir_prg[i].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE | 420 DMA_CTL_IRQ | DMA_CTL_BRANCH | d->left_size); 421 ir_prg[i].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma, 422 (buf+(i-1)*PAGE_SIZE) - 423 (unsigned long)d->dma.kvirt)); 424 } else { 425 /* Only one DMA page is used. Read d->left_size immediately and */ 426 /* generate an interrupt as this is also the last page. */ 427 ir_prg[1].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE | 428 DMA_CTL_IRQ | DMA_CTL_BRANCH | (d->left_size-4)); 429 ir_prg[1].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma, 430 (buf + 4) - (unsigned long)d->dma.kvirt)); 431 } 432} 433 434static void initialize_dma_ir_ctx(struct dma_iso_ctx *d, int tag, int flags) 435{ 436 struct ti_ohci *ohci = (struct ti_ohci *)d->ohci; 437 int i; 438 439 d->flags = flags; 440 441 ohci1394_stop_context(ohci, d->ctrlClear, NULL); 442 443 for (i=0;i<d->num_desc;i++) { 444 initialize_dma_ir_prg(d, i, flags); 445 reset_ir_status(d, i); 446 } 447 448 /* reset the ctrl register */ 449 reg_write(ohci, d->ctrlClear, 0xf0000000); 450 451 /* Set bufferFill */ 452 reg_write(ohci, d->ctrlSet, 0x80000000); 453 454 /* Set isoch header */ 455 if (flags & VIDEO1394_INCLUDE_ISO_HEADERS) 456 reg_write(ohci, d->ctrlSet, 0x40000000); 457 458 /* Set the context match register to match on all tags, 459 sync for sync tag, and listen to d->channel */ 460 reg_write(ohci, d->ctxMatch, 0xf0000000|((tag&0xf)<<8)|d->channel); 461 462 /* Set up isoRecvIntMask to generate interrupts */ 463 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1<<d->ctx); 464} 465 466/* find which context is listening to this channel */ 467static struct dma_iso_ctx * 468find_ctx(struct list_head *list, int type, int channel) 469{ 470 struct dma_iso_ctx *ctx; 471 472 list_for_each_entry(ctx, list, link) { 473 if (ctx->type == type && ctx->channel == channel) 474 return ctx; 475 } 476 477 return NULL; 478} 479 480static void wakeup_dma_ir_ctx(unsigned long l) 481{ 482 struct dma_iso_ctx *d = (struct dma_iso_ctx *) l; 483 int i; 484 485 spin_lock(&d->lock); 486 487 for (i = 0; i < d->num_desc; i++) { 488 if (d->ir_prg[i][d->nb_cmd-1].status & cpu_to_le32(0xFFFF0000)) { 489 reset_ir_status(d, i); 490 d->buffer_status[d->buffer_prg_assignment[i]] = VIDEO1394_BUFFER_READY; 491 do_gettimeofday(&d->buffer_time[d->buffer_prg_assignment[i]]); 492 dma_region_sync_for_cpu(&d->dma, 493 d->buffer_prg_assignment[i] * d->buf_size, 494 d->buf_size); 495 } 496 } 497 498 spin_unlock(&d->lock); 499 500 if (waitqueue_active(&d->waitq)) 501 wake_up_interruptible(&d->waitq); 502} 503 504static inline void put_timestamp(struct ti_ohci *ohci, struct dma_iso_ctx * d, 505 int n) 506{ 507 unsigned char* buf = d->dma.kvirt + n * d->buf_size; 508 u32 cycleTimer; 509 u32 timeStamp; 510 511 if (n == -1) { 512 return; 513 } 514 515 cycleTimer = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 516 517 timeStamp = ((cycleTimer & 0x0fff) + d->syt_offset); /* 11059 = 450 us */ 518 timeStamp = (timeStamp % 3072 + ((timeStamp / 3072) << 12) 519 + (cycleTimer & 0xf000)) & 0xffff; 520 521 buf[6] = timeStamp >> 8; 522 buf[7] = timeStamp & 0xff; 523 524 /* if first packet is empty packet, then put timestamp into the next full one too */ 525 if ( (le32_to_cpu(d->it_prg[n][0].data[1]) >>16) == 0x008) { 526 buf += d->packet_size; 527 buf[6] = timeStamp >> 8; 528 buf[7] = timeStamp & 0xff; 529 } 530 531 /* do the next buffer frame too in case of irq latency */ 532 n = d->next_buffer[n]; 533 if (n == -1) { 534 return; 535 } 536 buf = d->dma.kvirt + n * d->buf_size; 537 538 timeStamp += (d->last_used_cmd[n] << 12) & 0xffff; 539 540 buf[6] = timeStamp >> 8; 541 buf[7] = timeStamp & 0xff; 542 543 /* if first packet is empty packet, then put timestamp into the next full one too */ 544 if ( (le32_to_cpu(d->it_prg[n][0].data[1]) >>16) == 0x008) { 545 buf += d->packet_size; 546 buf[6] = timeStamp >> 8; 547 buf[7] = timeStamp & 0xff; 548 } 549 550} 551 552static void wakeup_dma_it_ctx(unsigned long l) 553{ 554 struct dma_iso_ctx *d = (struct dma_iso_ctx *) l; 555 struct ti_ohci *ohci = d->ohci; 556 int i; 557 558 spin_lock(&d->lock); 559 560 for (i = 0; i < d->num_desc; i++) { 561 if (d->it_prg[i][d->last_used_cmd[i]].end.status & 562 cpu_to_le32(0xFFFF0000)) { 563 int next = d->next_buffer[i]; 564 put_timestamp(ohci, d, next); 565 d->it_prg[i][d->last_used_cmd[i]].end.status = 0; 566 d->buffer_status[d->buffer_prg_assignment[i]] = VIDEO1394_BUFFER_READY; 567 } 568 } 569 570 spin_unlock(&d->lock); 571 572 if (waitqueue_active(&d->waitq)) 573 wake_up_interruptible(&d->waitq); 574} 575 576static void reprogram_dma_it_prg(struct dma_iso_ctx *d, int n, int buffer) 577{ 578 struct it_dma_prg *it_prg = d->it_prg[n]; 579 unsigned long buf = (unsigned long)d->dma.kvirt + buffer * d->buf_size; 580 int i; 581 582 d->buffer_prg_assignment[n] = buffer; 583 for (i=0;i<d->nb_cmd;i++) { 584 it_prg[i].end.address = 585 cpu_to_le32(dma_region_offset_to_bus(&d->dma, 586 (buf+i*d->packet_size) - (unsigned long)d->dma.kvirt)); 587 } 588} 589 590static void initialize_dma_it_prg(struct dma_iso_ctx *d, int n, int sync_tag) 591{ 592 struct it_dma_prg *it_prg = d->it_prg[n]; 593 struct dma_prog_region *it_reg = &d->prg_reg[n]; 594 unsigned long buf = (unsigned long)d->dma.kvirt; 595 int i; 596 d->last_used_cmd[n] = d->nb_cmd - 1; 597 for (i=0;i<d->nb_cmd;i++) { 598 599 it_prg[i].begin.control = cpu_to_le32(DMA_CTL_OUTPUT_MORE | 600 DMA_CTL_IMMEDIATE | 8) ; 601 it_prg[i].begin.address = 0; 602 603 it_prg[i].begin.status = 0; 604 605 it_prg[i].data[0] = cpu_to_le32( 606 (IEEE1394_SPEED_100 << 16) 607 | (/* tag */ 1 << 14) 608 | (d->channel << 8) 609 | (TCODE_ISO_DATA << 4)); 610 if (i==0) it_prg[i].data[0] |= cpu_to_le32(sync_tag); 611 it_prg[i].data[1] = cpu_to_le32(d->packet_size << 16); 612 it_prg[i].data[2] = 0; 613 it_prg[i].data[3] = 0; 614 615 it_prg[i].end.control = cpu_to_le32(DMA_CTL_OUTPUT_LAST | 616 DMA_CTL_BRANCH); 617 it_prg[i].end.address = 618 cpu_to_le32(dma_region_offset_to_bus(&d->dma, (buf+i*d->packet_size) - 619 (unsigned long)d->dma.kvirt)); 620 621 if (i<d->nb_cmd-1) { 622 it_prg[i].end.control |= cpu_to_le32(d->packet_size); 623 it_prg[i].begin.branchAddress = 624 cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) * 625 sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3); 626 it_prg[i].end.branchAddress = 627 cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) * 628 sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3); 629 } else { 630 /* the last prg generates an interrupt */ 631 it_prg[i].end.control |= cpu_to_le32(DMA_CTL_UPDATE | 632 DMA_CTL_IRQ | d->left_size); 633 /* the last prg doesn't branch */ 634 it_prg[i].begin.branchAddress = 0; 635 it_prg[i].end.branchAddress = 0; 636 } 637 it_prg[i].end.status = 0; 638 } 639} 640 641static void initialize_dma_it_prg_var_packet_queue( 642 struct dma_iso_ctx *d, int n, unsigned int * packet_sizes, 643 struct ti_ohci *ohci) 644{ 645 struct it_dma_prg *it_prg = d->it_prg[n]; 646 struct dma_prog_region *it_reg = &d->prg_reg[n]; 647 int i; 648 649 d->last_used_cmd[n] = d->nb_cmd - 1; 650 651 for (i = 0; i < d->nb_cmd; i++) { 652 unsigned int size; 653 if (packet_sizes[i] > d->packet_size) { 654 size = d->packet_size; 655 } else { 656 size = packet_sizes[i]; 657 } 658 it_prg[i].data[1] = cpu_to_le32(size << 16); 659 it_prg[i].end.control = cpu_to_le32(DMA_CTL_OUTPUT_LAST | DMA_CTL_BRANCH); 660 661 if (i < d->nb_cmd-1 && packet_sizes[i+1] != 0) { 662 it_prg[i].end.control |= cpu_to_le32(size); 663 it_prg[i].begin.branchAddress = 664 cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) * 665 sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3); 666 it_prg[i].end.branchAddress = 667 cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) * 668 sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3); 669 } else { 670 /* the last prg generates an interrupt */ 671 it_prg[i].end.control |= cpu_to_le32(DMA_CTL_UPDATE | 672 DMA_CTL_IRQ | size); 673 /* the last prg doesn't branch */ 674 it_prg[i].begin.branchAddress = 0; 675 it_prg[i].end.branchAddress = 0; 676 d->last_used_cmd[n] = i; 677 break; 678 } 679 } 680} 681 682static void initialize_dma_it_ctx(struct dma_iso_ctx *d, int sync_tag, 683 unsigned int syt_offset, int flags) 684{ 685 struct ti_ohci *ohci = (struct ti_ohci *)d->ohci; 686 int i; 687 688 d->flags = flags; 689 d->syt_offset = (syt_offset == 0 ? 11000 : syt_offset); 690 691 ohci1394_stop_context(ohci, d->ctrlClear, NULL); 692 693 for (i=0;i<d->num_desc;i++) 694 initialize_dma_it_prg(d, i, sync_tag); 695 696 /* Set up isoRecvIntMask to generate interrupts */ 697 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1<<d->ctx); 698} 699 700static inline unsigned video1394_buffer_state(struct dma_iso_ctx *d, 701 unsigned int buffer) 702{ 703 unsigned long flags; 704 unsigned int ret; 705 spin_lock_irqsave(&d->lock, flags); 706 ret = d->buffer_status[buffer]; 707 spin_unlock_irqrestore(&d->lock, flags); 708 return ret; 709} 710 711static long video1394_ioctl(struct file *file, 712 unsigned int cmd, unsigned long arg) 713{ 714 struct file_ctx *ctx = file->private_data; 715 struct ti_ohci *ohci = ctx->ohci; 716 unsigned long flags; 717 void __user *argp = (void __user *)arg; 718 719 switch(cmd) 720 { 721 case VIDEO1394_IOC_LISTEN_CHANNEL: 722 case VIDEO1394_IOC_TALK_CHANNEL: 723 { 724 struct video1394_mmap v; 725 u64 mask; 726 struct dma_iso_ctx *d; 727 int i; 728 729 if (copy_from_user(&v, argp, sizeof(v))) 730 return -EFAULT; 731 732 /* if channel < 0, find lowest available one */ 733 if (v.channel < 0) { 734 mask = (u64)0x1; 735 for (i=0; ; i++) { 736 if (i == ISO_CHANNELS) { 737 PRINT(KERN_ERR, ohci->host->id, 738 "No free channel found"); 739 return -EAGAIN; 740 } 741 if (!(ohci->ISO_channel_usage & mask)) { 742 v.channel = i; 743 PRINT(KERN_INFO, ohci->host->id, "Found free channel %d", i); 744 break; 745 } 746 mask = mask << 1; 747 } 748 } else if (v.channel >= ISO_CHANNELS) { 749 PRINT(KERN_ERR, ohci->host->id, 750 "Iso channel %d out of bounds", v.channel); 751 return -EINVAL; 752 } else { 753 mask = (u64)0x1<<v.channel; 754 } 755 DBGMSG(ohci->host->id, "mask: %08X%08X usage: %08X%08X\n", 756 (u32)(mask>>32),(u32)(mask&0xffffffff), 757 (u32)(ohci->ISO_channel_usage>>32), 758 (u32)(ohci->ISO_channel_usage&0xffffffff)); 759 if (ohci->ISO_channel_usage & mask) { 760 PRINT(KERN_ERR, ohci->host->id, 761 "Channel %d is already taken", v.channel); 762 return -EBUSY; 763 } 764 765 if (v.buf_size == 0 || v.buf_size > VIDEO1394_MAX_SIZE) { 766 PRINT(KERN_ERR, ohci->host->id, 767 "Invalid %d length buffer requested",v.buf_size); 768 return -EINVAL; 769 } 770 771 if (v.nb_buffers == 0 || v.nb_buffers > VIDEO1394_MAX_SIZE) { 772 PRINT(KERN_ERR, ohci->host->id, 773 "Invalid %d buffers requested",v.nb_buffers); 774 return -EINVAL; 775 } 776 777 if (v.nb_buffers * v.buf_size > VIDEO1394_MAX_SIZE) { 778 PRINT(KERN_ERR, ohci->host->id, 779 "%d buffers of size %d bytes is too big", 780 v.nb_buffers, v.buf_size); 781 return -EINVAL; 782 } 783 784 if (cmd == VIDEO1394_IOC_LISTEN_CHANNEL) { 785 d = alloc_dma_iso_ctx(ohci, OHCI_ISO_RECEIVE, 786 v.nb_buffers + 1, v.buf_size, 787 v.channel, 0); 788 789 if (d == NULL) { 790 PRINT(KERN_ERR, ohci->host->id, 791 "Couldn't allocate ir context"); 792 return -EAGAIN; 793 } 794 initialize_dma_ir_ctx(d, v.sync_tag, v.flags); 795 796 ctx->current_ctx = d; 797 798 v.buf_size = d->buf_size; 799 list_add_tail(&d->link, &ctx->context_list); 800 801 DBGMSG(ohci->host->id, 802 "iso context %d listen on channel %d", 803 d->ctx, v.channel); 804 } 805 else { 806 d = alloc_dma_iso_ctx(ohci, OHCI_ISO_TRANSMIT, 807 v.nb_buffers + 1, v.buf_size, 808 v.channel, v.packet_size); 809 810 if (d == NULL) { 811 PRINT(KERN_ERR, ohci->host->id, 812 "Couldn't allocate it context"); 813 return -EAGAIN; 814 } 815 initialize_dma_it_ctx(d, v.sync_tag, 816 v.syt_offset, v.flags); 817 818 ctx->current_ctx = d; 819 820 v.buf_size = d->buf_size; 821 822 list_add_tail(&d->link, &ctx->context_list); 823 824 DBGMSG(ohci->host->id, 825 "Iso context %d talk on channel %d", d->ctx, 826 v.channel); 827 } 828 829 if (copy_to_user(argp, &v, sizeof(v))) { 830 return -EFAULT; 831 } 832 833 ohci->ISO_channel_usage |= mask; 834 835 return 0; 836 } 837 case VIDEO1394_IOC_UNLISTEN_CHANNEL: 838 case VIDEO1394_IOC_UNTALK_CHANNEL: 839 { 840 int channel; 841 u64 mask; 842 struct dma_iso_ctx *d; 843 844 if (copy_from_user(&channel, argp, sizeof(int))) 845 return -EFAULT; 846 847 if (channel < 0 || channel >= ISO_CHANNELS) { 848 PRINT(KERN_ERR, ohci->host->id, 849 "Iso channel %d out of bound", channel); 850 return -EINVAL; 851 } 852 mask = (u64)0x1<<channel; 853 if (!(ohci->ISO_channel_usage & mask)) { 854 PRINT(KERN_ERR, ohci->host->id, 855 "Channel %d is not being used", channel); 856 return -ESRCH; 857 } 858 859 /* Mark this channel as unused */ 860 ohci->ISO_channel_usage &= ~mask; 861 862 if (cmd == VIDEO1394_IOC_UNLISTEN_CHANNEL) 863 d = find_ctx(&ctx->context_list, OHCI_ISO_RECEIVE, channel); 864 else 865 d = find_ctx(&ctx->context_list, OHCI_ISO_TRANSMIT, channel); 866 867 if (d == NULL) return -ESRCH; 868 DBGMSG(ohci->host->id, "Iso context %d " 869 "stop talking on channel %d", d->ctx, channel); 870 free_dma_iso_ctx(d); 871 872 return 0; 873 } 874 case VIDEO1394_IOC_LISTEN_QUEUE_BUFFER: 875 { 876 struct video1394_wait v; 877 struct dma_iso_ctx *d; 878 int next_prg; 879 880 if (unlikely(copy_from_user(&v, argp, sizeof(v)))) 881 return -EFAULT; 882 883 d = find_ctx(&ctx->context_list, OHCI_ISO_RECEIVE, v.channel); 884 if (unlikely(d == NULL)) 885 return -EFAULT; 886 887 if (unlikely(v.buffer >= d->num_desc - 1)) { 888 PRINT(KERN_ERR, ohci->host->id, 889 "Buffer %d out of range",v.buffer); 890 return -EINVAL; 891 } 892 893 spin_lock_irqsave(&d->lock,flags); 894 895 if (unlikely(d->buffer_status[v.buffer]==VIDEO1394_BUFFER_QUEUED)) { 896 PRINT(KERN_ERR, ohci->host->id, 897 "Buffer %d is already used",v.buffer); 898 spin_unlock_irqrestore(&d->lock,flags); 899 return -EBUSY; 900 } 901 902 d->buffer_status[v.buffer]=VIDEO1394_BUFFER_QUEUED; 903 904 next_prg = (d->last_buffer + 1) % d->num_desc; 905 if (d->last_buffer>=0) 906 d->ir_prg[d->last_buffer][d->nb_cmd-1].branchAddress = 907 cpu_to_le32((dma_prog_region_offset_to_bus(&d->prg_reg[next_prg], 0) 908 & 0xfffffff0) | 0x1); 909 910 d->last_buffer = next_prg; 911 reprogram_dma_ir_prg(d, d->last_buffer, v.buffer, d->flags); 912 913 d->ir_prg[d->last_buffer][d->nb_cmd-1].branchAddress = 0; 914 915 spin_unlock_irqrestore(&d->lock,flags); 916 917 if (!(reg_read(ohci, d->ctrlSet) & 0x8000)) 918 { 919 DBGMSG(ohci->host->id, "Starting iso DMA ctx=%d",d->ctx); 920 921 /* Tell the controller where the first program is */ 922 reg_write(ohci, d->cmdPtr, 923 dma_prog_region_offset_to_bus(&d->prg_reg[d->last_buffer], 0) | 0x1); 924 925 /* Run IR context */ 926 reg_write(ohci, d->ctrlSet, 0x8000); 927 } 928 else { 929 /* Wake up dma context if necessary */ 930 if (!(reg_read(ohci, d->ctrlSet) & 0x400)) { 931 DBGMSG(ohci->host->id, 932 "Waking up iso dma ctx=%d", d->ctx); 933 reg_write(ohci, d->ctrlSet, 0x1000); 934 } 935 } 936 return 0; 937 938 } 939 case VIDEO1394_IOC_LISTEN_WAIT_BUFFER: 940 case VIDEO1394_IOC_LISTEN_POLL_BUFFER: 941 { 942 struct video1394_wait v; 943 struct dma_iso_ctx *d; 944 int i = 0; 945 946 if (unlikely(copy_from_user(&v, argp, sizeof(v)))) 947 return -EFAULT; 948 949 d = find_ctx(&ctx->context_list, OHCI_ISO_RECEIVE, v.channel); 950 if (unlikely(d == NULL)) 951 return -EFAULT; 952 953 if (unlikely(v.buffer > d->num_desc - 1)) { 954 PRINT(KERN_ERR, ohci->host->id, 955 "Buffer %d out of range",v.buffer); 956 return -EINVAL; 957 } 958 959 /* 960 * I change the way it works so that it returns 961 * the last received frame. 962 */ 963 spin_lock_irqsave(&d->lock, flags); 964 switch(d->buffer_status[v.buffer]) { 965 case VIDEO1394_BUFFER_READY: 966 d->buffer_status[v.buffer]=VIDEO1394_BUFFER_FREE; 967 break; 968 case VIDEO1394_BUFFER_QUEUED: 969 if (cmd == VIDEO1394_IOC_LISTEN_POLL_BUFFER) { 970 /* for polling, return error code EINTR */ 971 spin_unlock_irqrestore(&d->lock, flags); 972 return -EINTR; 973 } 974 975 spin_unlock_irqrestore(&d->lock, flags); 976 wait_event_interruptible(d->waitq, 977 video1394_buffer_state(d, v.buffer) == 978 VIDEO1394_BUFFER_READY); 979 if (signal_pending(current)) 980 return -EINTR; 981 spin_lock_irqsave(&d->lock, flags); 982 d->buffer_status[v.buffer]=VIDEO1394_BUFFER_FREE; 983 break; 984 default: 985 PRINT(KERN_ERR, ohci->host->id, 986 "Buffer %d is not queued",v.buffer); 987 spin_unlock_irqrestore(&d->lock, flags); 988 return -ESRCH; 989 } 990 991 /* set time of buffer */ 992 v.filltime = d->buffer_time[v.buffer]; 993 994 /* 995 * Look ahead to see how many more buffers have been received 996 */ 997 i=0; 998 while (d->buffer_status[(v.buffer+1)%(d->num_desc - 1)]== 999 VIDEO1394_BUFFER_READY) { 1000 v.buffer=(v.buffer+1)%(d->num_desc - 1); 1001 i++; 1002 } 1003 spin_unlock_irqrestore(&d->lock, flags); 1004 1005 v.buffer=i; 1006 if (unlikely(copy_to_user(argp, &v, sizeof(v)))) 1007 return -EFAULT; 1008 1009 return 0; 1010 } 1011 case VIDEO1394_IOC_TALK_QUEUE_BUFFER: 1012 { 1013 struct video1394_wait v; 1014 unsigned int *psizes = NULL; 1015 struct dma_iso_ctx *d; 1016 int next_prg; 1017 1018 if (copy_from_user(&v, argp, sizeof(v))) 1019 return -EFAULT; 1020 1021 d = find_ctx(&ctx->context_list, OHCI_ISO_TRANSMIT, v.channel); 1022 if (d == NULL) return -EFAULT; 1023 1024 if (v.buffer >= d->num_desc - 1) { 1025 PRINT(KERN_ERR, ohci->host->id, 1026 "Buffer %d out of range",v.buffer); 1027 return -EINVAL; 1028 } 1029 1030 if (d->flags & VIDEO1394_VARIABLE_PACKET_SIZE) { 1031 int buf_size = d->nb_cmd * sizeof(*psizes); 1032 struct video1394_queue_variable __user *p = argp; 1033 unsigned int __user *qv; 1034 1035 if (get_user(qv, &p->packet_sizes)) 1036 return -EFAULT; 1037 1038 psizes = memdup_user(qv, buf_size); 1039 if (IS_ERR(psizes)) 1040 return PTR_ERR(psizes); 1041 } 1042 1043 spin_lock_irqsave(&d->lock,flags); 1044 1045 /* last_buffer is last_prg */ 1046 next_prg = (d->last_buffer + 1) % d->num_desc; 1047 if (d->buffer_status[v.buffer]!=VIDEO1394_BUFFER_FREE) { 1048 PRINT(KERN_ERR, ohci->host->id, 1049 "Buffer %d is already used",v.buffer); 1050 spin_unlock_irqrestore(&d->lock,flags); 1051 kfree(psizes); 1052 return -EBUSY; 1053 } 1054 1055 if (d->flags & VIDEO1394_VARIABLE_PACKET_SIZE) { 1056 initialize_dma_it_prg_var_packet_queue( 1057 d, next_prg, psizes, ohci); 1058 } 1059 1060 d->buffer_status[v.buffer]=VIDEO1394_BUFFER_QUEUED; 1061 1062 if (d->last_buffer >= 0) { 1063 d->it_prg[d->last_buffer] 1064 [ d->last_used_cmd[d->last_buffer] ].end.branchAddress = 1065 cpu_to_le32((dma_prog_region_offset_to_bus(&d->prg_reg[next_prg], 1066 0) & 0xfffffff0) | 0x3); 1067 1068 d->it_prg[d->last_buffer] 1069 [ d->last_used_cmd[d->last_buffer] ].begin.branchAddress = 1070 cpu_to_le32((dma_prog_region_offset_to_bus(&d->prg_reg[next_prg], 1071 0) & 0xfffffff0) | 0x3); 1072 d->next_buffer[d->last_buffer] = (v.buffer + 1) % (d->num_desc - 1); 1073 } 1074 d->last_buffer = next_prg; 1075 reprogram_dma_it_prg(d, d->last_buffer, v.buffer); 1076 d->next_buffer[d->last_buffer] = -1; 1077 1078 d->it_prg[d->last_buffer][d->last_used_cmd[d->last_buffer]].end.branchAddress = 0; 1079 1080 spin_unlock_irqrestore(&d->lock,flags); 1081 1082 if (!(reg_read(ohci, d->ctrlSet) & 0x8000)) 1083 { 1084 DBGMSG(ohci->host->id, "Starting iso transmit DMA ctx=%d", 1085 d->ctx); 1086 put_timestamp(ohci, d, d->last_buffer); 1087 dma_region_sync_for_device(&d->dma, 1088 v.buffer * d->buf_size, d->buf_size); 1089 1090 /* Tell the controller where the first program is */ 1091 reg_write(ohci, d->cmdPtr, 1092 dma_prog_region_offset_to_bus(&d->prg_reg[next_prg], 0) | 0x3); 1093 1094 /* Run IT context */ 1095 reg_write(ohci, d->ctrlSet, 0x8000); 1096 } 1097 else { 1098 /* Wake up dma context if necessary */ 1099 if (!(reg_read(ohci, d->ctrlSet) & 0x400)) { 1100 DBGMSG(ohci->host->id, 1101 "Waking up iso transmit dma ctx=%d", 1102 d->ctx); 1103 put_timestamp(ohci, d, d->last_buffer); 1104 dma_region_sync_for_device(&d->dma, 1105 v.buffer * d->buf_size, d->buf_size); 1106 1107 reg_write(ohci, d->ctrlSet, 0x1000); 1108 } 1109 } 1110 1111 kfree(psizes); 1112 return 0; 1113 1114 } 1115 case VIDEO1394_IOC_TALK_WAIT_BUFFER: 1116 { 1117 struct video1394_wait v; 1118 struct dma_iso_ctx *d; 1119 1120 if (copy_from_user(&v, argp, sizeof(v))) 1121 return -EFAULT; 1122 1123 d = find_ctx(&ctx->context_list, OHCI_ISO_TRANSMIT, v.channel); 1124 if (d == NULL) return -EFAULT; 1125 1126 if (v.buffer >= d->num_desc - 1) { 1127 PRINT(KERN_ERR, ohci->host->id, 1128 "Buffer %d out of range",v.buffer); 1129 return -EINVAL; 1130 } 1131 1132 switch(d->buffer_status[v.buffer]) { 1133 case VIDEO1394_BUFFER_READY: 1134 d->buffer_status[v.buffer]=VIDEO1394_BUFFER_FREE; 1135 return 0; 1136 case VIDEO1394_BUFFER_QUEUED: 1137 wait_event_interruptible(d->waitq, 1138 (d->buffer_status[v.buffer] == VIDEO1394_BUFFER_READY)); 1139 if (signal_pending(current)) 1140 return -EINTR; 1141 d->buffer_status[v.buffer]=VIDEO1394_BUFFER_FREE; 1142 return 0; 1143 default: 1144 PRINT(KERN_ERR, ohci->host->id, 1145 "Buffer %d is not queued",v.buffer); 1146 return -ESRCH; 1147 } 1148 } 1149 default: 1150 return -ENOTTY; 1151 } 1152} 1153 1154 1155static int video1394_mmap(struct file *file, struct vm_area_struct *vma) 1156{ 1157 struct file_ctx *ctx = file->private_data; 1158 1159 if (ctx->current_ctx == NULL) { 1160 PRINT(KERN_ERR, ctx->ohci->host->id, 1161 "Current iso context not set"); 1162 return -EINVAL; 1163 } 1164 1165 return dma_region_mmap(&ctx->current_ctx->dma, file, vma); 1166} 1167 1168static unsigned int video1394_poll(struct file *file, poll_table *pt) 1169{ 1170 struct file_ctx *ctx; 1171 unsigned int mask = 0; 1172 unsigned long flags; 1173 struct dma_iso_ctx *d; 1174 int i; 1175 1176 ctx = file->private_data; 1177 d = ctx->current_ctx; 1178 if (d == NULL) { 1179 PRINT(KERN_ERR, ctx->ohci->host->id, 1180 "Current iso context not set"); 1181 return POLLERR; 1182 } 1183 1184 poll_wait(file, &d->waitq, pt); 1185 1186 spin_lock_irqsave(&d->lock, flags); 1187 for (i = 0; i < d->num_desc; i++) { 1188 if (d->buffer_status[i] == VIDEO1394_BUFFER_READY) { 1189 mask |= POLLIN | POLLRDNORM; 1190 break; 1191 } 1192 } 1193 spin_unlock_irqrestore(&d->lock, flags); 1194 1195 return mask; 1196} 1197 1198static int video1394_open(struct inode *inode, struct file *file) 1199{ 1200 int i = ieee1394_file_to_instance(file); 1201 struct ti_ohci *ohci; 1202 struct file_ctx *ctx; 1203 1204 ohci = hpsb_get_hostinfo_bykey(&video1394_highlevel, i); 1205 if (ohci == NULL) 1206 return -EIO; 1207 1208 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 1209 if (!ctx) { 1210 PRINT(KERN_ERR, ohci->host->id, "Cannot malloc file_ctx"); 1211 return -ENOMEM; 1212 } 1213 1214 ctx->ohci = ohci; 1215 INIT_LIST_HEAD(&ctx->context_list); 1216 ctx->current_ctx = NULL; 1217 file->private_data = ctx; 1218 1219 return nonseekable_open(inode, file); 1220} 1221 1222static int video1394_release(struct inode *inode, struct file *file) 1223{ 1224 struct file_ctx *ctx = file->private_data; 1225 struct ti_ohci *ohci = ctx->ohci; 1226 struct list_head *lh, *next; 1227 u64 mask; 1228 1229 list_for_each_safe(lh, next, &ctx->context_list) { 1230 struct dma_iso_ctx *d; 1231 d = list_entry(lh, struct dma_iso_ctx, link); 1232 mask = (u64) 1 << d->channel; 1233 1234 if (!(ohci->ISO_channel_usage & mask)) 1235 PRINT(KERN_ERR, ohci->host->id, "On release: Channel %d " 1236 "is not being used", d->channel); 1237 else 1238 ohci->ISO_channel_usage &= ~mask; 1239 DBGMSG(ohci->host->id, "On release: Iso %s context " 1240 "%d stop listening on channel %d", 1241 d->type == OHCI_ISO_RECEIVE ? "receive" : "transmit", 1242 d->ctx, d->channel); 1243 free_dma_iso_ctx(d); 1244 } 1245 1246 kfree(ctx); 1247 file->private_data = NULL; 1248 1249 return 0; 1250} 1251 1252#ifdef CONFIG_COMPAT 1253static long video1394_compat_ioctl(struct file *f, unsigned cmd, unsigned long arg); 1254#endif 1255 1256static struct cdev video1394_cdev; 1257static const struct file_operations video1394_fops= 1258{ 1259 .owner = THIS_MODULE, 1260 .unlocked_ioctl = video1394_ioctl, 1261#ifdef CONFIG_COMPAT 1262 .compat_ioctl = video1394_compat_ioctl, 1263#endif 1264 .poll = video1394_poll, 1265 .mmap = video1394_mmap, 1266 .open = video1394_open, 1267 .release = video1394_release, 1268 .llseek = no_llseek, 1269}; 1270 1271/*** HOTPLUG STUFF **********************************************************/ 1272/* 1273 * Export information about protocols/devices supported by this driver. 1274 */ 1275#ifdef MODULE 1276static const struct ieee1394_device_id video1394_id_table[] = { 1277 { 1278 .match_flags = IEEE1394_MATCH_SPECIFIER_ID | IEEE1394_MATCH_VERSION, 1279 .specifier_id = CAMERA_UNIT_SPEC_ID_ENTRY & 0xffffff, 1280 .version = CAMERA_SW_VERSION_ENTRY & 0xffffff 1281 }, 1282 { 1283 .match_flags = IEEE1394_MATCH_SPECIFIER_ID | IEEE1394_MATCH_VERSION, 1284 .specifier_id = CAMERA_UNIT_SPEC_ID_ENTRY & 0xffffff, 1285 .version = (CAMERA_SW_VERSION_ENTRY + 1) & 0xffffff 1286 }, 1287 { 1288 .match_flags = IEEE1394_MATCH_SPECIFIER_ID | IEEE1394_MATCH_VERSION, 1289 .specifier_id = CAMERA_UNIT_SPEC_ID_ENTRY & 0xffffff, 1290 .version = (CAMERA_SW_VERSION_ENTRY + 2) & 0xffffff 1291 }, 1292 { } 1293}; 1294 1295MODULE_DEVICE_TABLE(ieee1394, video1394_id_table); 1296#endif /* MODULE */ 1297 1298static struct hpsb_protocol_driver video1394_driver = { 1299 .name = VIDEO1394_DRIVER_NAME, 1300}; 1301 1302 1303static void video1394_add_host (struct hpsb_host *host) 1304{ 1305 struct ti_ohci *ohci; 1306 int minor; 1307 1308 /* We only work with the OHCI-1394 driver */ 1309 if (strcmp(host->driver->name, OHCI1394_DRIVER_NAME)) 1310 return; 1311 1312 ohci = (struct ti_ohci *)host->hostdata; 1313 1314 if (!hpsb_create_hostinfo(&video1394_highlevel, host, 0)) { 1315 PRINT(KERN_ERR, ohci->host->id, "Cannot allocate hostinfo"); 1316 return; 1317 } 1318 1319 hpsb_set_hostinfo(&video1394_highlevel, host, ohci); 1320 hpsb_set_hostinfo_key(&video1394_highlevel, host, ohci->host->id); 1321 1322 minor = IEEE1394_MINOR_BLOCK_VIDEO1394 * 16 + ohci->host->id; 1323 device_create(hpsb_protocol_class, NULL, MKDEV(IEEE1394_MAJOR, minor), 1324 NULL, "%s-%d", VIDEO1394_DRIVER_NAME, ohci->host->id); 1325} 1326 1327 1328static void video1394_remove_host (struct hpsb_host *host) 1329{ 1330 struct ti_ohci *ohci = hpsb_get_hostinfo(&video1394_highlevel, host); 1331 1332 if (ohci) 1333 device_destroy(hpsb_protocol_class, MKDEV(IEEE1394_MAJOR, 1334 IEEE1394_MINOR_BLOCK_VIDEO1394 * 16 + ohci->host->id)); 1335 return; 1336} 1337 1338 1339static struct hpsb_highlevel video1394_highlevel = { 1340 .name = VIDEO1394_DRIVER_NAME, 1341 .add_host = video1394_add_host, 1342 .remove_host = video1394_remove_host, 1343}; 1344 1345MODULE_AUTHOR("Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>"); 1346MODULE_DESCRIPTION("driver for digital video on OHCI board"); 1347MODULE_SUPPORTED_DEVICE(VIDEO1394_DRIVER_NAME); 1348MODULE_LICENSE("GPL"); 1349 1350#ifdef CONFIG_COMPAT 1351 1352#define VIDEO1394_IOC32_LISTEN_QUEUE_BUFFER \ 1353 _IOW ('#', 0x12, struct video1394_wait32) 1354#define VIDEO1394_IOC32_LISTEN_WAIT_BUFFER \ 1355 _IOWR('#', 0x13, struct video1394_wait32) 1356#define VIDEO1394_IOC32_TALK_WAIT_BUFFER \ 1357 _IOW ('#', 0x17, struct video1394_wait32) 1358#define VIDEO1394_IOC32_LISTEN_POLL_BUFFER \ 1359 _IOWR('#', 0x18, struct video1394_wait32) 1360 1361struct video1394_wait32 { 1362 u32 channel; 1363 u32 buffer; 1364 struct compat_timeval filltime; 1365}; 1366 1367static int video1394_wr_wait32(struct file *file, unsigned int cmd, unsigned long arg) 1368{ 1369 struct video1394_wait32 __user *argp = (void __user *)arg; 1370 struct video1394_wait32 wait32; 1371 struct video1394_wait wait; 1372 mm_segment_t old_fs; 1373 int ret; 1374 1375 if (copy_from_user(&wait32, argp, sizeof(wait32))) 1376 return -EFAULT; 1377 1378 wait.channel = wait32.channel; 1379 wait.buffer = wait32.buffer; 1380 wait.filltime.tv_sec = (time_t)wait32.filltime.tv_sec; 1381 wait.filltime.tv_usec = (suseconds_t)wait32.filltime.tv_usec; 1382 1383 old_fs = get_fs(); 1384 set_fs(KERNEL_DS); 1385 if (cmd == VIDEO1394_IOC32_LISTEN_WAIT_BUFFER) 1386 ret = video1394_ioctl(file, 1387 VIDEO1394_IOC_LISTEN_WAIT_BUFFER, 1388 (unsigned long) &wait); 1389 else 1390 ret = video1394_ioctl(file, 1391 VIDEO1394_IOC_LISTEN_POLL_BUFFER, 1392 (unsigned long) &wait); 1393 set_fs(old_fs); 1394 1395 if (!ret) { 1396 wait32.channel = wait.channel; 1397 wait32.buffer = wait.buffer; 1398 wait32.filltime.tv_sec = (int)wait.filltime.tv_sec; 1399 wait32.filltime.tv_usec = (int)wait.filltime.tv_usec; 1400 1401 if (copy_to_user(argp, &wait32, sizeof(wait32))) 1402 ret = -EFAULT; 1403 } 1404 1405 return ret; 1406} 1407 1408static int video1394_w_wait32(struct file *file, unsigned int cmd, unsigned long arg) 1409{ 1410 struct video1394_wait32 wait32; 1411 struct video1394_wait wait; 1412 mm_segment_t old_fs; 1413 int ret; 1414 1415 if (copy_from_user(&wait32, (void __user *)arg, sizeof(wait32))) 1416 return -EFAULT; 1417 1418 wait.channel = wait32.channel; 1419 wait.buffer = wait32.buffer; 1420 wait.filltime.tv_sec = (time_t)wait32.filltime.tv_sec; 1421 wait.filltime.tv_usec = (suseconds_t)wait32.filltime.tv_usec; 1422 1423 old_fs = get_fs(); 1424 set_fs(KERNEL_DS); 1425 if (cmd == VIDEO1394_IOC32_LISTEN_QUEUE_BUFFER) 1426 ret = video1394_ioctl(file, 1427 VIDEO1394_IOC_LISTEN_QUEUE_BUFFER, 1428 (unsigned long) &wait); 1429 else 1430 ret = video1394_ioctl(file, 1431 VIDEO1394_IOC_TALK_WAIT_BUFFER, 1432 (unsigned long) &wait); 1433 set_fs(old_fs); 1434 1435 return ret; 1436} 1437 1438static int video1394_queue_buf32(struct file *file, unsigned int cmd, unsigned long arg) 1439{ 1440 return -EFAULT; /* ??? was there before. */ 1441 1442 return video1394_ioctl(file, 1443 VIDEO1394_IOC_TALK_QUEUE_BUFFER, arg); 1444} 1445 1446static long video1394_compat_ioctl(struct file *f, unsigned cmd, unsigned long arg) 1447{ 1448 switch (cmd) { 1449 case VIDEO1394_IOC_LISTEN_CHANNEL: 1450 case VIDEO1394_IOC_UNLISTEN_CHANNEL: 1451 case VIDEO1394_IOC_TALK_CHANNEL: 1452 case VIDEO1394_IOC_UNTALK_CHANNEL: 1453 return video1394_ioctl(f, cmd, arg); 1454 1455 case VIDEO1394_IOC32_LISTEN_QUEUE_BUFFER: 1456 return video1394_w_wait32(f, cmd, arg); 1457 case VIDEO1394_IOC32_LISTEN_WAIT_BUFFER: 1458 return video1394_wr_wait32(f, cmd, arg); 1459 case VIDEO1394_IOC_TALK_QUEUE_BUFFER: 1460 return video1394_queue_buf32(f, cmd, arg); 1461 case VIDEO1394_IOC32_TALK_WAIT_BUFFER: 1462 return video1394_w_wait32(f, cmd, arg); 1463 case VIDEO1394_IOC32_LISTEN_POLL_BUFFER: 1464 return video1394_wr_wait32(f, cmd, arg); 1465 default: 1466 return -ENOIOCTLCMD; 1467 } 1468} 1469 1470#endif /* CONFIG_COMPAT */ 1471 1472static void __exit video1394_exit_module (void) 1473{ 1474 hpsb_unregister_protocol(&video1394_driver); 1475 hpsb_unregister_highlevel(&video1394_highlevel); 1476 cdev_del(&video1394_cdev); 1477 PRINT_G(KERN_INFO, "Removed " VIDEO1394_DRIVER_NAME " module"); 1478} 1479 1480static int __init video1394_init_module (void) 1481{ 1482 int ret; 1483 1484 hpsb_init_highlevel(&video1394_highlevel); 1485 1486 cdev_init(&video1394_cdev, &video1394_fops); 1487 video1394_cdev.owner = THIS_MODULE; 1488 ret = cdev_add(&video1394_cdev, IEEE1394_VIDEO1394_DEV, 16); 1489 if (ret) { 1490 PRINT_G(KERN_ERR, "video1394: unable to get minor device block"); 1491 return ret; 1492 } 1493 1494 hpsb_register_highlevel(&video1394_highlevel); 1495 1496 ret = hpsb_register_protocol(&video1394_driver); 1497 if (ret) { 1498 PRINT_G(KERN_ERR, "video1394: failed to register protocol"); 1499 hpsb_unregister_highlevel(&video1394_highlevel); 1500 cdev_del(&video1394_cdev); 1501 return ret; 1502 } 1503 1504 PRINT_G(KERN_INFO, "Installed " VIDEO1394_DRIVER_NAME " module"); 1505 return 0; 1506} 1507 1508 1509module_init(video1394_init_module); 1510module_exit(video1394_exit_module); 1511