1/* 2 * IEEE 1394 for Linux 3 * 4 * CSR implementation, iso/bus manager implementation. 5 * 6 * Copyright (C) 1999 Andreas E. Bombe 7 * 2002 Manfred Weihs <weihs@ict.tuwien.ac.at> 8 * 9 * This code is licensed under the GPL. See the file COPYING in the root 10 * directory of the kernel sources for details. 11 * 12 * 13 * Contributions: 14 * 15 * Manfred Weihs <weihs@ict.tuwien.ac.at> 16 * configuration ROM manipulation 17 * 18 */ 19 20#include <linux/jiffies.h> 21#include <linux/kernel.h> 22#include <linux/module.h> 23#include <linux/moduleparam.h> 24#include <linux/param.h> 25#include <linux/spinlock.h> 26#include <linux/string.h> 27 28#include "csr1212.h" 29#include "ieee1394_types.h" 30#include "hosts.h" 31#include "ieee1394.h" 32#include "highlevel.h" 33#include "ieee1394_core.h" 34 35/* Module Parameters */ 36/* this module parameter can be used to disable mapping of the FCP registers */ 37 38static int fcp = 1; 39module_param(fcp, int, 0444); 40MODULE_PARM_DESC(fcp, "Map FCP registers (default = 1, disable = 0)."); 41 42static struct csr1212_keyval *node_cap = NULL; 43 44static void add_host(struct hpsb_host *host); 45static void remove_host(struct hpsb_host *host); 46static void host_reset(struct hpsb_host *host); 47static int read_maps(struct hpsb_host *host, int nodeid, quadlet_t *buffer, 48 u64 addr, size_t length, u16 fl); 49static int write_fcp(struct hpsb_host *host, int nodeid, int dest, 50 quadlet_t *data, u64 addr, size_t length, u16 flags); 51static int read_regs(struct hpsb_host *host, int nodeid, quadlet_t *buf, 52 u64 addr, size_t length, u16 flags); 53static int write_regs(struct hpsb_host *host, int nodeid, int destid, 54 quadlet_t *data, u64 addr, size_t length, u16 flags); 55static int lock_regs(struct hpsb_host *host, int nodeid, quadlet_t *store, 56 u64 addr, quadlet_t data, quadlet_t arg, int extcode, u16 fl); 57static int lock64_regs(struct hpsb_host *host, int nodeid, octlet_t * store, 58 u64 addr, octlet_t data, octlet_t arg, int extcode, u16 fl); 59static int read_config_rom(struct hpsb_host *host, int nodeid, quadlet_t *buffer, 60 u64 addr, size_t length, u16 fl); 61static u64 allocate_addr_range(u64 size, u32 alignment, void *__host); 62static void release_addr_range(u64 addr, void *__host); 63 64static struct hpsb_highlevel csr_highlevel = { 65 .name = "standard registers", 66 .add_host = add_host, 67 .remove_host = remove_host, 68 .host_reset = host_reset, 69}; 70 71static const struct hpsb_address_ops map_ops = { 72 .read = read_maps, 73}; 74 75static const struct hpsb_address_ops fcp_ops = { 76 .write = write_fcp, 77}; 78 79static const struct hpsb_address_ops reg_ops = { 80 .read = read_regs, 81 .write = write_regs, 82 .lock = lock_regs, 83 .lock64 = lock64_regs, 84}; 85 86static const struct hpsb_address_ops config_rom_ops = { 87 .read = read_config_rom, 88}; 89 90struct csr1212_bus_ops csr_bus_ops = { 91 .allocate_addr_range = allocate_addr_range, 92 .release_addr = release_addr_range, 93}; 94 95 96static u16 csr_crc16(unsigned *data, int length) 97{ 98 int check=0, i; 99 int shift, sum, next=0; 100 101 for (i = length; i; i--) { 102 for (next = check, shift = 28; shift >= 0; shift -= 4 ) { 103 sum = ((next >> 12) ^ (be32_to_cpu(*data) >> shift)) & 0xf; 104 next = (next << 4) ^ (sum << 12) ^ (sum << 5) ^ (sum); 105 } 106 check = next & 0xffff; 107 data++; 108 } 109 110 return check; 111} 112 113static void host_reset(struct hpsb_host *host) 114{ 115 host->csr.state &= 0x300; 116 117 host->csr.bus_manager_id = 0x3f; 118 host->csr.bandwidth_available = 4915; 119 host->csr.channels_available_hi = 0xfffffffe; /* pre-alloc ch 31 per 1394a-2000 */ 120 host->csr.channels_available_lo = ~0; 121 host->csr.broadcast_channel = 0x80000000 | 31; 122 123 if (host->is_irm) { 124 if (host->driver->hw_csr_reg) { 125 host->driver->hw_csr_reg(host, 2, 0xfffffffe, ~0); 126 } 127 } 128 129 host->csr.node_ids = host->node_id << 16; 130 131 if (!host->is_root) { 132 /* clear cmstr bit */ 133 host->csr.state &= ~0x100; 134 } 135 136 be32_add_cpu(&host->csr.topology_map[1], 1); 137 host->csr.topology_map[2] = cpu_to_be32(host->node_count << 16 138 | host->selfid_count); 139 host->csr.topology_map[0] = 140 cpu_to_be32((host->selfid_count + 2) << 16 141 | csr_crc16(host->csr.topology_map + 1, 142 host->selfid_count + 2)); 143 144 be32_add_cpu(&host->csr.speed_map[1], 1); 145 host->csr.speed_map[0] = cpu_to_be32(0x3f1 << 16 146 | csr_crc16(host->csr.speed_map+1, 147 0x3f1)); 148} 149 150/* 151 * HI == seconds (bits 0:2) 152 * LO == fractions of a second in units of 125usec (bits 19:31) 153 * 154 * Convert SPLIT_TIMEOUT to jiffies. 155 * The default and minimum as per 1394a-2000 clause 8.3.2.2.6 is 100ms. 156 */ 157static inline void calculate_expire(struct csr_control *csr) 158{ 159 unsigned int usecs = (csr->split_timeout_hi & 7) * 1000000 + 160 (csr->split_timeout_lo >> 19) * 125; 161 162 csr->expire = usecs_to_jiffies(usecs > 100000 ? usecs : 100000); 163 HPSB_VERBOSE("CSR: setting expire to %lu, HZ=%u", csr->expire, HZ); 164} 165 166 167static void add_host(struct hpsb_host *host) 168{ 169 struct csr1212_keyval *root; 170 quadlet_t bus_info[CSR_BUS_INFO_SIZE]; 171 172 hpsb_register_addrspace(&csr_highlevel, host, ®_ops, 173 CSR_REGISTER_BASE, 174 CSR_REGISTER_BASE + CSR_CONFIG_ROM); 175 hpsb_register_addrspace(&csr_highlevel, host, &config_rom_ops, 176 CSR_REGISTER_BASE + CSR_CONFIG_ROM, 177 CSR_REGISTER_BASE + CSR_CONFIG_ROM_END); 178 if (fcp) { 179 hpsb_register_addrspace(&csr_highlevel, host, &fcp_ops, 180 CSR_REGISTER_BASE + CSR_FCP_COMMAND, 181 CSR_REGISTER_BASE + CSR_FCP_END); 182 } 183 hpsb_register_addrspace(&csr_highlevel, host, &map_ops, 184 CSR_REGISTER_BASE + CSR_TOPOLOGY_MAP, 185 CSR_REGISTER_BASE + CSR_TOPOLOGY_MAP_END); 186 hpsb_register_addrspace(&csr_highlevel, host, &map_ops, 187 CSR_REGISTER_BASE + CSR_SPEED_MAP, 188 CSR_REGISTER_BASE + CSR_SPEED_MAP_END); 189 190 spin_lock_init(&host->csr.lock); 191 192 host->csr.state = 0; 193 host->csr.node_ids = 0; 194 host->csr.split_timeout_hi = 0; 195 host->csr.split_timeout_lo = 800 << 19; 196 calculate_expire(&host->csr); 197 host->csr.cycle_time = 0; 198 host->csr.bus_time = 0; 199 host->csr.bus_manager_id = 0x3f; 200 host->csr.bandwidth_available = 4915; 201 host->csr.channels_available_hi = 0xfffffffe; /* pre-alloc ch 31 per 1394a-2000 */ 202 host->csr.channels_available_lo = ~0; 203 host->csr.broadcast_channel = 0x80000000 | 31; 204 205 if (host->is_irm) { 206 if (host->driver->hw_csr_reg) { 207 host->driver->hw_csr_reg(host, 2, 0xfffffffe, ~0); 208 } 209 } 210 211 if (host->csr.max_rec >= 9) 212 host->csr.max_rom = 2; 213 else if (host->csr.max_rec >= 5) 214 host->csr.max_rom = 1; 215 else 216 host->csr.max_rom = 0; 217 218 host->csr.generation = 2; 219 220 bus_info[1] = IEEE1394_BUSID_MAGIC; 221 bus_info[2] = cpu_to_be32((hpsb_disable_irm ? 0 : 1 << CSR_IRMC_SHIFT) | 222 (1 << CSR_CMC_SHIFT) | 223 (1 << CSR_ISC_SHIFT) | 224 (0 << CSR_BMC_SHIFT) | 225 (0 << CSR_PMC_SHIFT) | 226 (host->csr.cyc_clk_acc << CSR_CYC_CLK_ACC_SHIFT) | 227 (host->csr.max_rec << CSR_MAX_REC_SHIFT) | 228 (host->csr.max_rom << CSR_MAX_ROM_SHIFT) | 229 (host->csr.generation << CSR_GENERATION_SHIFT) | 230 host->csr.lnk_spd); 231 232 bus_info[3] = cpu_to_be32(host->csr.guid_hi); 233 bus_info[4] = cpu_to_be32(host->csr.guid_lo); 234 235 /* The hardware copy of the bus info block will be set later when a 236 * bus reset is issued. */ 237 238 csr1212_init_local_csr(host->csr.rom, bus_info, host->csr.max_rom); 239 240 root = host->csr.rom->root_kv; 241 242 if(csr1212_attach_keyval_to_directory(root, node_cap) != CSR1212_SUCCESS) { 243 HPSB_ERR("Failed to attach Node Capabilities to root directory"); 244 } 245 246 host->update_config_rom = 1; 247} 248 249static void remove_host(struct hpsb_host *host) 250{ 251 quadlet_t bus_info[CSR_BUS_INFO_SIZE]; 252 253 bus_info[1] = IEEE1394_BUSID_MAGIC; 254 bus_info[2] = cpu_to_be32((0 << CSR_IRMC_SHIFT) | 255 (0 << CSR_CMC_SHIFT) | 256 (0 << CSR_ISC_SHIFT) | 257 (0 << CSR_BMC_SHIFT) | 258 (0 << CSR_PMC_SHIFT) | 259 (host->csr.cyc_clk_acc << CSR_CYC_CLK_ACC_SHIFT) | 260 (host->csr.max_rec << CSR_MAX_REC_SHIFT) | 261 (0 << CSR_MAX_ROM_SHIFT) | 262 (0 << CSR_GENERATION_SHIFT) | 263 host->csr.lnk_spd); 264 265 bus_info[3] = cpu_to_be32(host->csr.guid_hi); 266 bus_info[4] = cpu_to_be32(host->csr.guid_lo); 267 268 csr1212_detach_keyval_from_directory(host->csr.rom->root_kv, node_cap); 269 270 csr1212_init_local_csr(host->csr.rom, bus_info, 0); 271 host->update_config_rom = 1; 272} 273 274 275int hpsb_update_config_rom(struct hpsb_host *host, const quadlet_t *new_rom, 276 size_t buffersize, unsigned char rom_version) 277{ 278 unsigned long flags; 279 int ret; 280 281 HPSB_NOTICE("hpsb_update_config_rom() is deprecated"); 282 283 spin_lock_irqsave(&host->csr.lock, flags); 284 if (rom_version != host->csr.generation) 285 ret = -1; 286 else if (buffersize > host->csr.rom->cache_head->size) 287 ret = -2; 288 else { 289 /* Just overwrite the generated ConfigROM image with new data, 290 * it can be regenerated later. */ 291 memcpy(host->csr.rom->cache_head->data, new_rom, buffersize); 292 host->csr.rom->cache_head->len = buffersize; 293 294 if (host->driver->set_hw_config_rom) 295 host->driver->set_hw_config_rom(host, host->csr.rom->bus_info_data); 296 /* Increment the generation number to keep some sort of sync 297 * with the newer ConfigROM manipulation method. */ 298 host->csr.generation++; 299 if (host->csr.generation > 0xf || host->csr.generation < 2) 300 host->csr.generation = 2; 301 ret=0; 302 } 303 spin_unlock_irqrestore(&host->csr.lock, flags); 304 return ret; 305} 306 307 308/* Read topology / speed maps and configuration ROM */ 309static int read_maps(struct hpsb_host *host, int nodeid, quadlet_t *buffer, 310 u64 addr, size_t length, u16 fl) 311{ 312 unsigned long flags; 313 int csraddr = addr - CSR_REGISTER_BASE; 314 const char *src; 315 316 spin_lock_irqsave(&host->csr.lock, flags); 317 318 if (csraddr < CSR_SPEED_MAP) { 319 src = ((char *)host->csr.topology_map) + csraddr 320 - CSR_TOPOLOGY_MAP; 321 } else { 322 src = ((char *)host->csr.speed_map) + csraddr - CSR_SPEED_MAP; 323 } 324 325 memcpy(buffer, src, length); 326 spin_unlock_irqrestore(&host->csr.lock, flags); 327 return RCODE_COMPLETE; 328} 329 330 331#define out if (--length == 0) break 332 333static int read_regs(struct hpsb_host *host, int nodeid, quadlet_t *buf, 334 u64 addr, size_t length, u16 flags) 335{ 336 int csraddr = addr - CSR_REGISTER_BASE; 337 int oldcycle; 338 quadlet_t ret; 339 340 if ((csraddr | length) & 0x3) 341 return RCODE_TYPE_ERROR; 342 343 length /= 4; 344 345 switch (csraddr) { 346 case CSR_STATE_CLEAR: 347 *(buf++) = cpu_to_be32(host->csr.state); 348 out; 349 case CSR_STATE_SET: 350 *(buf++) = cpu_to_be32(host->csr.state); 351 out; 352 case CSR_NODE_IDS: 353 *(buf++) = cpu_to_be32(host->csr.node_ids); 354 out; 355 356 case CSR_RESET_START: 357 return RCODE_TYPE_ERROR; 358 359 /* address gap - handled by default below */ 360 361 case CSR_SPLIT_TIMEOUT_HI: 362 *(buf++) = cpu_to_be32(host->csr.split_timeout_hi); 363 out; 364 case CSR_SPLIT_TIMEOUT_LO: 365 *(buf++) = cpu_to_be32(host->csr.split_timeout_lo); 366 out; 367 368 /* address gap */ 369 return RCODE_ADDRESS_ERROR; 370 371 case CSR_CYCLE_TIME: 372 oldcycle = host->csr.cycle_time; 373 host->csr.cycle_time = 374 host->driver->devctl(host, GET_CYCLE_COUNTER, 0); 375 376 if (oldcycle > host->csr.cycle_time) { 377 /* cycle time wrapped around */ 378 host->csr.bus_time += 1 << 7; 379 } 380 *(buf++) = cpu_to_be32(host->csr.cycle_time); 381 out; 382 case CSR_BUS_TIME: 383 oldcycle = host->csr.cycle_time; 384 host->csr.cycle_time = 385 host->driver->devctl(host, GET_CYCLE_COUNTER, 0); 386 387 if (oldcycle > host->csr.cycle_time) { 388 /* cycle time wrapped around */ 389 host->csr.bus_time += (1 << 7); 390 } 391 *(buf++) = cpu_to_be32(host->csr.bus_time 392 | (host->csr.cycle_time >> 25)); 393 out; 394 395 /* address gap */ 396 return RCODE_ADDRESS_ERROR; 397 398 case CSR_BUSY_TIMEOUT: 399 /* not yet implemented */ 400 return RCODE_ADDRESS_ERROR; 401 402 case CSR_BUS_MANAGER_ID: 403 if (host->driver->hw_csr_reg) 404 ret = host->driver->hw_csr_reg(host, 0, 0, 0); 405 else 406 ret = host->csr.bus_manager_id; 407 408 *(buf++) = cpu_to_be32(ret); 409 out; 410 case CSR_BANDWIDTH_AVAILABLE: 411 if (host->driver->hw_csr_reg) 412 ret = host->driver->hw_csr_reg(host, 1, 0, 0); 413 else 414 ret = host->csr.bandwidth_available; 415 416 *(buf++) = cpu_to_be32(ret); 417 out; 418 case CSR_CHANNELS_AVAILABLE_HI: 419 if (host->driver->hw_csr_reg) 420 ret = host->driver->hw_csr_reg(host, 2, 0, 0); 421 else 422 ret = host->csr.channels_available_hi; 423 424 *(buf++) = cpu_to_be32(ret); 425 out; 426 case CSR_CHANNELS_AVAILABLE_LO: 427 if (host->driver->hw_csr_reg) 428 ret = host->driver->hw_csr_reg(host, 3, 0, 0); 429 else 430 ret = host->csr.channels_available_lo; 431 432 *(buf++) = cpu_to_be32(ret); 433 out; 434 435 case CSR_BROADCAST_CHANNEL: 436 *(buf++) = cpu_to_be32(host->csr.broadcast_channel); 437 out; 438 439 /* address gap to end - fall through to default */ 440 default: 441 return RCODE_ADDRESS_ERROR; 442 } 443 444 return RCODE_COMPLETE; 445} 446 447static int write_regs(struct hpsb_host *host, int nodeid, int destid, 448 quadlet_t *data, u64 addr, size_t length, u16 flags) 449{ 450 int csraddr = addr - CSR_REGISTER_BASE; 451 452 if ((csraddr | length) & 0x3) 453 return RCODE_TYPE_ERROR; 454 455 length /= 4; 456 457 switch (csraddr) { 458 case CSR_STATE_CLEAR: 459 printk("doh, someone wants to mess with state clear\n"); 460 out; 461 case CSR_STATE_SET: 462 printk("doh, someone wants to mess with state set\n"); 463 out; 464 465 case CSR_NODE_IDS: 466 host->csr.node_ids &= NODE_MASK << 16; 467 host->csr.node_ids |= be32_to_cpu(*(data++)) & (BUS_MASK << 16); 468 host->node_id = host->csr.node_ids >> 16; 469 host->driver->devctl(host, SET_BUS_ID, host->node_id >> 6); 470 out; 471 472 case CSR_RESET_START: 473 out; 474 475 /* address gap */ 476 return RCODE_ADDRESS_ERROR; 477 478 case CSR_SPLIT_TIMEOUT_HI: 479 host->csr.split_timeout_hi = 480 be32_to_cpu(*(data++)) & 0x00000007; 481 calculate_expire(&host->csr); 482 out; 483 case CSR_SPLIT_TIMEOUT_LO: 484 host->csr.split_timeout_lo = 485 be32_to_cpu(*(data++)) & 0xfff80000; 486 calculate_expire(&host->csr); 487 out; 488 489 /* address gap */ 490 return RCODE_ADDRESS_ERROR; 491 492 case CSR_CYCLE_TIME: 493 /* should only be set by cycle start packet, automatically */ 494 host->csr.cycle_time = be32_to_cpu(*data); 495 host->driver->devctl(host, SET_CYCLE_COUNTER, 496 be32_to_cpu(*(data++))); 497 out; 498 case CSR_BUS_TIME: 499 host->csr.bus_time = be32_to_cpu(*(data++)) & 0xffffff80; 500 out; 501 502 /* address gap */ 503 return RCODE_ADDRESS_ERROR; 504 505 case CSR_BUSY_TIMEOUT: 506 /* not yet implemented */ 507 return RCODE_ADDRESS_ERROR; 508 509 case CSR_BUS_MANAGER_ID: 510 case CSR_BANDWIDTH_AVAILABLE: 511 case CSR_CHANNELS_AVAILABLE_HI: 512 case CSR_CHANNELS_AVAILABLE_LO: 513 /* these are not writable, only lockable */ 514 return RCODE_TYPE_ERROR; 515 516 case CSR_BROADCAST_CHANNEL: 517 /* only the valid bit can be written */ 518 host->csr.broadcast_channel = (host->csr.broadcast_channel & ~0x40000000) 519 | (be32_to_cpu(*data) & 0x40000000); 520 out; 521 522 /* address gap to end - fall through */ 523 default: 524 return RCODE_ADDRESS_ERROR; 525 } 526 527 return RCODE_COMPLETE; 528} 529 530#undef out 531 532 533static int lock_regs(struct hpsb_host *host, int nodeid, quadlet_t *store, 534 u64 addr, quadlet_t data, quadlet_t arg, int extcode, u16 fl) 535{ 536 int csraddr = addr - CSR_REGISTER_BASE; 537 unsigned long flags; 538 quadlet_t *regptr = NULL; 539 540 if (csraddr & 0x3) 541 return RCODE_TYPE_ERROR; 542 543 if (csraddr < CSR_BUS_MANAGER_ID || csraddr > CSR_CHANNELS_AVAILABLE_LO 544 || extcode != EXTCODE_COMPARE_SWAP) 545 goto unsupported_lockreq; 546 547 data = be32_to_cpu(data); 548 arg = be32_to_cpu(arg); 549 550 /* Is somebody releasing the broadcast_channel on us? */ 551 if (csraddr == CSR_CHANNELS_AVAILABLE_HI && (data & 0x1)) { 552 /* Note: this is may not be the right way to handle 553 * the problem, so we should look into the proper way 554 * eventually. */ 555 HPSB_WARN("Node [" NODE_BUS_FMT "] wants to release " 556 "broadcast channel 31. Ignoring.", 557 NODE_BUS_ARGS(host, nodeid)); 558 559 data &= ~0x1; /* keep broadcast channel allocated */ 560 } 561 562 if (host->driver->hw_csr_reg) { 563 quadlet_t old; 564 565 old = host->driver-> 566 hw_csr_reg(host, (csraddr - CSR_BUS_MANAGER_ID) >> 2, 567 data, arg); 568 569 *store = cpu_to_be32(old); 570 return RCODE_COMPLETE; 571 } 572 573 spin_lock_irqsave(&host->csr.lock, flags); 574 575 switch (csraddr) { 576 case CSR_BUS_MANAGER_ID: 577 regptr = &host->csr.bus_manager_id; 578 *store = cpu_to_be32(*regptr); 579 if (*regptr == arg) 580 *regptr = data; 581 break; 582 583 case CSR_BANDWIDTH_AVAILABLE: 584 { 585 quadlet_t bandwidth; 586 quadlet_t old; 587 quadlet_t new; 588 589 regptr = &host->csr.bandwidth_available; 590 old = *regptr; 591 592 /* bandwidth available algorithm adapted from IEEE 1394a-2000 spec */ 593 if (arg > 0x1fff) { 594 *store = cpu_to_be32(old); /* change nothing */ 595 break; 596 } 597 data &= 0x1fff; 598 if (arg >= data) { 599 /* allocate bandwidth */ 600 bandwidth = arg - data; 601 if (old >= bandwidth) { 602 new = old - bandwidth; 603 *store = cpu_to_be32(arg); 604 *regptr = new; 605 } else { 606 *store = cpu_to_be32(old); 607 } 608 } else { 609 /* deallocate bandwidth */ 610 bandwidth = data - arg; 611 if (old + bandwidth < 0x2000) { 612 new = old + bandwidth; 613 *store = cpu_to_be32(arg); 614 *regptr = new; 615 } else { 616 *store = cpu_to_be32(old); 617 } 618 } 619 break; 620 } 621 622 case CSR_CHANNELS_AVAILABLE_HI: 623 { 624 /* Lock algorithm for CHANNELS_AVAILABLE as recommended by 1394a-2000 */ 625 quadlet_t affected_channels = arg ^ data; 626 627 regptr = &host->csr.channels_available_hi; 628 629 if ((arg & affected_channels) == (*regptr & affected_channels)) { 630 *regptr ^= affected_channels; 631 *store = cpu_to_be32(arg); 632 } else { 633 *store = cpu_to_be32(*regptr); 634 } 635 636 break; 637 } 638 639 case CSR_CHANNELS_AVAILABLE_LO: 640 { 641 /* Lock algorithm for CHANNELS_AVAILABLE as recommended by 1394a-2000 */ 642 quadlet_t affected_channels = arg ^ data; 643 644 regptr = &host->csr.channels_available_lo; 645 646 if ((arg & affected_channels) == (*regptr & affected_channels)) { 647 *regptr ^= affected_channels; 648 *store = cpu_to_be32(arg); 649 } else { 650 *store = cpu_to_be32(*regptr); 651 } 652 break; 653 } 654 } 655 656 spin_unlock_irqrestore(&host->csr.lock, flags); 657 658 return RCODE_COMPLETE; 659 660 unsupported_lockreq: 661 switch (csraddr) { 662 case CSR_STATE_CLEAR: 663 case CSR_STATE_SET: 664 case CSR_RESET_START: 665 case CSR_NODE_IDS: 666 case CSR_SPLIT_TIMEOUT_HI: 667 case CSR_SPLIT_TIMEOUT_LO: 668 case CSR_CYCLE_TIME: 669 case CSR_BUS_TIME: 670 case CSR_BROADCAST_CHANNEL: 671 return RCODE_TYPE_ERROR; 672 673 case CSR_BUSY_TIMEOUT: 674 /* not yet implemented - fall through */ 675 default: 676 return RCODE_ADDRESS_ERROR; 677 } 678} 679 680static int lock64_regs(struct hpsb_host *host, int nodeid, octlet_t * store, 681 u64 addr, octlet_t data, octlet_t arg, int extcode, u16 fl) 682{ 683 int csraddr = addr - CSR_REGISTER_BASE; 684 unsigned long flags; 685 686 data = be64_to_cpu(data); 687 arg = be64_to_cpu(arg); 688 689 if (csraddr & 0x3) 690 return RCODE_TYPE_ERROR; 691 692 if (csraddr != CSR_CHANNELS_AVAILABLE 693 || extcode != EXTCODE_COMPARE_SWAP) 694 goto unsupported_lock64req; 695 696 /* Is somebody releasing the broadcast_channel on us? */ 697 if (csraddr == CSR_CHANNELS_AVAILABLE_HI && (data & 0x100000000ULL)) { 698 /* Note: this is may not be the right way to handle 699 * the problem, so we should look into the proper way 700 * eventually. */ 701 HPSB_WARN("Node [" NODE_BUS_FMT "] wants to release " 702 "broadcast channel 31. Ignoring.", 703 NODE_BUS_ARGS(host, nodeid)); 704 705 data &= ~0x100000000ULL; /* keep broadcast channel allocated */ 706 } 707 708 if (host->driver->hw_csr_reg) { 709 quadlet_t data_hi, data_lo; 710 quadlet_t arg_hi, arg_lo; 711 quadlet_t old_hi, old_lo; 712 713 data_hi = data >> 32; 714 data_lo = data & 0xFFFFFFFF; 715 arg_hi = arg >> 32; 716 arg_lo = arg & 0xFFFFFFFF; 717 718 old_hi = host->driver->hw_csr_reg(host, (csraddr - CSR_BUS_MANAGER_ID) >> 2, 719 data_hi, arg_hi); 720 721 old_lo = host->driver->hw_csr_reg(host, ((csraddr + 4) - CSR_BUS_MANAGER_ID) >> 2, 722 data_lo, arg_lo); 723 724 *store = cpu_to_be64(((octlet_t)old_hi << 32) | old_lo); 725 } else { 726 octlet_t old; 727 octlet_t affected_channels = arg ^ data; 728 729 spin_lock_irqsave(&host->csr.lock, flags); 730 731 old = ((octlet_t)host->csr.channels_available_hi << 32) | host->csr.channels_available_lo; 732 733 if ((arg & affected_channels) == (old & affected_channels)) { 734 host->csr.channels_available_hi ^= (affected_channels >> 32); 735 host->csr.channels_available_lo ^= (affected_channels & 0xffffffff); 736 *store = cpu_to_be64(arg); 737 } else { 738 *store = cpu_to_be64(old); 739 } 740 741 spin_unlock_irqrestore(&host->csr.lock, flags); 742 } 743 744 /* Is somebody erroneously releasing the broadcast_channel on us? */ 745 if (host->csr.channels_available_hi & 0x1) 746 host->csr.channels_available_hi &= ~0x1; 747 748 return RCODE_COMPLETE; 749 750 unsupported_lock64req: 751 switch (csraddr) { 752 case CSR_STATE_CLEAR: 753 case CSR_STATE_SET: 754 case CSR_RESET_START: 755 case CSR_NODE_IDS: 756 case CSR_SPLIT_TIMEOUT_HI: 757 case CSR_SPLIT_TIMEOUT_LO: 758 case CSR_CYCLE_TIME: 759 case CSR_BUS_TIME: 760 case CSR_BUS_MANAGER_ID: 761 case CSR_BROADCAST_CHANNEL: 762 case CSR_BUSY_TIMEOUT: 763 case CSR_BANDWIDTH_AVAILABLE: 764 return RCODE_TYPE_ERROR; 765 766 default: 767 return RCODE_ADDRESS_ERROR; 768 } 769} 770 771static int write_fcp(struct hpsb_host *host, int nodeid, int dest, 772 quadlet_t *data, u64 addr, size_t length, u16 flags) 773{ 774 int csraddr = addr - CSR_REGISTER_BASE; 775 776 if (length > 512) 777 return RCODE_TYPE_ERROR; 778 779 switch (csraddr) { 780 case CSR_FCP_COMMAND: 781 highlevel_fcp_request(host, nodeid, 0, (u8 *)data, length); 782 break; 783 case CSR_FCP_RESPONSE: 784 highlevel_fcp_request(host, nodeid, 1, (u8 *)data, length); 785 break; 786 default: 787 return RCODE_TYPE_ERROR; 788 } 789 790 return RCODE_COMPLETE; 791} 792 793static int read_config_rom(struct hpsb_host *host, int nodeid, quadlet_t *buffer, 794 u64 addr, size_t length, u16 fl) 795{ 796 u32 offset = addr - CSR1212_REGISTER_SPACE_BASE; 797 798 if (csr1212_read(host->csr.rom, offset, buffer, length) == CSR1212_SUCCESS) 799 return RCODE_COMPLETE; 800 else 801 return RCODE_ADDRESS_ERROR; 802} 803 804static u64 allocate_addr_range(u64 size, u32 alignment, void *__host) 805{ 806 struct hpsb_host *host = (struct hpsb_host*)__host; 807 808 return hpsb_allocate_and_register_addrspace(&csr_highlevel, 809 host, 810 &config_rom_ops, 811 size, alignment, 812 CSR1212_UNITS_SPACE_BASE, 813 CSR1212_UNITS_SPACE_END); 814} 815 816static void release_addr_range(u64 addr, void *__host) 817{ 818 struct hpsb_host *host = (struct hpsb_host*)__host; 819 hpsb_unregister_addrspace(&csr_highlevel, host, addr); 820} 821 822 823int init_csr(void) 824{ 825 node_cap = csr1212_new_immediate(CSR1212_KV_ID_NODE_CAPABILITIES, 0x0083c0); 826 if (!node_cap) { 827 HPSB_ERR("Failed to allocate memory for Node Capabilties ConfigROM entry!"); 828 return -ENOMEM; 829 } 830 831 hpsb_register_highlevel(&csr_highlevel); 832 833 return 0; 834} 835 836void cleanup_csr(void) 837{ 838 if (node_cap) 839 csr1212_release_keyval(node_cap); 840 hpsb_unregister_highlevel(&csr_highlevel); 841} 842