1/* 2 * SL82C105/Winbond 553 IDE driver 3 * 4 * Maintainer unknown. 5 * 6 * Drive tuning added from Rebel.com's kernel sources 7 * -- Russell King (15/11/98) linux@arm.linux.org.uk 8 * 9 * Merge in Russell's HW workarounds, fix various problems 10 * with the timing registers setup. 11 * -- Benjamin Herrenschmidt (01/11/03) benh@kernel.crashing.org 12 * 13 * Copyright (C) 2006-2007,2009 MontaVista Software, Inc. <source@mvista.com> 14 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz 15 */ 16 17#include <linux/types.h> 18#include <linux/module.h> 19#include <linux/kernel.h> 20#include <linux/pci.h> 21#include <linux/ide.h> 22 23#include <asm/io.h> 24 25#define DRV_NAME "sl82c105" 26 27/* 28 * SL82C105 PCI config register 0x40 bits. 29 */ 30#define CTRL_IDE_IRQB (1 << 30) 31#define CTRL_IDE_IRQA (1 << 28) 32#define CTRL_LEGIRQ (1 << 11) 33#define CTRL_P1F16 (1 << 5) 34#define CTRL_P1EN (1 << 4) 35#define CTRL_P0F16 (1 << 1) 36#define CTRL_P0EN (1 << 0) 37 38/* 39 * Convert a PIO mode and cycle time to the required on/off times 40 * for the interface. This has protection against runaway timings. 41 */ 42static unsigned int get_pio_timings(ide_drive_t *drive, u8 pio) 43{ 44 struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio); 45 unsigned int cmd_on, cmd_off; 46 u8 iordy = 0; 47 48 cmd_on = (t->active + 29) / 30; 49 cmd_off = (ide_pio_cycle_time(drive, pio) - 30 * cmd_on + 29) / 30; 50 51 if (cmd_on == 0) 52 cmd_on = 1; 53 54 if (cmd_off == 0) 55 cmd_off = 1; 56 57 if (ide_pio_need_iordy(drive, pio)) 58 iordy = 0x40; 59 60 return (cmd_on - 1) << 8 | (cmd_off - 1) | iordy; 61} 62 63/* 64 * Configure the chipset for PIO mode. 65 */ 66static void sl82c105_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) 67{ 68 struct pci_dev *dev = to_pci_dev(hwif->dev); 69 unsigned long timings = (unsigned long)ide_get_drivedata(drive); 70 int reg = 0x44 + drive->dn * 4; 71 u16 drv_ctrl; 72 const u8 pio = drive->pio_mode - XFER_PIO_0; 73 74 drv_ctrl = get_pio_timings(drive, pio); 75 76 /* 77 * Store the PIO timings so that we can restore them 78 * in case DMA will be turned off... 79 */ 80 timings &= 0xffff0000; 81 timings |= drv_ctrl; 82 ide_set_drivedata(drive, (void *)timings); 83 84 pci_write_config_word(dev, reg, drv_ctrl); 85 pci_read_config_word (dev, reg, &drv_ctrl); 86 87 printk(KERN_DEBUG "%s: selected %s (%dns) (%04X)\n", drive->name, 88 ide_xfer_verbose(pio + XFER_PIO_0), 89 ide_pio_cycle_time(drive, pio), drv_ctrl); 90} 91 92/* 93 * Configure the chipset for DMA mode. 94 */ 95static void sl82c105_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) 96{ 97 static u16 mwdma_timings[] = {0x0707, 0x0201, 0x0200}; 98 unsigned long timings = (unsigned long)ide_get_drivedata(drive); 99 u16 drv_ctrl; 100 const u8 speed = drive->dma_mode; 101 102 drv_ctrl = mwdma_timings[speed - XFER_MW_DMA_0]; 103 104 /* 105 * Store the DMA timings so that we can actually program 106 * them when DMA will be turned on... 107 */ 108 timings &= 0x0000ffff; 109 timings |= (unsigned long)drv_ctrl << 16; 110 ide_set_drivedata(drive, (void *)timings); 111} 112 113static int sl82c105_test_irq(ide_hwif_t *hwif) 114{ 115 struct pci_dev *dev = to_pci_dev(hwif->dev); 116 u32 val, mask = hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA; 117 118 pci_read_config_dword(dev, 0x40, &val); 119 120 return (val & mask) ? 1 : 0; 121} 122 123static inline void sl82c105_reset_host(struct pci_dev *dev) 124{ 125 u16 val; 126 127 pci_read_config_word(dev, 0x7e, &val); 128 pci_write_config_word(dev, 0x7e, val | (1 << 2)); 129 pci_write_config_word(dev, 0x7e, val & ~(1 << 2)); 130} 131 132/* 133 * If we get an IRQ timeout, it might be that the DMA state machine 134 * got confused. Fix from Todd Inglett. Details from Winbond. 135 * 136 * This function is called when the IDE timer expires, the drive 137 * indicates that it is READY, and we were waiting for DMA to complete. 138 */ 139static void sl82c105_dma_lost_irq(ide_drive_t *drive) 140{ 141 ide_hwif_t *hwif = drive->hwif; 142 struct pci_dev *dev = to_pci_dev(hwif->dev); 143 u32 val, mask = hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA; 144 u8 dma_cmd; 145 146 printk(KERN_WARNING "sl82c105: lost IRQ, resetting host\n"); 147 148 /* 149 * Check the raw interrupt from the drive. 150 */ 151 pci_read_config_dword(dev, 0x40, &val); 152 if (val & mask) 153 printk(KERN_INFO "sl82c105: drive was requesting IRQ, " 154 "but host lost it\n"); 155 156 /* 157 * Was DMA enabled? If so, disable it - we're resetting the 158 * host. The IDE layer will be handling the drive for us. 159 */ 160 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD); 161 if (dma_cmd & 1) { 162 outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD); 163 printk(KERN_INFO "sl82c105: DMA was enabled\n"); 164 } 165 166 sl82c105_reset_host(dev); 167} 168 169/* 170 * ATAPI devices can cause the SL82C105 DMA state machine to go gaga. 171 * Winbond recommend that the DMA state machine is reset prior to 172 * setting the bus master DMA enable bit. 173 * 174 * The generic IDE core will have disabled the BMEN bit before this 175 * function is called. 176 */ 177static void sl82c105_dma_start(ide_drive_t *drive) 178{ 179 ide_hwif_t *hwif = drive->hwif; 180 struct pci_dev *dev = to_pci_dev(hwif->dev); 181 int reg = 0x44 + drive->dn * 4; 182 183 pci_write_config_word(dev, reg, 184 (unsigned long)ide_get_drivedata(drive) >> 16); 185 186 sl82c105_reset_host(dev); 187 ide_dma_start(drive); 188} 189 190static void sl82c105_dma_clear(ide_drive_t *drive) 191{ 192 struct pci_dev *dev = to_pci_dev(drive->hwif->dev); 193 194 sl82c105_reset_host(dev); 195} 196 197static int sl82c105_dma_end(ide_drive_t *drive) 198{ 199 struct pci_dev *dev = to_pci_dev(drive->hwif->dev); 200 int reg = 0x44 + drive->dn * 4; 201 int ret = ide_dma_end(drive); 202 203 pci_write_config_word(dev, reg, 204 (unsigned long)ide_get_drivedata(drive)); 205 206 return ret; 207} 208 209/* 210 * ATA reset will clear the 16 bits mode in the control 211 * register, we need to reprogram it 212 */ 213static void sl82c105_resetproc(ide_drive_t *drive) 214{ 215 struct pci_dev *dev = to_pci_dev(drive->hwif->dev); 216 u32 val; 217 218 pci_read_config_dword(dev, 0x40, &val); 219 val |= (CTRL_P1F16 | CTRL_P0F16); 220 pci_write_config_dword(dev, 0x40, val); 221} 222 223/* 224 * Return the revision of the Winbond bridge 225 * which this function is part of. 226 */ 227static u8 sl82c105_bridge_revision(struct pci_dev *dev) 228{ 229 struct pci_dev *bridge; 230 231 /* 232 * The bridge should be part of the same device, but function 0. 233 */ 234 bridge = pci_get_bus_and_slot(dev->bus->number, 235 PCI_DEVFN(PCI_SLOT(dev->devfn), 0)); 236 if (!bridge) 237 return -1; 238 239 /* 240 * Make sure it is a Winbond 553 and is an ISA bridge. 241 */ 242 if (bridge->vendor != PCI_VENDOR_ID_WINBOND || 243 bridge->device != PCI_DEVICE_ID_WINBOND_83C553 || 244 bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA) { 245 pci_dev_put(bridge); 246 return -1; 247 } 248 /* 249 * We need to find function 0's revision, not function 1 250 */ 251 pci_dev_put(bridge); 252 253 return bridge->revision; 254} 255 256/* 257 * Enable the PCI device 258 * 259 * --BenH: It's arch fixup code that should enable channels that 260 * have not been enabled by firmware. I decided we can still enable 261 * channel 0 here at least, but channel 1 has to be enabled by 262 * firmware or arch code. We still set both to 16 bits mode. 263 */ 264static int init_chipset_sl82c105(struct pci_dev *dev) 265{ 266 u32 val; 267 268 pci_read_config_dword(dev, 0x40, &val); 269 val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16; 270 pci_write_config_dword(dev, 0x40, val); 271 272 return 0; 273} 274 275static const struct ide_port_ops sl82c105_port_ops = { 276 .set_pio_mode = sl82c105_set_pio_mode, 277 .set_dma_mode = sl82c105_set_dma_mode, 278 .resetproc = sl82c105_resetproc, 279 .test_irq = sl82c105_test_irq, 280}; 281 282static const struct ide_dma_ops sl82c105_dma_ops = { 283 .dma_host_set = ide_dma_host_set, 284 .dma_setup = ide_dma_setup, 285 .dma_start = sl82c105_dma_start, 286 .dma_end = sl82c105_dma_end, 287 .dma_test_irq = ide_dma_test_irq, 288 .dma_lost_irq = sl82c105_dma_lost_irq, 289 .dma_timer_expiry = ide_dma_sff_timer_expiry, 290 .dma_clear = sl82c105_dma_clear, 291 .dma_sff_read_status = ide_dma_sff_read_status, 292}; 293 294static const struct ide_port_info sl82c105_chipset __devinitdata = { 295 .name = DRV_NAME, 296 .init_chipset = init_chipset_sl82c105, 297 .enablebits = {{0x40,0x01,0x01}, {0x40,0x10,0x10}}, 298 .port_ops = &sl82c105_port_ops, 299 .dma_ops = &sl82c105_dma_ops, 300 .host_flags = IDE_HFLAG_IO_32BIT | 301 IDE_HFLAG_UNMASK_IRQS | 302 IDE_HFLAG_SERIALIZE_DMA | 303 IDE_HFLAG_NO_AUTODMA, 304 .pio_mask = ATA_PIO5, 305 .mwdma_mask = ATA_MWDMA2, 306}; 307 308static int __devinit sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id) 309{ 310 struct ide_port_info d = sl82c105_chipset; 311 u8 rev = sl82c105_bridge_revision(dev); 312 313 if (rev <= 5) { 314 /* 315 * Never ever EVER under any circumstances enable 316 * DMA when the bridge is this old. 317 */ 318 printk(KERN_INFO DRV_NAME ": Winbond W83C553 bridge " 319 "revision %d, BM-DMA disabled\n", rev); 320 d.dma_ops = NULL; 321 d.mwdma_mask = 0; 322 d.host_flags &= ~IDE_HFLAG_SERIALIZE_DMA; 323 } 324 325 return ide_pci_init_one(dev, &d, NULL); 326} 327 328static const struct pci_device_id sl82c105_pci_tbl[] = { 329 { PCI_VDEVICE(WINBOND, PCI_DEVICE_ID_WINBOND_82C105), 0 }, 330 { 0, }, 331}; 332MODULE_DEVICE_TABLE(pci, sl82c105_pci_tbl); 333 334static struct pci_driver sl82c105_pci_driver = { 335 .name = "W82C105_IDE", 336 .id_table = sl82c105_pci_tbl, 337 .probe = sl82c105_init_one, 338 .remove = ide_pci_remove, 339 .suspend = ide_pci_suspend, 340 .resume = ide_pci_resume, 341}; 342 343static int __init sl82c105_ide_init(void) 344{ 345 return ide_pci_register_driver(&sl82c105_pci_driver); 346} 347 348static void __exit sl82c105_ide_exit(void) 349{ 350 pci_unregister_driver(&sl82c105_pci_driver); 351} 352 353module_init(sl82c105_ide_init); 354module_exit(sl82c105_ide_exit); 355 356MODULE_DESCRIPTION("PCI driver module for W82C105 IDE"); 357MODULE_LICENSE("GPL"); 358