1/* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28#include <linux/firmware.h> 29#include <linux/platform_device.h> 30#include <linux/slab.h> 31#include "drmP.h" 32#include "radeon.h" 33#include "radeon_asic.h" 34#include "radeon_drm.h" 35#include "rv770d.h" 36#include "atom.h" 37#include "avivod.h" 38 39#define R700_PFP_UCODE_SIZE 848 40#define R700_PM4_UCODE_SIZE 1360 41 42static void rv770_gpu_init(struct radeon_device *rdev); 43void rv770_fini(struct radeon_device *rdev); 44 45/* get temperature in millidegrees */ 46u32 rv770_get_temp(struct radeon_device *rdev) 47{ 48 u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >> 49 ASIC_T_SHIFT; 50 u32 actual_temp = 0; 51 52 if ((temp >> 9) & 1) 53 actual_temp = 0; 54 else 55 actual_temp = (temp >> 1) & 0xff; 56 57 return actual_temp * 1000; 58} 59 60void rv770_pm_misc(struct radeon_device *rdev) 61{ 62 int req_ps_idx = rdev->pm.requested_power_state_index; 63 int req_cm_idx = rdev->pm.requested_clock_mode_index; 64 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; 65 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; 66 67 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { 68 if (voltage->voltage != rdev->pm.current_vddc) { 69 radeon_atom_set_voltage(rdev, voltage->voltage); 70 rdev->pm.current_vddc = voltage->voltage; 71 DRM_DEBUG("Setting: v: %d\n", voltage->voltage); 72 } 73 } 74} 75 76/* 77 * GART 78 */ 79int rv770_pcie_gart_enable(struct radeon_device *rdev) 80{ 81 u32 tmp; 82 int r, i; 83 84 if (rdev->gart.table.vram.robj == NULL) { 85 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 86 return -EINVAL; 87 } 88 r = radeon_gart_table_vram_pin(rdev); 89 if (r) 90 return r; 91 radeon_gart_restore(rdev); 92 /* Setup L2 cache */ 93 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 94 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 95 EFFECTIVE_L2_QUEUE_SIZE(7)); 96 WREG32(VM_L2_CNTL2, 0); 97 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); 98 /* Setup TLB control */ 99 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 100 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 101 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | 102 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); 103 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); 104 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); 105 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); 106 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); 107 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); 108 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); 109 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); 110 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); 111 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); 112 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); 113 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 114 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); 115 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 116 (u32)(rdev->dummy_page.addr >> 12)); 117 for (i = 1; i < 7; i++) 118 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 119 120 r600_pcie_gart_tlb_flush(rdev); 121 rdev->gart.ready = true; 122 return 0; 123} 124 125void rv770_pcie_gart_disable(struct radeon_device *rdev) 126{ 127 u32 tmp; 128 int i, r; 129 130 /* Disable all tables */ 131 for (i = 0; i < 7; i++) 132 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 133 134 /* Setup L2 cache */ 135 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | 136 EFFECTIVE_L2_QUEUE_SIZE(7)); 137 WREG32(VM_L2_CNTL2, 0); 138 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); 139 /* Setup TLB control */ 140 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); 141 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); 142 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); 143 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); 144 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); 145 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); 146 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); 147 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); 148 if (rdev->gart.table.vram.robj) { 149 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false); 150 if (likely(r == 0)) { 151 radeon_bo_kunmap(rdev->gart.table.vram.robj); 152 radeon_bo_unpin(rdev->gart.table.vram.robj); 153 radeon_bo_unreserve(rdev->gart.table.vram.robj); 154 } 155 } 156} 157 158void rv770_pcie_gart_fini(struct radeon_device *rdev) 159{ 160 radeon_gart_fini(rdev); 161 rv770_pcie_gart_disable(rdev); 162 radeon_gart_table_vram_free(rdev); 163} 164 165 166void rv770_agp_enable(struct radeon_device *rdev) 167{ 168 u32 tmp; 169 int i; 170 171 /* Setup L2 cache */ 172 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 173 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 174 EFFECTIVE_L2_QUEUE_SIZE(7)); 175 WREG32(VM_L2_CNTL2, 0); 176 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); 177 /* Setup TLB control */ 178 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 179 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 180 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | 181 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); 182 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); 183 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); 184 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); 185 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); 186 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); 187 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); 188 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); 189 for (i = 0; i < 7; i++) 190 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 191} 192 193static void rv770_mc_program(struct radeon_device *rdev) 194{ 195 struct rv515_mc_save save; 196 u32 tmp; 197 int i, j; 198 199 /* Initialize HDP */ 200 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 201 WREG32((0x2c14 + j), 0x00000000); 202 WREG32((0x2c18 + j), 0x00000000); 203 WREG32((0x2c1c + j), 0x00000000); 204 WREG32((0x2c20 + j), 0x00000000); 205 WREG32((0x2c24 + j), 0x00000000); 206 } 207 /* r7xx hw bug. Read from HDP_DEBUG1 rather 208 * than writing to HDP_REG_COHERENCY_FLUSH_CNTL 209 */ 210 tmp = RREG32(HDP_DEBUG1); 211 212 rv515_mc_stop(rdev, &save); 213 if (r600_mc_wait_for_idle(rdev)) { 214 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 215 } 216 /* Lockout access through VGA aperture*/ 217 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); 218 /* Update configuration */ 219 if (rdev->flags & RADEON_IS_AGP) { 220 if (rdev->mc.vram_start < rdev->mc.gtt_start) { 221 /* VRAM before AGP */ 222 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 223 rdev->mc.vram_start >> 12); 224 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 225 rdev->mc.gtt_end >> 12); 226 } else { 227 /* VRAM after AGP */ 228 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 229 rdev->mc.gtt_start >> 12); 230 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 231 rdev->mc.vram_end >> 12); 232 } 233 } else { 234 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 235 rdev->mc.vram_start >> 12); 236 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 237 rdev->mc.vram_end >> 12); 238 } 239 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); 240 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; 241 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); 242 WREG32(MC_VM_FB_LOCATION, tmp); 243 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); 244 WREG32(HDP_NONSURFACE_INFO, (2 << 7)); 245 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); 246 if (rdev->flags & RADEON_IS_AGP) { 247 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16); 248 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16); 249 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); 250 } else { 251 WREG32(MC_VM_AGP_BASE, 0); 252 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); 253 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); 254 } 255 if (r600_mc_wait_for_idle(rdev)) { 256 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 257 } 258 rv515_mc_resume(rdev, &save); 259 /* we need to own VRAM, so turn off the VGA renderer here 260 * to stop it overwriting our objects */ 261 rv515_vga_render_disable(rdev); 262} 263 264 265/* 266 * CP. 267 */ 268void r700_cp_stop(struct radeon_device *rdev) 269{ 270 rdev->mc.active_vram_size = rdev->mc.visible_vram_size; 271 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); 272} 273 274static int rv770_cp_load_microcode(struct radeon_device *rdev) 275{ 276 const __be32 *fw_data; 277 int i; 278 279 if (!rdev->me_fw || !rdev->pfp_fw) 280 return -EINVAL; 281 282 r700_cp_stop(rdev); 283 WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0)); 284 285 /* Reset cp */ 286 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 287 RREG32(GRBM_SOFT_RESET); 288 mdelay(15); 289 WREG32(GRBM_SOFT_RESET, 0); 290 291 fw_data = (const __be32 *)rdev->pfp_fw->data; 292 WREG32(CP_PFP_UCODE_ADDR, 0); 293 for (i = 0; i < R700_PFP_UCODE_SIZE; i++) 294 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); 295 WREG32(CP_PFP_UCODE_ADDR, 0); 296 297 fw_data = (const __be32 *)rdev->me_fw->data; 298 WREG32(CP_ME_RAM_WADDR, 0); 299 for (i = 0; i < R700_PM4_UCODE_SIZE; i++) 300 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); 301 302 WREG32(CP_PFP_UCODE_ADDR, 0); 303 WREG32(CP_ME_RAM_WADDR, 0); 304 WREG32(CP_ME_RAM_RADDR, 0); 305 return 0; 306} 307 308void r700_cp_fini(struct radeon_device *rdev) 309{ 310 r700_cp_stop(rdev); 311 radeon_ring_fini(rdev); 312} 313 314/* 315 * Core functions 316 */ 317static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev, 318 u32 num_tile_pipes, 319 u32 num_backends, 320 u32 backend_disable_mask) 321{ 322 u32 backend_map = 0; 323 u32 enabled_backends_mask; 324 u32 enabled_backends_count; 325 u32 cur_pipe; 326 u32 swizzle_pipe[R7XX_MAX_PIPES]; 327 u32 cur_backend; 328 u32 i; 329 bool force_no_swizzle; 330 331 if (num_tile_pipes > R7XX_MAX_PIPES) 332 num_tile_pipes = R7XX_MAX_PIPES; 333 if (num_tile_pipes < 1) 334 num_tile_pipes = 1; 335 if (num_backends > R7XX_MAX_BACKENDS) 336 num_backends = R7XX_MAX_BACKENDS; 337 if (num_backends < 1) 338 num_backends = 1; 339 340 enabled_backends_mask = 0; 341 enabled_backends_count = 0; 342 for (i = 0; i < R7XX_MAX_BACKENDS; ++i) { 343 if (((backend_disable_mask >> i) & 1) == 0) { 344 enabled_backends_mask |= (1 << i); 345 ++enabled_backends_count; 346 } 347 if (enabled_backends_count == num_backends) 348 break; 349 } 350 351 if (enabled_backends_count == 0) { 352 enabled_backends_mask = 1; 353 enabled_backends_count = 1; 354 } 355 356 if (enabled_backends_count != num_backends) 357 num_backends = enabled_backends_count; 358 359 switch (rdev->family) { 360 case CHIP_RV770: 361 case CHIP_RV730: 362 force_no_swizzle = false; 363 break; 364 case CHIP_RV710: 365 case CHIP_RV740: 366 default: 367 force_no_swizzle = true; 368 break; 369 } 370 371 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES); 372 switch (num_tile_pipes) { 373 case 1: 374 swizzle_pipe[0] = 0; 375 break; 376 case 2: 377 swizzle_pipe[0] = 0; 378 swizzle_pipe[1] = 1; 379 break; 380 case 3: 381 if (force_no_swizzle) { 382 swizzle_pipe[0] = 0; 383 swizzle_pipe[1] = 1; 384 swizzle_pipe[2] = 2; 385 } else { 386 swizzle_pipe[0] = 0; 387 swizzle_pipe[1] = 2; 388 swizzle_pipe[2] = 1; 389 } 390 break; 391 case 4: 392 if (force_no_swizzle) { 393 swizzle_pipe[0] = 0; 394 swizzle_pipe[1] = 1; 395 swizzle_pipe[2] = 2; 396 swizzle_pipe[3] = 3; 397 } else { 398 swizzle_pipe[0] = 0; 399 swizzle_pipe[1] = 2; 400 swizzle_pipe[2] = 3; 401 swizzle_pipe[3] = 1; 402 } 403 break; 404 case 5: 405 if (force_no_swizzle) { 406 swizzle_pipe[0] = 0; 407 swizzle_pipe[1] = 1; 408 swizzle_pipe[2] = 2; 409 swizzle_pipe[3] = 3; 410 swizzle_pipe[4] = 4; 411 } else { 412 swizzle_pipe[0] = 0; 413 swizzle_pipe[1] = 2; 414 swizzle_pipe[2] = 4; 415 swizzle_pipe[3] = 1; 416 swizzle_pipe[4] = 3; 417 } 418 break; 419 case 6: 420 if (force_no_swizzle) { 421 swizzle_pipe[0] = 0; 422 swizzle_pipe[1] = 1; 423 swizzle_pipe[2] = 2; 424 swizzle_pipe[3] = 3; 425 swizzle_pipe[4] = 4; 426 swizzle_pipe[5] = 5; 427 } else { 428 swizzle_pipe[0] = 0; 429 swizzle_pipe[1] = 2; 430 swizzle_pipe[2] = 4; 431 swizzle_pipe[3] = 5; 432 swizzle_pipe[4] = 3; 433 swizzle_pipe[5] = 1; 434 } 435 break; 436 case 7: 437 if (force_no_swizzle) { 438 swizzle_pipe[0] = 0; 439 swizzle_pipe[1] = 1; 440 swizzle_pipe[2] = 2; 441 swizzle_pipe[3] = 3; 442 swizzle_pipe[4] = 4; 443 swizzle_pipe[5] = 5; 444 swizzle_pipe[6] = 6; 445 } else { 446 swizzle_pipe[0] = 0; 447 swizzle_pipe[1] = 2; 448 swizzle_pipe[2] = 4; 449 swizzle_pipe[3] = 6; 450 swizzle_pipe[4] = 3; 451 swizzle_pipe[5] = 1; 452 swizzle_pipe[6] = 5; 453 } 454 break; 455 case 8: 456 if (force_no_swizzle) { 457 swizzle_pipe[0] = 0; 458 swizzle_pipe[1] = 1; 459 swizzle_pipe[2] = 2; 460 swizzle_pipe[3] = 3; 461 swizzle_pipe[4] = 4; 462 swizzle_pipe[5] = 5; 463 swizzle_pipe[6] = 6; 464 swizzle_pipe[7] = 7; 465 } else { 466 swizzle_pipe[0] = 0; 467 swizzle_pipe[1] = 2; 468 swizzle_pipe[2] = 4; 469 swizzle_pipe[3] = 6; 470 swizzle_pipe[4] = 3; 471 swizzle_pipe[5] = 1; 472 swizzle_pipe[6] = 7; 473 swizzle_pipe[7] = 5; 474 } 475 break; 476 } 477 478 cur_backend = 0; 479 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { 480 while (((1 << cur_backend) & enabled_backends_mask) == 0) 481 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; 482 483 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); 484 485 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; 486 } 487 488 return backend_map; 489} 490 491static void rv770_gpu_init(struct radeon_device *rdev) 492{ 493 int i, j, num_qd_pipes; 494 u32 ta_aux_cntl; 495 u32 sx_debug_1; 496 u32 smx_dc_ctl0; 497 u32 db_debug3; 498 u32 num_gs_verts_per_thread; 499 u32 vgt_gs_per_es; 500 u32 gs_prim_buffer_depth = 0; 501 u32 sq_ms_fifo_sizes; 502 u32 sq_config; 503 u32 sq_thread_resource_mgmt; 504 u32 hdp_host_path_cntl; 505 u32 sq_dyn_gpr_size_simd_ab_0; 506 u32 backend_map; 507 u32 gb_tiling_config = 0; 508 u32 cc_rb_backend_disable = 0; 509 u32 cc_gc_shader_pipe_config = 0; 510 u32 mc_arb_ramcfg; 511 u32 db_debug4; 512 513 /* setup chip specs */ 514 switch (rdev->family) { 515 case CHIP_RV770: 516 rdev->config.rv770.max_pipes = 4; 517 rdev->config.rv770.max_tile_pipes = 8; 518 rdev->config.rv770.max_simds = 10; 519 rdev->config.rv770.max_backends = 4; 520 rdev->config.rv770.max_gprs = 256; 521 rdev->config.rv770.max_threads = 248; 522 rdev->config.rv770.max_stack_entries = 512; 523 rdev->config.rv770.max_hw_contexts = 8; 524 rdev->config.rv770.max_gs_threads = 16 * 2; 525 rdev->config.rv770.sx_max_export_size = 128; 526 rdev->config.rv770.sx_max_export_pos_size = 16; 527 rdev->config.rv770.sx_max_export_smx_size = 112; 528 rdev->config.rv770.sq_num_cf_insts = 2; 529 530 rdev->config.rv770.sx_num_of_sets = 7; 531 rdev->config.rv770.sc_prim_fifo_size = 0xF9; 532 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; 533 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; 534 break; 535 case CHIP_RV730: 536 rdev->config.rv770.max_pipes = 2; 537 rdev->config.rv770.max_tile_pipes = 4; 538 rdev->config.rv770.max_simds = 8; 539 rdev->config.rv770.max_backends = 2; 540 rdev->config.rv770.max_gprs = 128; 541 rdev->config.rv770.max_threads = 248; 542 rdev->config.rv770.max_stack_entries = 256; 543 rdev->config.rv770.max_hw_contexts = 8; 544 rdev->config.rv770.max_gs_threads = 16 * 2; 545 rdev->config.rv770.sx_max_export_size = 256; 546 rdev->config.rv770.sx_max_export_pos_size = 32; 547 rdev->config.rv770.sx_max_export_smx_size = 224; 548 rdev->config.rv770.sq_num_cf_insts = 2; 549 550 rdev->config.rv770.sx_num_of_sets = 7; 551 rdev->config.rv770.sc_prim_fifo_size = 0xf9; 552 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; 553 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; 554 if (rdev->config.rv770.sx_max_export_pos_size > 16) { 555 rdev->config.rv770.sx_max_export_pos_size -= 16; 556 rdev->config.rv770.sx_max_export_smx_size += 16; 557 } 558 break; 559 case CHIP_RV710: 560 rdev->config.rv770.max_pipes = 2; 561 rdev->config.rv770.max_tile_pipes = 2; 562 rdev->config.rv770.max_simds = 2; 563 rdev->config.rv770.max_backends = 1; 564 rdev->config.rv770.max_gprs = 256; 565 rdev->config.rv770.max_threads = 192; 566 rdev->config.rv770.max_stack_entries = 256; 567 rdev->config.rv770.max_hw_contexts = 4; 568 rdev->config.rv770.max_gs_threads = 8 * 2; 569 rdev->config.rv770.sx_max_export_size = 128; 570 rdev->config.rv770.sx_max_export_pos_size = 16; 571 rdev->config.rv770.sx_max_export_smx_size = 112; 572 rdev->config.rv770.sq_num_cf_insts = 1; 573 574 rdev->config.rv770.sx_num_of_sets = 7; 575 rdev->config.rv770.sc_prim_fifo_size = 0x40; 576 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; 577 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; 578 break; 579 case CHIP_RV740: 580 rdev->config.rv770.max_pipes = 4; 581 rdev->config.rv770.max_tile_pipes = 4; 582 rdev->config.rv770.max_simds = 8; 583 rdev->config.rv770.max_backends = 4; 584 rdev->config.rv770.max_gprs = 256; 585 rdev->config.rv770.max_threads = 248; 586 rdev->config.rv770.max_stack_entries = 512; 587 rdev->config.rv770.max_hw_contexts = 8; 588 rdev->config.rv770.max_gs_threads = 16 * 2; 589 rdev->config.rv770.sx_max_export_size = 256; 590 rdev->config.rv770.sx_max_export_pos_size = 32; 591 rdev->config.rv770.sx_max_export_smx_size = 224; 592 rdev->config.rv770.sq_num_cf_insts = 2; 593 594 rdev->config.rv770.sx_num_of_sets = 7; 595 rdev->config.rv770.sc_prim_fifo_size = 0x100; 596 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; 597 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; 598 599 if (rdev->config.rv770.sx_max_export_pos_size > 16) { 600 rdev->config.rv770.sx_max_export_pos_size -= 16; 601 rdev->config.rv770.sx_max_export_smx_size += 16; 602 } 603 break; 604 default: 605 break; 606 } 607 608 /* Initialize HDP */ 609 j = 0; 610 for (i = 0; i < 32; i++) { 611 WREG32((0x2c14 + j), 0x00000000); 612 WREG32((0x2c18 + j), 0x00000000); 613 WREG32((0x2c1c + j), 0x00000000); 614 WREG32((0x2c20 + j), 0x00000000); 615 WREG32((0x2c24 + j), 0x00000000); 616 j += 0x18; 617 } 618 619 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 620 621 /* setup tiling, simd, pipe config */ 622 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); 623 624 switch (rdev->config.rv770.max_tile_pipes) { 625 case 1: 626 default: 627 gb_tiling_config |= PIPE_TILING(0); 628 break; 629 case 2: 630 gb_tiling_config |= PIPE_TILING(1); 631 break; 632 case 4: 633 gb_tiling_config |= PIPE_TILING(2); 634 break; 635 case 8: 636 gb_tiling_config |= PIPE_TILING(3); 637 break; 638 } 639 rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes; 640 641 if (rdev->family == CHIP_RV770) 642 gb_tiling_config |= BANK_TILING(1); 643 else 644 gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 645 rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3); 646 gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); 647 if ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) 648 rdev->config.rv770.tiling_group_size = 512; 649 else 650 rdev->config.rv770.tiling_group_size = 256; 651 if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) { 652 gb_tiling_config |= ROW_TILING(3); 653 gb_tiling_config |= SAMPLE_SPLIT(3); 654 } else { 655 gb_tiling_config |= 656 ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT)); 657 gb_tiling_config |= 658 SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT)); 659 } 660 661 gb_tiling_config |= BANK_SWAPS(1); 662 663 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000; 664 cc_rb_backend_disable |= 665 BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK); 666 667 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00; 668 cc_gc_shader_pipe_config |= 669 INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK); 670 cc_gc_shader_pipe_config |= 671 INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK); 672 673 if (rdev->family == CHIP_RV740) 674 backend_map = 0x28; 675 else 676 backend_map = r700_get_tile_pipe_to_backend_map(rdev, 677 rdev->config.rv770.max_tile_pipes, 678 (R7XX_MAX_BACKENDS - 679 r600_count_pipe_bits((cc_rb_backend_disable & 680 R7XX_MAX_BACKENDS_MASK) >> 16)), 681 (cc_rb_backend_disable >> 16)); 682 683 rdev->config.rv770.tile_config = gb_tiling_config; 684 gb_tiling_config |= BACKEND_MAP(backend_map); 685 686 WREG32(GB_TILING_CONFIG, gb_tiling_config); 687 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 688 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 689 690 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); 691 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 692 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 693 WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); 694 695 WREG32(CGTS_SYS_TCC_DISABLE, 0); 696 WREG32(CGTS_TCC_DISABLE, 0); 697 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0); 698 WREG32(CGTS_USER_TCC_DISABLE, 0); 699 700 num_qd_pipes = 701 R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); 702 WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK); 703 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK); 704 705 /* set HW defaults for 3D engine */ 706 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | 707 ROQ_IB2_START(0x2b))); 708 709 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30)); 710 711 ta_aux_cntl = RREG32(TA_CNTL_AUX); 712 WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO); 713 714 sx_debug_1 = RREG32(SX_DEBUG_1); 715 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS; 716 WREG32(SX_DEBUG_1, sx_debug_1); 717 718 smx_dc_ctl0 = RREG32(SMX_DC_CTL0); 719 smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff); 720 smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1); 721 WREG32(SMX_DC_CTL0, smx_dc_ctl0); 722 723 if (rdev->family != CHIP_RV740) 724 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) | 725 GS_FLUSH_CTL(4) | 726 ACK_FLUSH_CTL(3) | 727 SYNC_FLUSH_CTL)); 728 729 db_debug3 = RREG32(DB_DEBUG3); 730 db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f); 731 switch (rdev->family) { 732 case CHIP_RV770: 733 case CHIP_RV740: 734 db_debug3 |= DB_CLK_OFF_DELAY(0x1f); 735 break; 736 case CHIP_RV710: 737 case CHIP_RV730: 738 default: 739 db_debug3 |= DB_CLK_OFF_DELAY(2); 740 break; 741 } 742 WREG32(DB_DEBUG3, db_debug3); 743 744 if (rdev->family != CHIP_RV770) { 745 db_debug4 = RREG32(DB_DEBUG4); 746 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER; 747 WREG32(DB_DEBUG4, db_debug4); 748 } 749 750 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) | 751 POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) | 752 SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1))); 753 754 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) | 755 SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) | 756 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize))); 757 758 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 759 760 WREG32(VGT_NUM_INSTANCES, 1); 761 762 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); 763 764 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); 765 766 WREG32(CP_PERFMON_CNTL, 0); 767 768 sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) | 769 DONE_FIFO_HIWATER(0xe0) | 770 ALU_UPDATE_FIFO_HIWATER(0x8)); 771 switch (rdev->family) { 772 case CHIP_RV770: 773 case CHIP_RV730: 774 case CHIP_RV710: 775 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1); 776 break; 777 case CHIP_RV740: 778 default: 779 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4); 780 break; 781 } 782 WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); 783 784 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 785 * should be adjusted as needed by the 2D/3D drivers. This just sets default values 786 */ 787 sq_config = RREG32(SQ_CONFIG); 788 sq_config &= ~(PS_PRIO(3) | 789 VS_PRIO(3) | 790 GS_PRIO(3) | 791 ES_PRIO(3)); 792 sq_config |= (DX9_CONSTS | 793 VC_ENABLE | 794 EXPORT_SRC_C | 795 PS_PRIO(0) | 796 VS_PRIO(1) | 797 GS_PRIO(2) | 798 ES_PRIO(3)); 799 if (rdev->family == CHIP_RV710) 800 /* no vertex cache */ 801 sq_config &= ~VC_ENABLE; 802 803 WREG32(SQ_CONFIG, sq_config); 804 805 WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | 806 NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | 807 NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2))); 808 809 WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) | 810 NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64))); 811 812 sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) | 813 NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) | 814 NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8)); 815 if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads) 816 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads); 817 else 818 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8); 819 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 820 821 WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) | 822 NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4))); 823 824 WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) | 825 NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4))); 826 827 sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) | 828 SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) | 829 SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) | 830 SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64)); 831 832 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0); 833 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0); 834 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0); 835 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0); 836 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0); 837 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0); 838 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0); 839 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0); 840 841 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | 842 FORCE_EOV_MAX_REZ_CNT(255))); 843 844 if (rdev->family == CHIP_RV710) 845 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) | 846 AUTO_INVLD_EN(ES_AND_GS_AUTO))); 847 else 848 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) | 849 AUTO_INVLD_EN(ES_AND_GS_AUTO))); 850 851 switch (rdev->family) { 852 case CHIP_RV770: 853 case CHIP_RV730: 854 case CHIP_RV740: 855 gs_prim_buffer_depth = 384; 856 break; 857 case CHIP_RV710: 858 gs_prim_buffer_depth = 128; 859 break; 860 default: 861 break; 862 } 863 864 num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16; 865 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread; 866 /* Max value for this is 256 */ 867 if (vgt_gs_per_es > 256) 868 vgt_gs_per_es = 256; 869 870 WREG32(VGT_ES_PER_GS, 128); 871 WREG32(VGT_GS_PER_ES, vgt_gs_per_es); 872 WREG32(VGT_GS_PER_VS, 2); 873 874 /* more default values. 2D/3D driver should adjust as needed */ 875 WREG32(VGT_GS_VERTEX_REUSE, 16); 876 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); 877 WREG32(VGT_STRMOUT_EN, 0); 878 WREG32(SX_MISC, 0); 879 WREG32(PA_SC_MODE_CNTL, 0); 880 WREG32(PA_SC_EDGERULE, 0xaaaaaaaa); 881 WREG32(PA_SC_AA_CONFIG, 0); 882 WREG32(PA_SC_CLIPRECT_RULE, 0xffff); 883 WREG32(PA_SC_LINE_STIPPLE, 0); 884 WREG32(SPI_INPUT_Z, 0); 885 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); 886 WREG32(CB_COLOR7_FRAG, 0); 887 888 /* clear render buffer base addresses */ 889 WREG32(CB_COLOR0_BASE, 0); 890 WREG32(CB_COLOR1_BASE, 0); 891 WREG32(CB_COLOR2_BASE, 0); 892 WREG32(CB_COLOR3_BASE, 0); 893 WREG32(CB_COLOR4_BASE, 0); 894 WREG32(CB_COLOR5_BASE, 0); 895 WREG32(CB_COLOR6_BASE, 0); 896 WREG32(CB_COLOR7_BASE, 0); 897 898 WREG32(TCP_CNTL, 0); 899 900 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); 901 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 902 903 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 904 905 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | 906 NUM_CLIP_SEQ(3))); 907 908} 909 910static int rv770_vram_scratch_init(struct radeon_device *rdev) 911{ 912 int r; 913 u64 gpu_addr; 914 915 if (rdev->vram_scratch.robj == NULL) { 916 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, 917 true, RADEON_GEM_DOMAIN_VRAM, 918 &rdev->vram_scratch.robj); 919 if (r) { 920 return r; 921 } 922 } 923 924 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); 925 if (unlikely(r != 0)) 926 return r; 927 r = radeon_bo_pin(rdev->vram_scratch.robj, 928 RADEON_GEM_DOMAIN_VRAM, &gpu_addr); 929 if (r) { 930 radeon_bo_unreserve(rdev->vram_scratch.robj); 931 return r; 932 } 933 r = radeon_bo_kmap(rdev->vram_scratch.robj, 934 (void **)&rdev->vram_scratch.ptr); 935 if (r) 936 radeon_bo_unpin(rdev->vram_scratch.robj); 937 radeon_bo_unreserve(rdev->vram_scratch.robj); 938 939 return r; 940} 941 942static void rv770_vram_scratch_fini(struct radeon_device *rdev) 943{ 944 int r; 945 946 if (rdev->vram_scratch.robj == NULL) { 947 return; 948 } 949 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); 950 if (likely(r == 0)) { 951 radeon_bo_kunmap(rdev->vram_scratch.robj); 952 radeon_bo_unpin(rdev->vram_scratch.robj); 953 radeon_bo_unreserve(rdev->vram_scratch.robj); 954 } 955 radeon_bo_unref(&rdev->vram_scratch.robj); 956} 957 958int rv770_mc_init(struct radeon_device *rdev) 959{ 960 u32 tmp; 961 int chansize, numchan; 962 963 /* Get VRAM informations */ 964 rdev->mc.vram_is_ddr = true; 965 tmp = RREG32(MC_ARB_RAMCFG); 966 if (tmp & CHANSIZE_OVERRIDE) { 967 chansize = 16; 968 } else if (tmp & CHANSIZE_MASK) { 969 chansize = 64; 970 } else { 971 chansize = 32; 972 } 973 tmp = RREG32(MC_SHARED_CHMAP); 974 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 975 case 0: 976 default: 977 numchan = 1; 978 break; 979 case 1: 980 numchan = 2; 981 break; 982 case 2: 983 numchan = 4; 984 break; 985 case 3: 986 numchan = 8; 987 break; 988 } 989 rdev->mc.vram_width = numchan * chansize; 990 /* Could aper size report 0 ? */ 991 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 992 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 993 /* Setup GPU memory space */ 994 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); 995 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 996 rdev->mc.visible_vram_size = rdev->mc.aper_size; 997 rdev->mc.active_vram_size = rdev->mc.visible_vram_size; 998 r600_vram_gtt_location(rdev, &rdev->mc); 999 radeon_update_bandwidth_info(rdev); 1000 1001 return 0; 1002} 1003 1004static int rv770_startup(struct radeon_device *rdev) 1005{ 1006 int r; 1007 1008 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { 1009 r = r600_init_microcode(rdev); 1010 if (r) { 1011 DRM_ERROR("Failed to load firmware!\n"); 1012 return r; 1013 } 1014 } 1015 1016 rv770_mc_program(rdev); 1017 if (rdev->flags & RADEON_IS_AGP) { 1018 rv770_agp_enable(rdev); 1019 } else { 1020 r = rv770_pcie_gart_enable(rdev); 1021 if (r) 1022 return r; 1023 } 1024 r = rv770_vram_scratch_init(rdev); 1025 if (r) 1026 return r; 1027 rv770_gpu_init(rdev); 1028 r = r600_blit_init(rdev); 1029 if (r) { 1030 r600_blit_fini(rdev); 1031 rdev->asic->copy = NULL; 1032 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); 1033 } 1034 /* pin copy shader into vram */ 1035 if (rdev->r600_blit.shader_obj) { 1036 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); 1037 if (unlikely(r != 0)) 1038 return r; 1039 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM, 1040 &rdev->r600_blit.shader_gpu_addr); 1041 radeon_bo_unreserve(rdev->r600_blit.shader_obj); 1042 if (r) { 1043 DRM_ERROR("failed to pin blit object %d\n", r); 1044 return r; 1045 } 1046 } 1047 /* Enable IRQ */ 1048 r = r600_irq_init(rdev); 1049 if (r) { 1050 DRM_ERROR("radeon: IH init failed (%d).\n", r); 1051 radeon_irq_kms_fini(rdev); 1052 return r; 1053 } 1054 r600_irq_set(rdev); 1055 1056 r = radeon_ring_init(rdev, rdev->cp.ring_size); 1057 if (r) 1058 return r; 1059 r = rv770_cp_load_microcode(rdev); 1060 if (r) 1061 return r; 1062 r = r600_cp_resume(rdev); 1063 if (r) 1064 return r; 1065 /* write back buffer are not vital so don't worry about failure */ 1066 r600_wb_enable(rdev); 1067 return 0; 1068} 1069 1070int rv770_resume(struct radeon_device *rdev) 1071{ 1072 int r; 1073 1074 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw, 1075 * posting will perform necessary task to bring back GPU into good 1076 * shape. 1077 */ 1078 /* post card */ 1079 atom_asic_init(rdev->mode_info.atom_context); 1080 1081 r = rv770_startup(rdev); 1082 if (r) { 1083 DRM_ERROR("r600 startup failed on resume\n"); 1084 return r; 1085 } 1086 1087 r = r600_ib_test(rdev); 1088 if (r) { 1089 DRM_ERROR("radeon: failled testing IB (%d).\n", r); 1090 return r; 1091 } 1092 1093 r = r600_audio_init(rdev); 1094 if (r) { 1095 dev_err(rdev->dev, "radeon: audio init failed\n"); 1096 return r; 1097 } 1098 1099 return r; 1100 1101} 1102 1103int rv770_suspend(struct radeon_device *rdev) 1104{ 1105 int r; 1106 1107 r600_audio_fini(rdev); 1108 r700_cp_stop(rdev); 1109 rdev->cp.ready = false; 1110 r600_irq_suspend(rdev); 1111 r600_wb_disable(rdev); 1112 rv770_pcie_gart_disable(rdev); 1113 /* unpin shaders bo */ 1114 if (rdev->r600_blit.shader_obj) { 1115 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); 1116 if (likely(r == 0)) { 1117 radeon_bo_unpin(rdev->r600_blit.shader_obj); 1118 radeon_bo_unreserve(rdev->r600_blit.shader_obj); 1119 } 1120 } 1121 return 0; 1122} 1123 1124/* Plan is to move initialization in that function and use 1125 * helper function so that radeon_device_init pretty much 1126 * do nothing more than calling asic specific function. This 1127 * should also allow to remove a bunch of callback function 1128 * like vram_info. 1129 */ 1130int rv770_init(struct radeon_device *rdev) 1131{ 1132 int r; 1133 1134 r = radeon_dummy_page_init(rdev); 1135 if (r) 1136 return r; 1137 /* This don't do much */ 1138 r = radeon_gem_init(rdev); 1139 if (r) 1140 return r; 1141 /* Read BIOS */ 1142 if (!radeon_get_bios(rdev)) { 1143 if (ASIC_IS_AVIVO(rdev)) 1144 return -EINVAL; 1145 } 1146 /* Must be an ATOMBIOS */ 1147 if (!rdev->is_atom_bios) { 1148 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); 1149 return -EINVAL; 1150 } 1151 r = radeon_atombios_init(rdev); 1152 if (r) 1153 return r; 1154 /* Post card if necessary */ 1155 if (!r600_card_posted(rdev)) { 1156 if (!rdev->bios) { 1157 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 1158 return -EINVAL; 1159 } 1160 DRM_INFO("GPU not posted. posting now...\n"); 1161 atom_asic_init(rdev->mode_info.atom_context); 1162 } 1163 /* Initialize scratch registers */ 1164 r600_scratch_init(rdev); 1165 /* Initialize surface registers */ 1166 radeon_surface_init(rdev); 1167 /* Initialize clocks */ 1168 radeon_get_clock_info(rdev->ddev); 1169 /* Fence driver */ 1170 r = radeon_fence_driver_init(rdev); 1171 if (r) 1172 return r; 1173 /* initialize AGP */ 1174 if (rdev->flags & RADEON_IS_AGP) { 1175 r = radeon_agp_init(rdev); 1176 if (r) 1177 radeon_agp_disable(rdev); 1178 } 1179 r = rv770_mc_init(rdev); 1180 if (r) 1181 return r; 1182 /* Memory manager */ 1183 r = radeon_bo_init(rdev); 1184 if (r) 1185 return r; 1186 1187 r = radeon_irq_kms_init(rdev); 1188 if (r) 1189 return r; 1190 1191 rdev->cp.ring_obj = NULL; 1192 r600_ring_init(rdev, 1024 * 1024); 1193 1194 rdev->ih.ring_obj = NULL; 1195 r600_ih_ring_init(rdev, 64 * 1024); 1196 1197 r = r600_pcie_gart_init(rdev); 1198 if (r) 1199 return r; 1200 1201 rdev->accel_working = true; 1202 r = rv770_startup(rdev); 1203 if (r) { 1204 dev_err(rdev->dev, "disabling GPU acceleration\n"); 1205 r700_cp_fini(rdev); 1206 r600_wb_fini(rdev); 1207 r600_irq_fini(rdev); 1208 radeon_irq_kms_fini(rdev); 1209 rv770_pcie_gart_fini(rdev); 1210 rdev->accel_working = false; 1211 } 1212 if (rdev->accel_working) { 1213 r = radeon_ib_pool_init(rdev); 1214 if (r) { 1215 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 1216 rdev->accel_working = false; 1217 } else { 1218 r = r600_ib_test(rdev); 1219 if (r) { 1220 dev_err(rdev->dev, "IB test failed (%d).\n", r); 1221 rdev->accel_working = false; 1222 } 1223 } 1224 } 1225 1226 r = r600_audio_init(rdev); 1227 if (r) { 1228 dev_err(rdev->dev, "radeon: audio init failed\n"); 1229 return r; 1230 } 1231 1232 return 0; 1233} 1234 1235void rv770_fini(struct radeon_device *rdev) 1236{ 1237 r600_blit_fini(rdev); 1238 r700_cp_fini(rdev); 1239 r600_wb_fini(rdev); 1240 r600_irq_fini(rdev); 1241 radeon_irq_kms_fini(rdev); 1242 rv770_pcie_gart_fini(rdev); 1243 rv770_vram_scratch_fini(rdev); 1244 radeon_gem_fini(rdev); 1245 radeon_fence_driver_fini(rdev); 1246 radeon_agp_fini(rdev); 1247 radeon_bo_fini(rdev); 1248 radeon_atombios_fini(rdev); 1249 kfree(rdev->bios); 1250 rdev->bios = NULL; 1251 radeon_dummy_page_fini(rdev); 1252} 1253