1/* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28#include <linux/console.h> 29#include <linux/slab.h> 30#include <drm/drmP.h> 31#include <drm/drm_crtc_helper.h> 32#include <drm/radeon_drm.h> 33#include <linux/vgaarb.h> 34#include <linux/vga_switcheroo.h> 35#include "radeon_reg.h" 36#include "radeon.h" 37#include "atom.h" 38 39static const char radeon_family_name[][16] = { 40 "R100", 41 "RV100", 42 "RS100", 43 "RV200", 44 "RS200", 45 "R200", 46 "RV250", 47 "RS300", 48 "RV280", 49 "R300", 50 "R350", 51 "RV350", 52 "RV380", 53 "R420", 54 "R423", 55 "RV410", 56 "RS400", 57 "RS480", 58 "RS600", 59 "RS690", 60 "RS740", 61 "RV515", 62 "R520", 63 "RV530", 64 "RV560", 65 "RV570", 66 "R580", 67 "R600", 68 "RV610", 69 "RV630", 70 "RV670", 71 "RV620", 72 "RV635", 73 "RS780", 74 "RS880", 75 "RV770", 76 "RV730", 77 "RV710", 78 "RV740", 79 "CEDAR", 80 "REDWOOD", 81 "JUNIPER", 82 "CYPRESS", 83 "HEMLOCK", 84 "LAST", 85}; 86 87/* 88 * Clear GPU surface registers. 89 */ 90void radeon_surface_init(struct radeon_device *rdev) 91{ 92 if (rdev->family < CHIP_R600) { 93 int i; 94 95 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { 96 if (rdev->surface_regs[i].bo) 97 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo); 98 else 99 radeon_clear_surface_reg(rdev, i); 100 } 101 /* enable surfaces */ 102 WREG32(RADEON_SURFACE_CNTL, 0); 103 } 104} 105 106/* 107 * GPU scratch registers helpers function. 108 */ 109void radeon_scratch_init(struct radeon_device *rdev) 110{ 111 int i; 112 113 if (rdev->family < CHIP_R300) { 114 rdev->scratch.num_reg = 5; 115 } else { 116 rdev->scratch.num_reg = 7; 117 } 118 for (i = 0; i < rdev->scratch.num_reg; i++) { 119 rdev->scratch.free[i] = true; 120 rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4); 121 } 122} 123 124int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) 125{ 126 int i; 127 128 for (i = 0; i < rdev->scratch.num_reg; i++) { 129 if (rdev->scratch.free[i]) { 130 rdev->scratch.free[i] = false; 131 *reg = rdev->scratch.reg[i]; 132 return 0; 133 } 134 } 135 return -EINVAL; 136} 137 138void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) 139{ 140 int i; 141 142 for (i = 0; i < rdev->scratch.num_reg; i++) { 143 if (rdev->scratch.reg[i] == reg) { 144 rdev->scratch.free[i] = true; 145 return; 146 } 147 } 148} 149 150void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base) 151{ 152 mc->vram_start = base; 153 if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) { 154 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); 155 mc->real_vram_size = mc->aper_size; 156 mc->mc_vram_size = mc->aper_size; 157 } 158 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 159 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) { 160 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); 161 mc->real_vram_size = mc->aper_size; 162 mc->mc_vram_size = mc->aper_size; 163 } 164 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 165 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", 166 mc->mc_vram_size >> 20, mc->vram_start, 167 mc->vram_end, mc->real_vram_size >> 20); 168} 169 170void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 171{ 172 u64 size_af, size_bf; 173 174 size_af = ((0xFFFFFFFF - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; 175 size_bf = mc->vram_start & ~mc->gtt_base_align; 176 if (size_bf > size_af) { 177 if (mc->gtt_size > size_bf) { 178 dev_warn(rdev->dev, "limiting GTT\n"); 179 mc->gtt_size = size_bf; 180 } 181 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size; 182 } else { 183 if (mc->gtt_size > size_af) { 184 dev_warn(rdev->dev, "limiting GTT\n"); 185 mc->gtt_size = size_af; 186 } 187 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align; 188 } 189 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; 190 dev_info(rdev->dev, "GTT: %lluM 0x%08llX - 0x%08llX\n", 191 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); 192} 193 194/* 195 * GPU helpers function. 196 */ 197bool radeon_card_posted(struct radeon_device *rdev) 198{ 199 uint32_t reg; 200 201 /* first check CRTCs */ 202 if (ASIC_IS_DCE4(rdev)) { 203 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | 204 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) | 205 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | 206 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) | 207 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | 208 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); 209 if (reg & EVERGREEN_CRTC_MASTER_EN) 210 return true; 211 } else if (ASIC_IS_AVIVO(rdev)) { 212 reg = RREG32(AVIVO_D1CRTC_CONTROL) | 213 RREG32(AVIVO_D2CRTC_CONTROL); 214 if (reg & AVIVO_CRTC_EN) { 215 return true; 216 } 217 } else { 218 reg = RREG32(RADEON_CRTC_GEN_CNTL) | 219 RREG32(RADEON_CRTC2_GEN_CNTL); 220 if (reg & RADEON_CRTC_EN) { 221 return true; 222 } 223 } 224 225 /* then check MEM_SIZE, in case the crtcs are off */ 226 if (rdev->family >= CHIP_R600) 227 reg = RREG32(R600_CONFIG_MEMSIZE); 228 else 229 reg = RREG32(RADEON_CONFIG_MEMSIZE); 230 231 if (reg) 232 return true; 233 234 return false; 235 236} 237 238void radeon_update_bandwidth_info(struct radeon_device *rdev) 239{ 240 fixed20_12 a; 241 u32 sclk = rdev->pm.current_sclk; 242 u32 mclk = rdev->pm.current_mclk; 243 244 /* sclk/mclk in Mhz */ 245 a.full = dfixed_const(100); 246 rdev->pm.sclk.full = dfixed_const(sclk); 247 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a); 248 rdev->pm.mclk.full = dfixed_const(mclk); 249 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a); 250 251 if (rdev->flags & RADEON_IS_IGP) { 252 a.full = dfixed_const(16); 253 /* core_bandwidth = sclk(Mhz) * 16 */ 254 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); 255 } 256} 257 258bool radeon_boot_test_post_card(struct radeon_device *rdev) 259{ 260 if (radeon_card_posted(rdev)) 261 return true; 262 263 if (rdev->bios) { 264 DRM_INFO("GPU not posted. posting now...\n"); 265 if (rdev->is_atom_bios) 266 atom_asic_init(rdev->mode_info.atom_context); 267 else 268 radeon_combios_asic_init(rdev->ddev); 269 return true; 270 } else { 271 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 272 return false; 273 } 274} 275 276int radeon_dummy_page_init(struct radeon_device *rdev) 277{ 278 if (rdev->dummy_page.page) 279 return 0; 280 rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO); 281 if (rdev->dummy_page.page == NULL) 282 return -ENOMEM; 283 rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page, 284 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 285 if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) { 286 dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n"); 287 __free_page(rdev->dummy_page.page); 288 rdev->dummy_page.page = NULL; 289 return -ENOMEM; 290 } 291 return 0; 292} 293 294void radeon_dummy_page_fini(struct radeon_device *rdev) 295{ 296 if (rdev->dummy_page.page == NULL) 297 return; 298 pci_unmap_page(rdev->pdev, rdev->dummy_page.addr, 299 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 300 __free_page(rdev->dummy_page.page); 301 rdev->dummy_page.page = NULL; 302} 303 304 305/* ATOM accessor methods */ 306static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) 307{ 308 struct radeon_device *rdev = info->dev->dev_private; 309 uint32_t r; 310 311 r = rdev->pll_rreg(rdev, reg); 312 return r; 313} 314 315static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) 316{ 317 struct radeon_device *rdev = info->dev->dev_private; 318 319 rdev->pll_wreg(rdev, reg, val); 320} 321 322static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) 323{ 324 struct radeon_device *rdev = info->dev->dev_private; 325 uint32_t r; 326 327 r = rdev->mc_rreg(rdev, reg); 328 return r; 329} 330 331static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) 332{ 333 struct radeon_device *rdev = info->dev->dev_private; 334 335 rdev->mc_wreg(rdev, reg, val); 336} 337 338static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) 339{ 340 struct radeon_device *rdev = info->dev->dev_private; 341 342 WREG32(reg*4, val); 343} 344 345static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) 346{ 347 struct radeon_device *rdev = info->dev->dev_private; 348 uint32_t r; 349 350 r = RREG32(reg*4); 351 return r; 352} 353 354static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) 355{ 356 struct radeon_device *rdev = info->dev->dev_private; 357 358 WREG32_IO(reg*4, val); 359} 360 361static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) 362{ 363 struct radeon_device *rdev = info->dev->dev_private; 364 uint32_t r; 365 366 r = RREG32_IO(reg*4); 367 return r; 368} 369 370int radeon_atombios_init(struct radeon_device *rdev) 371{ 372 struct card_info *atom_card_info = 373 kzalloc(sizeof(struct card_info), GFP_KERNEL); 374 375 if (!atom_card_info) 376 return -ENOMEM; 377 378 rdev->mode_info.atom_card_info = atom_card_info; 379 atom_card_info->dev = rdev->ddev; 380 atom_card_info->reg_read = cail_reg_read; 381 atom_card_info->reg_write = cail_reg_write; 382 /* needed for iio ops */ 383 if (rdev->rio_mem) { 384 atom_card_info->ioreg_read = cail_ioreg_read; 385 atom_card_info->ioreg_write = cail_ioreg_write; 386 } else { 387 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n"); 388 atom_card_info->ioreg_read = cail_reg_read; 389 atom_card_info->ioreg_write = cail_reg_write; 390 } 391 atom_card_info->mc_read = cail_mc_read; 392 atom_card_info->mc_write = cail_mc_write; 393 atom_card_info->pll_read = cail_pll_read; 394 atom_card_info->pll_write = cail_pll_write; 395 396 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios); 397 mutex_init(&rdev->mode_info.atom_context->mutex); 398 radeon_atom_initialize_bios_scratch_regs(rdev->ddev); 399 atom_allocate_fb_scratch(rdev->mode_info.atom_context); 400 return 0; 401} 402 403void radeon_atombios_fini(struct radeon_device *rdev) 404{ 405 if (rdev->mode_info.atom_context) { 406 kfree(rdev->mode_info.atom_context->scratch); 407 kfree(rdev->mode_info.atom_context); 408 } 409 kfree(rdev->mode_info.atom_card_info); 410} 411 412int radeon_combios_init(struct radeon_device *rdev) 413{ 414 radeon_combios_initialize_bios_scratch_regs(rdev->ddev); 415 return 0; 416} 417 418void radeon_combios_fini(struct radeon_device *rdev) 419{ 420} 421 422/* if we get transitioned to only one device, tak VGA back */ 423static unsigned int radeon_vga_set_decode(void *cookie, bool state) 424{ 425 struct radeon_device *rdev = cookie; 426 radeon_vga_set_state(rdev, state); 427 if (state) 428 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | 429 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 430 else 431 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 432} 433 434void radeon_check_arguments(struct radeon_device *rdev) 435{ 436 /* vramlimit must be a power of two */ 437 switch (radeon_vram_limit) { 438 case 0: 439 case 4: 440 case 8: 441 case 16: 442 case 32: 443 case 64: 444 case 128: 445 case 256: 446 case 512: 447 case 1024: 448 case 2048: 449 case 4096: 450 break; 451 default: 452 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n", 453 radeon_vram_limit); 454 radeon_vram_limit = 0; 455 break; 456 } 457 radeon_vram_limit = radeon_vram_limit << 20; 458 /* gtt size must be power of two and greater or equal to 32M */ 459 switch (radeon_gart_size) { 460 case 4: 461 case 8: 462 case 16: 463 dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n", 464 radeon_gart_size); 465 radeon_gart_size = 512; 466 break; 467 case 32: 468 case 64: 469 case 128: 470 case 256: 471 case 512: 472 case 1024: 473 case 2048: 474 case 4096: 475 break; 476 default: 477 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n", 478 radeon_gart_size); 479 radeon_gart_size = 512; 480 break; 481 } 482 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; 483 /* AGP mode can only be -1, 1, 2, 4, 8 */ 484 switch (radeon_agpmode) { 485 case -1: 486 case 0: 487 case 1: 488 case 2: 489 case 4: 490 case 8: 491 break; 492 default: 493 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: " 494 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode); 495 radeon_agpmode = 0; 496 break; 497 } 498} 499 500static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) 501{ 502 struct drm_device *dev = pci_get_drvdata(pdev); 503 struct radeon_device *rdev = dev->dev_private; 504 pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; 505 if (state == VGA_SWITCHEROO_ON) { 506 printk(KERN_INFO "radeon: switched on\n"); 507 /* don't suspend or resume card normally */ 508 rdev->powered_down = false; 509 radeon_resume_kms(dev); 510 drm_kms_helper_poll_enable(dev); 511 } else { 512 printk(KERN_INFO "radeon: switched off\n"); 513 drm_kms_helper_poll_disable(dev); 514 radeon_suspend_kms(dev, pmm); 515 /* don't suspend or resume card normally */ 516 rdev->powered_down = true; 517 } 518} 519 520static bool radeon_switcheroo_can_switch(struct pci_dev *pdev) 521{ 522 struct drm_device *dev = pci_get_drvdata(pdev); 523 bool can_switch; 524 525 spin_lock(&dev->count_lock); 526 can_switch = (dev->open_count == 0); 527 spin_unlock(&dev->count_lock); 528 return can_switch; 529} 530 531 532int radeon_device_init(struct radeon_device *rdev, 533 struct drm_device *ddev, 534 struct pci_dev *pdev, 535 uint32_t flags) 536{ 537 int r, i; 538 int dma_bits; 539 540 rdev->shutdown = false; 541 rdev->dev = &pdev->dev; 542 rdev->ddev = ddev; 543 rdev->pdev = pdev; 544 rdev->flags = flags; 545 rdev->family = flags & RADEON_FAMILY_MASK; 546 rdev->is_atom_bios = false; 547 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; 548 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; 549 rdev->gpu_lockup = false; 550 rdev->accel_working = false; 551 552 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X).\n", 553 radeon_family_name[rdev->family], pdev->vendor, pdev->device); 554 555 /* mutex initialization are all done here so we 556 * can recall function without having locking issues */ 557 mutex_init(&rdev->cs_mutex); 558 mutex_init(&rdev->ib_pool.mutex); 559 mutex_init(&rdev->cp.mutex); 560 mutex_init(&rdev->dc_hw_i2c_mutex); 561 if (rdev->family >= CHIP_R600) 562 spin_lock_init(&rdev->ih.lock); 563 mutex_init(&rdev->gem.mutex); 564 mutex_init(&rdev->pm.mutex); 565 mutex_init(&rdev->vram_mutex); 566 rwlock_init(&rdev->fence_drv.lock); 567 INIT_LIST_HEAD(&rdev->gem.objects); 568 init_waitqueue_head(&rdev->irq.vblank_queue); 569 init_waitqueue_head(&rdev->irq.idle_queue); 570 571 /* setup workqueue */ 572 rdev->wq = create_workqueue("radeon"); 573 if (rdev->wq == NULL) 574 return -ENOMEM; 575 576 /* Set asic functions */ 577 r = radeon_asic_init(rdev); 578 if (r) 579 return r; 580 radeon_check_arguments(rdev); 581 582 /* all of the newer IGP chips have an internal gart 583 * However some rs4xx report as AGP, so remove that here. 584 */ 585 if ((rdev->family >= CHIP_RS400) && 586 (rdev->flags & RADEON_IS_IGP)) { 587 rdev->flags &= ~RADEON_IS_AGP; 588 } 589 590 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) { 591 radeon_agp_disable(rdev); 592 } 593 594 /* set DMA mask + need_dma32 flags. 595 * PCIE - can handle 40-bits. 596 * IGP - can handle 40-bits (in theory) 597 * AGP - generally dma32 is safest 598 * PCI - only dma32 599 */ 600 rdev->need_dma32 = false; 601 if (rdev->flags & RADEON_IS_AGP) 602 rdev->need_dma32 = true; 603 if (rdev->flags & RADEON_IS_PCI) 604 rdev->need_dma32 = true; 605 606 dma_bits = rdev->need_dma32 ? 32 : 40; 607 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); 608 if (r) { 609 printk(KERN_WARNING "radeon: No suitable DMA available.\n"); 610 } 611 612 /* Registers mapping */ 613 /* TODO: block userspace mapping of io register */ 614 rdev->rmmio_base = pci_resource_start(rdev->pdev, 2); 615 rdev->rmmio_size = pci_resource_len(rdev->pdev, 2); 616 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size); 617 if (rdev->rmmio == NULL) { 618 return -ENOMEM; 619 } 620 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); 621 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); 622 623 /* io port mapping */ 624 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 625 if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) { 626 rdev->rio_mem_size = pci_resource_len(rdev->pdev, i); 627 rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size); 628 break; 629 } 630 } 631 if (rdev->rio_mem == NULL) 632 DRM_ERROR("Unable to find PCI I/O BAR\n"); 633 634 /* if we have > 1 VGA cards, then disable the radeon VGA resources */ 635 /* this will fail for cards that aren't VGA class devices, just 636 * ignore it */ 637 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode); 638 vga_switcheroo_register_client(rdev->pdev, 639 radeon_switcheroo_set_state, 640 radeon_switcheroo_can_switch); 641 642 r = radeon_init(rdev); 643 if (r) 644 return r; 645 646 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) { 647 /* Acceleration not working on AGP card try again 648 * with fallback to PCI or PCIE GART 649 */ 650 radeon_asic_reset(rdev); 651 radeon_fini(rdev); 652 radeon_agp_disable(rdev); 653 r = radeon_init(rdev); 654 if (r) 655 return r; 656 } 657 if (radeon_testing) { 658 radeon_test_moves(rdev); 659 } 660 if (radeon_benchmarking) { 661 radeon_benchmark(rdev); 662 } 663 return 0; 664} 665 666void radeon_device_fini(struct radeon_device *rdev) 667{ 668 DRM_INFO("radeon: finishing device.\n"); 669 rdev->shutdown = true; 670 /* evict vram memory */ 671 radeon_bo_evict_vram(rdev); 672 radeon_fini(rdev); 673 destroy_workqueue(rdev->wq); 674 vga_switcheroo_unregister_client(rdev->pdev); 675 vga_client_register(rdev->pdev, NULL, NULL, NULL); 676 if (rdev->rio_mem) 677 pci_iounmap(rdev->pdev, rdev->rio_mem); 678 rdev->rio_mem = NULL; 679 iounmap(rdev->rmmio); 680 rdev->rmmio = NULL; 681} 682 683 684/* 685 * Suspend & resume. 686 */ 687int radeon_suspend_kms(struct drm_device *dev, pm_message_t state) 688{ 689 struct radeon_device *rdev; 690 struct drm_crtc *crtc; 691 struct drm_connector *connector; 692 int r; 693 694 if (dev == NULL || dev->dev_private == NULL) { 695 return -ENODEV; 696 } 697 if (state.event == PM_EVENT_PRETHAW) { 698 return 0; 699 } 700 rdev = dev->dev_private; 701 702 if (rdev->powered_down) 703 return 0; 704 705 /* turn off display hw */ 706 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 707 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 708 } 709 710 /* unpin the front buffers */ 711 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 712 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb); 713 struct radeon_bo *robj; 714 715 if (rfb == NULL || rfb->obj == NULL) { 716 continue; 717 } 718 robj = rfb->obj->driver_private; 719 /* don't unpin kernel fb objects */ 720 if (!radeon_fbdev_robj_is_fb(rdev, robj)) { 721 r = radeon_bo_reserve(robj, false); 722 if (r == 0) { 723 radeon_bo_unpin(robj); 724 radeon_bo_unreserve(robj); 725 } 726 } 727 } 728 /* evict vram memory */ 729 radeon_bo_evict_vram(rdev); 730 /* wait for gpu to finish processing current batch */ 731 radeon_fence_wait_last(rdev); 732 733 radeon_save_bios_scratch_regs(rdev); 734 735 radeon_pm_suspend(rdev); 736 radeon_suspend(rdev); 737 radeon_hpd_fini(rdev); 738 /* evict remaining vram memory */ 739 radeon_bo_evict_vram(rdev); 740 741 radeon_agp_suspend(rdev); 742 743 pci_save_state(dev->pdev); 744 if (state.event == PM_EVENT_SUSPEND) { 745 /* Shut down the device */ 746 pci_disable_device(dev->pdev); 747 pci_set_power_state(dev->pdev, PCI_D3hot); 748 } 749 acquire_console_sem(); 750 radeon_fbdev_set_suspend(rdev, 1); 751 release_console_sem(); 752 return 0; 753} 754 755int radeon_resume_kms(struct drm_device *dev) 756{ 757 struct drm_connector *connector; 758 struct radeon_device *rdev = dev->dev_private; 759 760 if (rdev->powered_down) 761 return 0; 762 763 acquire_console_sem(); 764 pci_set_power_state(dev->pdev, PCI_D0); 765 pci_restore_state(dev->pdev); 766 if (pci_enable_device(dev->pdev)) { 767 release_console_sem(); 768 return -1; 769 } 770 pci_set_master(dev->pdev); 771 /* resume AGP if in use */ 772 radeon_agp_resume(rdev); 773 radeon_resume(rdev); 774 radeon_pm_resume(rdev); 775 radeon_restore_bios_scratch_regs(rdev); 776 777 radeon_fbdev_set_suspend(rdev, 0); 778 release_console_sem(); 779 780 /* reset hpd state */ 781 radeon_hpd_init(rdev); 782 /* blat the mode back in */ 783 drm_helper_resume_force_mode(dev); 784 /* turn on display hw */ 785 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 786 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 787 } 788 return 0; 789} 790 791int radeon_gpu_reset(struct radeon_device *rdev) 792{ 793 int r; 794 795 radeon_save_bios_scratch_regs(rdev); 796 radeon_suspend(rdev); 797 798 r = radeon_asic_reset(rdev); 799 if (!r) { 800 dev_info(rdev->dev, "GPU reset succeed\n"); 801 radeon_resume(rdev); 802 radeon_restore_bios_scratch_regs(rdev); 803 drm_helper_resume_force_mode(rdev->ddev); 804 return 0; 805 } 806 /* bad news, how to tell it to userspace ? */ 807 dev_info(rdev->dev, "GPU reset failed\n"); 808 return r; 809} 810 811 812/* 813 * Debugfs 814 */ 815struct radeon_debugfs { 816 struct drm_info_list *files; 817 unsigned num_files; 818}; 819static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_NUM_FILES]; 820static unsigned _radeon_debugfs_count = 0; 821 822int radeon_debugfs_add_files(struct radeon_device *rdev, 823 struct drm_info_list *files, 824 unsigned nfiles) 825{ 826 unsigned i; 827 828 for (i = 0; i < _radeon_debugfs_count; i++) { 829 if (_radeon_debugfs[i].files == files) { 830 /* Already registered */ 831 return 0; 832 } 833 } 834 if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) { 835 DRM_ERROR("Reached maximum number of debugfs files.\n"); 836 DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n"); 837 return -EINVAL; 838 } 839 _radeon_debugfs[_radeon_debugfs_count].files = files; 840 _radeon_debugfs[_radeon_debugfs_count].num_files = nfiles; 841 _radeon_debugfs_count++; 842#if defined(CONFIG_DEBUG_FS) 843 drm_debugfs_create_files(files, nfiles, 844 rdev->ddev->control->debugfs_root, 845 rdev->ddev->control); 846 drm_debugfs_create_files(files, nfiles, 847 rdev->ddev->primary->debugfs_root, 848 rdev->ddev->primary); 849#endif 850 return 0; 851} 852 853#if defined(CONFIG_DEBUG_FS) 854int radeon_debugfs_init(struct drm_minor *minor) 855{ 856 return 0; 857} 858 859void radeon_debugfs_cleanup(struct drm_minor *minor) 860{ 861 unsigned i; 862 863 for (i = 0; i < _radeon_debugfs_count; i++) { 864 drm_debugfs_remove_files(_radeon_debugfs[i].files, 865 _radeon_debugfs[i].num_files, minor); 866 } 867} 868#endif 869