1/* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29#include <linux/console.h> 30#include <drm/drmP.h> 31#include <drm/drm_crtc_helper.h> 32#include <drm/radeon_drm.h> 33#include <linux/vgaarb.h> 34#include <linux/vga_switcheroo.h> 35#include "radeon_reg.h" 36#include "radeon.h" 37#include "radeon_asic.h" 38#include "atom.h" 39 40/* 41 * Registers accessors functions. 42 */ 43static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) 44{ 45 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); 46 BUG_ON(1); 47 return 0; 48} 49 50static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 51{ 52 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", 53 reg, v); 54 BUG_ON(1); 55} 56 57static void radeon_register_accessor_init(struct radeon_device *rdev) 58{ 59 rdev->mc_rreg = &radeon_invalid_rreg; 60 rdev->mc_wreg = &radeon_invalid_wreg; 61 rdev->pll_rreg = &radeon_invalid_rreg; 62 rdev->pll_wreg = &radeon_invalid_wreg; 63 rdev->pciep_rreg = &radeon_invalid_rreg; 64 rdev->pciep_wreg = &radeon_invalid_wreg; 65 66 /* Don't change order as we are overridding accessor. */ 67 if (rdev->family < CHIP_RV515) { 68 rdev->pcie_reg_mask = 0xff; 69 } else { 70 rdev->pcie_reg_mask = 0x7ff; 71 } 72 if (rdev->family <= CHIP_R580) { 73 rdev->pll_rreg = &r100_pll_rreg; 74 rdev->pll_wreg = &r100_pll_wreg; 75 } 76 if (rdev->family >= CHIP_R420) { 77 rdev->mc_rreg = &r420_mc_rreg; 78 rdev->mc_wreg = &r420_mc_wreg; 79 } 80 if (rdev->family >= CHIP_RV515) { 81 rdev->mc_rreg = &rv515_mc_rreg; 82 rdev->mc_wreg = &rv515_mc_wreg; 83 } 84 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { 85 rdev->mc_rreg = &rs400_mc_rreg; 86 rdev->mc_wreg = &rs400_mc_wreg; 87 } 88 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { 89 rdev->mc_rreg = &rs690_mc_rreg; 90 rdev->mc_wreg = &rs690_mc_wreg; 91 } 92 if (rdev->family == CHIP_RS600) { 93 rdev->mc_rreg = &rs600_mc_rreg; 94 rdev->mc_wreg = &rs600_mc_wreg; 95 } 96 if ((rdev->family >= CHIP_R600) && (rdev->family <= CHIP_RV740)) { 97 rdev->pciep_rreg = &r600_pciep_rreg; 98 rdev->pciep_wreg = &r600_pciep_wreg; 99 } 100} 101 102 103/* helper to disable agp */ 104void radeon_agp_disable(struct radeon_device *rdev) 105{ 106 rdev->flags &= ~RADEON_IS_AGP; 107 if (rdev->family >= CHIP_R600) { 108 DRM_INFO("Forcing AGP to PCIE mode\n"); 109 rdev->flags |= RADEON_IS_PCIE; 110 } else if (rdev->family >= CHIP_RV515 || 111 rdev->family == CHIP_RV380 || 112 rdev->family == CHIP_RV410 || 113 rdev->family == CHIP_R423) { 114 DRM_INFO("Forcing AGP to PCIE mode\n"); 115 rdev->flags |= RADEON_IS_PCIE; 116 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; 117 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; 118 } else { 119 DRM_INFO("Forcing AGP to PCI mode\n"); 120 rdev->flags |= RADEON_IS_PCI; 121 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush; 122 rdev->asic->gart_set_page = &r100_pci_gart_set_page; 123 } 124 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; 125} 126 127/* 128 * ASIC 129 */ 130static struct radeon_asic r100_asic = { 131 .init = &r100_init, 132 .fini = &r100_fini, 133 .suspend = &r100_suspend, 134 .resume = &r100_resume, 135 .vga_set_state = &r100_vga_set_state, 136 .gpu_is_lockup = &r100_gpu_is_lockup, 137 .asic_reset = &r100_asic_reset, 138 .gart_tlb_flush = &r100_pci_gart_tlb_flush, 139 .gart_set_page = &r100_pci_gart_set_page, 140 .cp_commit = &r100_cp_commit, 141 .ring_start = &r100_ring_start, 142 .ring_test = &r100_ring_test, 143 .ring_ib_execute = &r100_ring_ib_execute, 144 .irq_set = &r100_irq_set, 145 .irq_process = &r100_irq_process, 146 .get_vblank_counter = &r100_get_vblank_counter, 147 .fence_ring_emit = &r100_fence_ring_emit, 148 .cs_parse = &r100_cs_parse, 149 .copy_blit = &r100_copy_blit, 150 .copy_dma = NULL, 151 .copy = &r100_copy_blit, 152 .get_engine_clock = &radeon_legacy_get_engine_clock, 153 .set_engine_clock = &radeon_legacy_set_engine_clock, 154 .get_memory_clock = &radeon_legacy_get_memory_clock, 155 .set_memory_clock = NULL, 156 .get_pcie_lanes = NULL, 157 .set_pcie_lanes = NULL, 158 .set_clock_gating = &radeon_legacy_set_clock_gating, 159 .set_surface_reg = r100_set_surface_reg, 160 .clear_surface_reg = r100_clear_surface_reg, 161 .bandwidth_update = &r100_bandwidth_update, 162 .hpd_init = &r100_hpd_init, 163 .hpd_fini = &r100_hpd_fini, 164 .hpd_sense = &r100_hpd_sense, 165 .hpd_set_polarity = &r100_hpd_set_polarity, 166 .ioctl_wait_idle = NULL, 167 .gui_idle = &r100_gui_idle, 168 .pm_misc = &r100_pm_misc, 169 .pm_prepare = &r100_pm_prepare, 170 .pm_finish = &r100_pm_finish, 171 .pm_init_profile = &r100_pm_init_profile, 172 .pm_get_dynpm_state = &r100_pm_get_dynpm_state, 173}; 174 175static struct radeon_asic r200_asic = { 176 .init = &r100_init, 177 .fini = &r100_fini, 178 .suspend = &r100_suspend, 179 .resume = &r100_resume, 180 .vga_set_state = &r100_vga_set_state, 181 .gpu_is_lockup = &r100_gpu_is_lockup, 182 .asic_reset = &r100_asic_reset, 183 .gart_tlb_flush = &r100_pci_gart_tlb_flush, 184 .gart_set_page = &r100_pci_gart_set_page, 185 .cp_commit = &r100_cp_commit, 186 .ring_start = &r100_ring_start, 187 .ring_test = &r100_ring_test, 188 .ring_ib_execute = &r100_ring_ib_execute, 189 .irq_set = &r100_irq_set, 190 .irq_process = &r100_irq_process, 191 .get_vblank_counter = &r100_get_vblank_counter, 192 .fence_ring_emit = &r100_fence_ring_emit, 193 .cs_parse = &r100_cs_parse, 194 .copy_blit = &r100_copy_blit, 195 .copy_dma = &r200_copy_dma, 196 .copy = &r100_copy_blit, 197 .get_engine_clock = &radeon_legacy_get_engine_clock, 198 .set_engine_clock = &radeon_legacy_set_engine_clock, 199 .get_memory_clock = &radeon_legacy_get_memory_clock, 200 .set_memory_clock = NULL, 201 .set_pcie_lanes = NULL, 202 .set_clock_gating = &radeon_legacy_set_clock_gating, 203 .set_surface_reg = r100_set_surface_reg, 204 .clear_surface_reg = r100_clear_surface_reg, 205 .bandwidth_update = &r100_bandwidth_update, 206 .hpd_init = &r100_hpd_init, 207 .hpd_fini = &r100_hpd_fini, 208 .hpd_sense = &r100_hpd_sense, 209 .hpd_set_polarity = &r100_hpd_set_polarity, 210 .ioctl_wait_idle = NULL, 211 .gui_idle = &r100_gui_idle, 212 .pm_misc = &r100_pm_misc, 213 .pm_prepare = &r100_pm_prepare, 214 .pm_finish = &r100_pm_finish, 215 .pm_init_profile = &r100_pm_init_profile, 216 .pm_get_dynpm_state = &r100_pm_get_dynpm_state, 217}; 218 219static struct radeon_asic r300_asic = { 220 .init = &r300_init, 221 .fini = &r300_fini, 222 .suspend = &r300_suspend, 223 .resume = &r300_resume, 224 .vga_set_state = &r100_vga_set_state, 225 .gpu_is_lockup = &r300_gpu_is_lockup, 226 .asic_reset = &r300_asic_reset, 227 .gart_tlb_flush = &r100_pci_gart_tlb_flush, 228 .gart_set_page = &r100_pci_gart_set_page, 229 .cp_commit = &r100_cp_commit, 230 .ring_start = &r300_ring_start, 231 .ring_test = &r100_ring_test, 232 .ring_ib_execute = &r100_ring_ib_execute, 233 .irq_set = &r100_irq_set, 234 .irq_process = &r100_irq_process, 235 .get_vblank_counter = &r100_get_vblank_counter, 236 .fence_ring_emit = &r300_fence_ring_emit, 237 .cs_parse = &r300_cs_parse, 238 .copy_blit = &r100_copy_blit, 239 .copy_dma = &r200_copy_dma, 240 .copy = &r100_copy_blit, 241 .get_engine_clock = &radeon_legacy_get_engine_clock, 242 .set_engine_clock = &radeon_legacy_set_engine_clock, 243 .get_memory_clock = &radeon_legacy_get_memory_clock, 244 .set_memory_clock = NULL, 245 .get_pcie_lanes = &rv370_get_pcie_lanes, 246 .set_pcie_lanes = &rv370_set_pcie_lanes, 247 .set_clock_gating = &radeon_legacy_set_clock_gating, 248 .set_surface_reg = r100_set_surface_reg, 249 .clear_surface_reg = r100_clear_surface_reg, 250 .bandwidth_update = &r100_bandwidth_update, 251 .hpd_init = &r100_hpd_init, 252 .hpd_fini = &r100_hpd_fini, 253 .hpd_sense = &r100_hpd_sense, 254 .hpd_set_polarity = &r100_hpd_set_polarity, 255 .ioctl_wait_idle = NULL, 256 .gui_idle = &r100_gui_idle, 257 .pm_misc = &r100_pm_misc, 258 .pm_prepare = &r100_pm_prepare, 259 .pm_finish = &r100_pm_finish, 260 .pm_init_profile = &r100_pm_init_profile, 261 .pm_get_dynpm_state = &r100_pm_get_dynpm_state, 262}; 263 264static struct radeon_asic r300_asic_pcie = { 265 .init = &r300_init, 266 .fini = &r300_fini, 267 .suspend = &r300_suspend, 268 .resume = &r300_resume, 269 .vga_set_state = &r100_vga_set_state, 270 .gpu_is_lockup = &r300_gpu_is_lockup, 271 .asic_reset = &r300_asic_reset, 272 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, 273 .gart_set_page = &rv370_pcie_gart_set_page, 274 .cp_commit = &r100_cp_commit, 275 .ring_start = &r300_ring_start, 276 .ring_test = &r100_ring_test, 277 .ring_ib_execute = &r100_ring_ib_execute, 278 .irq_set = &r100_irq_set, 279 .irq_process = &r100_irq_process, 280 .get_vblank_counter = &r100_get_vblank_counter, 281 .fence_ring_emit = &r300_fence_ring_emit, 282 .cs_parse = &r300_cs_parse, 283 .copy_blit = &r100_copy_blit, 284 .copy_dma = &r200_copy_dma, 285 .copy = &r100_copy_blit, 286 .get_engine_clock = &radeon_legacy_get_engine_clock, 287 .set_engine_clock = &radeon_legacy_set_engine_clock, 288 .get_memory_clock = &radeon_legacy_get_memory_clock, 289 .set_memory_clock = NULL, 290 .set_pcie_lanes = &rv370_set_pcie_lanes, 291 .set_clock_gating = &radeon_legacy_set_clock_gating, 292 .set_surface_reg = r100_set_surface_reg, 293 .clear_surface_reg = r100_clear_surface_reg, 294 .bandwidth_update = &r100_bandwidth_update, 295 .hpd_init = &r100_hpd_init, 296 .hpd_fini = &r100_hpd_fini, 297 .hpd_sense = &r100_hpd_sense, 298 .hpd_set_polarity = &r100_hpd_set_polarity, 299 .ioctl_wait_idle = NULL, 300 .gui_idle = &r100_gui_idle, 301 .pm_misc = &r100_pm_misc, 302 .pm_prepare = &r100_pm_prepare, 303 .pm_finish = &r100_pm_finish, 304 .pm_init_profile = &r100_pm_init_profile, 305 .pm_get_dynpm_state = &r100_pm_get_dynpm_state, 306}; 307 308static struct radeon_asic r420_asic = { 309 .init = &r420_init, 310 .fini = &r420_fini, 311 .suspend = &r420_suspend, 312 .resume = &r420_resume, 313 .vga_set_state = &r100_vga_set_state, 314 .gpu_is_lockup = &r300_gpu_is_lockup, 315 .asic_reset = &r300_asic_reset, 316 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, 317 .gart_set_page = &rv370_pcie_gart_set_page, 318 .cp_commit = &r100_cp_commit, 319 .ring_start = &r300_ring_start, 320 .ring_test = &r100_ring_test, 321 .ring_ib_execute = &r100_ring_ib_execute, 322 .irq_set = &r100_irq_set, 323 .irq_process = &r100_irq_process, 324 .get_vblank_counter = &r100_get_vblank_counter, 325 .fence_ring_emit = &r300_fence_ring_emit, 326 .cs_parse = &r300_cs_parse, 327 .copy_blit = &r100_copy_blit, 328 .copy_dma = &r200_copy_dma, 329 .copy = &r100_copy_blit, 330 .get_engine_clock = &radeon_atom_get_engine_clock, 331 .set_engine_clock = &radeon_atom_set_engine_clock, 332 .get_memory_clock = &radeon_atom_get_memory_clock, 333 .set_memory_clock = &radeon_atom_set_memory_clock, 334 .get_pcie_lanes = &rv370_get_pcie_lanes, 335 .set_pcie_lanes = &rv370_set_pcie_lanes, 336 .set_clock_gating = &radeon_atom_set_clock_gating, 337 .set_surface_reg = r100_set_surface_reg, 338 .clear_surface_reg = r100_clear_surface_reg, 339 .bandwidth_update = &r100_bandwidth_update, 340 .hpd_init = &r100_hpd_init, 341 .hpd_fini = &r100_hpd_fini, 342 .hpd_sense = &r100_hpd_sense, 343 .hpd_set_polarity = &r100_hpd_set_polarity, 344 .ioctl_wait_idle = NULL, 345 .gui_idle = &r100_gui_idle, 346 .pm_misc = &r100_pm_misc, 347 .pm_prepare = &r100_pm_prepare, 348 .pm_finish = &r100_pm_finish, 349 .pm_init_profile = &r420_pm_init_profile, 350 .pm_get_dynpm_state = &r100_pm_get_dynpm_state, 351}; 352 353static struct radeon_asic rs400_asic = { 354 .init = &rs400_init, 355 .fini = &rs400_fini, 356 .suspend = &rs400_suspend, 357 .resume = &rs400_resume, 358 .vga_set_state = &r100_vga_set_state, 359 .gpu_is_lockup = &r300_gpu_is_lockup, 360 .asic_reset = &r300_asic_reset, 361 .gart_tlb_flush = &rs400_gart_tlb_flush, 362 .gart_set_page = &rs400_gart_set_page, 363 .cp_commit = &r100_cp_commit, 364 .ring_start = &r300_ring_start, 365 .ring_test = &r100_ring_test, 366 .ring_ib_execute = &r100_ring_ib_execute, 367 .irq_set = &r100_irq_set, 368 .irq_process = &r100_irq_process, 369 .get_vblank_counter = &r100_get_vblank_counter, 370 .fence_ring_emit = &r300_fence_ring_emit, 371 .cs_parse = &r300_cs_parse, 372 .copy_blit = &r100_copy_blit, 373 .copy_dma = &r200_copy_dma, 374 .copy = &r100_copy_blit, 375 .get_engine_clock = &radeon_legacy_get_engine_clock, 376 .set_engine_clock = &radeon_legacy_set_engine_clock, 377 .get_memory_clock = &radeon_legacy_get_memory_clock, 378 .set_memory_clock = NULL, 379 .get_pcie_lanes = NULL, 380 .set_pcie_lanes = NULL, 381 .set_clock_gating = &radeon_legacy_set_clock_gating, 382 .set_surface_reg = r100_set_surface_reg, 383 .clear_surface_reg = r100_clear_surface_reg, 384 .bandwidth_update = &r100_bandwidth_update, 385 .hpd_init = &r100_hpd_init, 386 .hpd_fini = &r100_hpd_fini, 387 .hpd_sense = &r100_hpd_sense, 388 .hpd_set_polarity = &r100_hpd_set_polarity, 389 .ioctl_wait_idle = NULL, 390 .gui_idle = &r100_gui_idle, 391 .pm_misc = &r100_pm_misc, 392 .pm_prepare = &r100_pm_prepare, 393 .pm_finish = &r100_pm_finish, 394 .pm_init_profile = &r100_pm_init_profile, 395 .pm_get_dynpm_state = &r100_pm_get_dynpm_state, 396}; 397 398static struct radeon_asic rs600_asic = { 399 .init = &rs600_init, 400 .fini = &rs600_fini, 401 .suspend = &rs600_suspend, 402 .resume = &rs600_resume, 403 .vga_set_state = &r100_vga_set_state, 404 .gpu_is_lockup = &r300_gpu_is_lockup, 405 .asic_reset = &rs600_asic_reset, 406 .gart_tlb_flush = &rs600_gart_tlb_flush, 407 .gart_set_page = &rs600_gart_set_page, 408 .cp_commit = &r100_cp_commit, 409 .ring_start = &r300_ring_start, 410 .ring_test = &r100_ring_test, 411 .ring_ib_execute = &r100_ring_ib_execute, 412 .irq_set = &rs600_irq_set, 413 .irq_process = &rs600_irq_process, 414 .get_vblank_counter = &rs600_get_vblank_counter, 415 .fence_ring_emit = &r300_fence_ring_emit, 416 .cs_parse = &r300_cs_parse, 417 .copy_blit = &r100_copy_blit, 418 .copy_dma = &r200_copy_dma, 419 .copy = &r100_copy_blit, 420 .get_engine_clock = &radeon_atom_get_engine_clock, 421 .set_engine_clock = &radeon_atom_set_engine_clock, 422 .get_memory_clock = &radeon_atom_get_memory_clock, 423 .set_memory_clock = &radeon_atom_set_memory_clock, 424 .get_pcie_lanes = NULL, 425 .set_pcie_lanes = NULL, 426 .set_clock_gating = &radeon_atom_set_clock_gating, 427 .set_surface_reg = r100_set_surface_reg, 428 .clear_surface_reg = r100_clear_surface_reg, 429 .bandwidth_update = &rs600_bandwidth_update, 430 .hpd_init = &rs600_hpd_init, 431 .hpd_fini = &rs600_hpd_fini, 432 .hpd_sense = &rs600_hpd_sense, 433 .hpd_set_polarity = &rs600_hpd_set_polarity, 434 .ioctl_wait_idle = NULL, 435 .gui_idle = &r100_gui_idle, 436 .pm_misc = &rs600_pm_misc, 437 .pm_prepare = &rs600_pm_prepare, 438 .pm_finish = &rs600_pm_finish, 439 .pm_init_profile = &r420_pm_init_profile, 440 .pm_get_dynpm_state = &r100_pm_get_dynpm_state, 441}; 442 443static struct radeon_asic rs690_asic = { 444 .init = &rs690_init, 445 .fini = &rs690_fini, 446 .suspend = &rs690_suspend, 447 .resume = &rs690_resume, 448 .vga_set_state = &r100_vga_set_state, 449 .gpu_is_lockup = &r300_gpu_is_lockup, 450 .asic_reset = &rs600_asic_reset, 451 .gart_tlb_flush = &rs400_gart_tlb_flush, 452 .gart_set_page = &rs400_gart_set_page, 453 .cp_commit = &r100_cp_commit, 454 .ring_start = &r300_ring_start, 455 .ring_test = &r100_ring_test, 456 .ring_ib_execute = &r100_ring_ib_execute, 457 .irq_set = &rs600_irq_set, 458 .irq_process = &rs600_irq_process, 459 .get_vblank_counter = &rs600_get_vblank_counter, 460 .fence_ring_emit = &r300_fence_ring_emit, 461 .cs_parse = &r300_cs_parse, 462 .copy_blit = &r100_copy_blit, 463 .copy_dma = &r200_copy_dma, 464 .copy = &r200_copy_dma, 465 .get_engine_clock = &radeon_atom_get_engine_clock, 466 .set_engine_clock = &radeon_atom_set_engine_clock, 467 .get_memory_clock = &radeon_atom_get_memory_clock, 468 .set_memory_clock = &radeon_atom_set_memory_clock, 469 .get_pcie_lanes = NULL, 470 .set_pcie_lanes = NULL, 471 .set_clock_gating = &radeon_atom_set_clock_gating, 472 .set_surface_reg = r100_set_surface_reg, 473 .clear_surface_reg = r100_clear_surface_reg, 474 .bandwidth_update = &rs690_bandwidth_update, 475 .hpd_init = &rs600_hpd_init, 476 .hpd_fini = &rs600_hpd_fini, 477 .hpd_sense = &rs600_hpd_sense, 478 .hpd_set_polarity = &rs600_hpd_set_polarity, 479 .ioctl_wait_idle = NULL, 480 .gui_idle = &r100_gui_idle, 481 .pm_misc = &rs600_pm_misc, 482 .pm_prepare = &rs600_pm_prepare, 483 .pm_finish = &rs600_pm_finish, 484 .pm_init_profile = &r420_pm_init_profile, 485 .pm_get_dynpm_state = &r100_pm_get_dynpm_state, 486}; 487 488static struct radeon_asic rv515_asic = { 489 .init = &rv515_init, 490 .fini = &rv515_fini, 491 .suspend = &rv515_suspend, 492 .resume = &rv515_resume, 493 .vga_set_state = &r100_vga_set_state, 494 .gpu_is_lockup = &r300_gpu_is_lockup, 495 .asic_reset = &rs600_asic_reset, 496 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, 497 .gart_set_page = &rv370_pcie_gart_set_page, 498 .cp_commit = &r100_cp_commit, 499 .ring_start = &rv515_ring_start, 500 .ring_test = &r100_ring_test, 501 .ring_ib_execute = &r100_ring_ib_execute, 502 .irq_set = &rs600_irq_set, 503 .irq_process = &rs600_irq_process, 504 .get_vblank_counter = &rs600_get_vblank_counter, 505 .fence_ring_emit = &r300_fence_ring_emit, 506 .cs_parse = &r300_cs_parse, 507 .copy_blit = &r100_copy_blit, 508 .copy_dma = &r200_copy_dma, 509 .copy = &r100_copy_blit, 510 .get_engine_clock = &radeon_atom_get_engine_clock, 511 .set_engine_clock = &radeon_atom_set_engine_clock, 512 .get_memory_clock = &radeon_atom_get_memory_clock, 513 .set_memory_clock = &radeon_atom_set_memory_clock, 514 .get_pcie_lanes = &rv370_get_pcie_lanes, 515 .set_pcie_lanes = &rv370_set_pcie_lanes, 516 .set_clock_gating = &radeon_atom_set_clock_gating, 517 .set_surface_reg = r100_set_surface_reg, 518 .clear_surface_reg = r100_clear_surface_reg, 519 .bandwidth_update = &rv515_bandwidth_update, 520 .hpd_init = &rs600_hpd_init, 521 .hpd_fini = &rs600_hpd_fini, 522 .hpd_sense = &rs600_hpd_sense, 523 .hpd_set_polarity = &rs600_hpd_set_polarity, 524 .ioctl_wait_idle = NULL, 525 .gui_idle = &r100_gui_idle, 526 .pm_misc = &rs600_pm_misc, 527 .pm_prepare = &rs600_pm_prepare, 528 .pm_finish = &rs600_pm_finish, 529 .pm_init_profile = &r420_pm_init_profile, 530 .pm_get_dynpm_state = &r100_pm_get_dynpm_state, 531}; 532 533static struct radeon_asic r520_asic = { 534 .init = &r520_init, 535 .fini = &rv515_fini, 536 .suspend = &rv515_suspend, 537 .resume = &r520_resume, 538 .vga_set_state = &r100_vga_set_state, 539 .gpu_is_lockup = &r300_gpu_is_lockup, 540 .asic_reset = &rs600_asic_reset, 541 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, 542 .gart_set_page = &rv370_pcie_gart_set_page, 543 .cp_commit = &r100_cp_commit, 544 .ring_start = &rv515_ring_start, 545 .ring_test = &r100_ring_test, 546 .ring_ib_execute = &r100_ring_ib_execute, 547 .irq_set = &rs600_irq_set, 548 .irq_process = &rs600_irq_process, 549 .get_vblank_counter = &rs600_get_vblank_counter, 550 .fence_ring_emit = &r300_fence_ring_emit, 551 .cs_parse = &r300_cs_parse, 552 .copy_blit = &r100_copy_blit, 553 .copy_dma = &r200_copy_dma, 554 .copy = &r100_copy_blit, 555 .get_engine_clock = &radeon_atom_get_engine_clock, 556 .set_engine_clock = &radeon_atom_set_engine_clock, 557 .get_memory_clock = &radeon_atom_get_memory_clock, 558 .set_memory_clock = &radeon_atom_set_memory_clock, 559 .get_pcie_lanes = &rv370_get_pcie_lanes, 560 .set_pcie_lanes = &rv370_set_pcie_lanes, 561 .set_clock_gating = &radeon_atom_set_clock_gating, 562 .set_surface_reg = r100_set_surface_reg, 563 .clear_surface_reg = r100_clear_surface_reg, 564 .bandwidth_update = &rv515_bandwidth_update, 565 .hpd_init = &rs600_hpd_init, 566 .hpd_fini = &rs600_hpd_fini, 567 .hpd_sense = &rs600_hpd_sense, 568 .hpd_set_polarity = &rs600_hpd_set_polarity, 569 .ioctl_wait_idle = NULL, 570 .gui_idle = &r100_gui_idle, 571 .pm_misc = &rs600_pm_misc, 572 .pm_prepare = &rs600_pm_prepare, 573 .pm_finish = &rs600_pm_finish, 574 .pm_init_profile = &r420_pm_init_profile, 575 .pm_get_dynpm_state = &r100_pm_get_dynpm_state, 576}; 577 578static struct radeon_asic r600_asic = { 579 .init = &r600_init, 580 .fini = &r600_fini, 581 .suspend = &r600_suspend, 582 .resume = &r600_resume, 583 .cp_commit = &r600_cp_commit, 584 .vga_set_state = &r600_vga_set_state, 585 .gpu_is_lockup = &r600_gpu_is_lockup, 586 .asic_reset = &r600_asic_reset, 587 .gart_tlb_flush = &r600_pcie_gart_tlb_flush, 588 .gart_set_page = &rs600_gart_set_page, 589 .ring_test = &r600_ring_test, 590 .ring_ib_execute = &r600_ring_ib_execute, 591 .irq_set = &r600_irq_set, 592 .irq_process = &r600_irq_process, 593 .get_vblank_counter = &rs600_get_vblank_counter, 594 .fence_ring_emit = &r600_fence_ring_emit, 595 .cs_parse = &r600_cs_parse, 596 .copy_blit = &r600_copy_blit, 597 .copy_dma = &r600_copy_blit, 598 .copy = &r600_copy_blit, 599 .get_engine_clock = &radeon_atom_get_engine_clock, 600 .set_engine_clock = &radeon_atom_set_engine_clock, 601 .get_memory_clock = &radeon_atom_get_memory_clock, 602 .set_memory_clock = &radeon_atom_set_memory_clock, 603 .get_pcie_lanes = &rv370_get_pcie_lanes, 604 .set_pcie_lanes = NULL, 605 .set_clock_gating = NULL, 606 .set_surface_reg = r600_set_surface_reg, 607 .clear_surface_reg = r600_clear_surface_reg, 608 .bandwidth_update = &rv515_bandwidth_update, 609 .hpd_init = &r600_hpd_init, 610 .hpd_fini = &r600_hpd_fini, 611 .hpd_sense = &r600_hpd_sense, 612 .hpd_set_polarity = &r600_hpd_set_polarity, 613 .ioctl_wait_idle = r600_ioctl_wait_idle, 614 .gui_idle = &r600_gui_idle, 615 .pm_misc = &r600_pm_misc, 616 .pm_prepare = &rs600_pm_prepare, 617 .pm_finish = &rs600_pm_finish, 618 .pm_init_profile = &r600_pm_init_profile, 619 .pm_get_dynpm_state = &r600_pm_get_dynpm_state, 620}; 621 622static struct radeon_asic rs780_asic = { 623 .init = &r600_init, 624 .fini = &r600_fini, 625 .suspend = &r600_suspend, 626 .resume = &r600_resume, 627 .cp_commit = &r600_cp_commit, 628 .gpu_is_lockup = &r600_gpu_is_lockup, 629 .vga_set_state = &r600_vga_set_state, 630 .asic_reset = &r600_asic_reset, 631 .gart_tlb_flush = &r600_pcie_gart_tlb_flush, 632 .gart_set_page = &rs600_gart_set_page, 633 .ring_test = &r600_ring_test, 634 .ring_ib_execute = &r600_ring_ib_execute, 635 .irq_set = &r600_irq_set, 636 .irq_process = &r600_irq_process, 637 .get_vblank_counter = &rs600_get_vblank_counter, 638 .fence_ring_emit = &r600_fence_ring_emit, 639 .cs_parse = &r600_cs_parse, 640 .copy_blit = &r600_copy_blit, 641 .copy_dma = &r600_copy_blit, 642 .copy = &r600_copy_blit, 643 .get_engine_clock = &radeon_atom_get_engine_clock, 644 .set_engine_clock = &radeon_atom_set_engine_clock, 645 .get_memory_clock = NULL, 646 .set_memory_clock = NULL, 647 .get_pcie_lanes = NULL, 648 .set_pcie_lanes = NULL, 649 .set_clock_gating = NULL, 650 .set_surface_reg = r600_set_surface_reg, 651 .clear_surface_reg = r600_clear_surface_reg, 652 .bandwidth_update = &rs690_bandwidth_update, 653 .hpd_init = &r600_hpd_init, 654 .hpd_fini = &r600_hpd_fini, 655 .hpd_sense = &r600_hpd_sense, 656 .hpd_set_polarity = &r600_hpd_set_polarity, 657 .ioctl_wait_idle = r600_ioctl_wait_idle, 658 .gui_idle = &r600_gui_idle, 659 .pm_misc = &r600_pm_misc, 660 .pm_prepare = &rs600_pm_prepare, 661 .pm_finish = &rs600_pm_finish, 662 .pm_init_profile = &rs780_pm_init_profile, 663 .pm_get_dynpm_state = &r600_pm_get_dynpm_state, 664}; 665 666static struct radeon_asic rv770_asic = { 667 .init = &rv770_init, 668 .fini = &rv770_fini, 669 .suspend = &rv770_suspend, 670 .resume = &rv770_resume, 671 .cp_commit = &r600_cp_commit, 672 .asic_reset = &r600_asic_reset, 673 .gpu_is_lockup = &r600_gpu_is_lockup, 674 .vga_set_state = &r600_vga_set_state, 675 .gart_tlb_flush = &r600_pcie_gart_tlb_flush, 676 .gart_set_page = &rs600_gart_set_page, 677 .ring_test = &r600_ring_test, 678 .ring_ib_execute = &r600_ring_ib_execute, 679 .irq_set = &r600_irq_set, 680 .irq_process = &r600_irq_process, 681 .get_vblank_counter = &rs600_get_vblank_counter, 682 .fence_ring_emit = &r600_fence_ring_emit, 683 .cs_parse = &r600_cs_parse, 684 .copy_blit = &r600_copy_blit, 685 .copy_dma = &r600_copy_blit, 686 .copy = &r600_copy_blit, 687 .get_engine_clock = &radeon_atom_get_engine_clock, 688 .set_engine_clock = &radeon_atom_set_engine_clock, 689 .get_memory_clock = &radeon_atom_get_memory_clock, 690 .set_memory_clock = &radeon_atom_set_memory_clock, 691 .get_pcie_lanes = &rv370_get_pcie_lanes, 692 .set_pcie_lanes = NULL, 693 .set_clock_gating = &radeon_atom_set_clock_gating, 694 .set_surface_reg = r600_set_surface_reg, 695 .clear_surface_reg = r600_clear_surface_reg, 696 .bandwidth_update = &rv515_bandwidth_update, 697 .hpd_init = &r600_hpd_init, 698 .hpd_fini = &r600_hpd_fini, 699 .hpd_sense = &r600_hpd_sense, 700 .hpd_set_polarity = &r600_hpd_set_polarity, 701 .ioctl_wait_idle = r600_ioctl_wait_idle, 702 .gui_idle = &r600_gui_idle, 703 .pm_misc = &rv770_pm_misc, 704 .pm_prepare = &rs600_pm_prepare, 705 .pm_finish = &rs600_pm_finish, 706 .pm_init_profile = &r600_pm_init_profile, 707 .pm_get_dynpm_state = &r600_pm_get_dynpm_state, 708}; 709 710static struct radeon_asic evergreen_asic = { 711 .init = &evergreen_init, 712 .fini = &evergreen_fini, 713 .suspend = &evergreen_suspend, 714 .resume = &evergreen_resume, 715 .cp_commit = &r600_cp_commit, 716 .gpu_is_lockup = &evergreen_gpu_is_lockup, 717 .asic_reset = &evergreen_asic_reset, 718 .vga_set_state = &r600_vga_set_state, 719 .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, 720 .gart_set_page = &rs600_gart_set_page, 721 .ring_test = &r600_ring_test, 722 .ring_ib_execute = &r600_ring_ib_execute, 723 .irq_set = &evergreen_irq_set, 724 .irq_process = &evergreen_irq_process, 725 .get_vblank_counter = &evergreen_get_vblank_counter, 726 .fence_ring_emit = &r600_fence_ring_emit, 727 .cs_parse = &evergreen_cs_parse, 728 .copy_blit = NULL, 729 .copy_dma = NULL, 730 .copy = NULL, 731 .get_engine_clock = &radeon_atom_get_engine_clock, 732 .set_engine_clock = &radeon_atom_set_engine_clock, 733 .get_memory_clock = &radeon_atom_get_memory_clock, 734 .set_memory_clock = &radeon_atom_set_memory_clock, 735 .get_pcie_lanes = NULL, 736 .set_pcie_lanes = NULL, 737 .set_clock_gating = NULL, 738 .set_surface_reg = r600_set_surface_reg, 739 .clear_surface_reg = r600_clear_surface_reg, 740 .bandwidth_update = &evergreen_bandwidth_update, 741 .hpd_init = &evergreen_hpd_init, 742 .hpd_fini = &evergreen_hpd_fini, 743 .hpd_sense = &evergreen_hpd_sense, 744 .hpd_set_polarity = &evergreen_hpd_set_polarity, 745 .gui_idle = &r600_gui_idle, 746 .pm_misc = &evergreen_pm_misc, 747 .pm_prepare = &evergreen_pm_prepare, 748 .pm_finish = &evergreen_pm_finish, 749 .pm_init_profile = &r600_pm_init_profile, 750 .pm_get_dynpm_state = &r600_pm_get_dynpm_state, 751}; 752 753int radeon_asic_init(struct radeon_device *rdev) 754{ 755 radeon_register_accessor_init(rdev); 756 switch (rdev->family) { 757 case CHIP_R100: 758 case CHIP_RV100: 759 case CHIP_RS100: 760 case CHIP_RV200: 761 case CHIP_RS200: 762 rdev->asic = &r100_asic; 763 break; 764 case CHIP_R200: 765 case CHIP_RV250: 766 case CHIP_RS300: 767 case CHIP_RV280: 768 rdev->asic = &r200_asic; 769 break; 770 case CHIP_R300: 771 case CHIP_R350: 772 case CHIP_RV350: 773 case CHIP_RV380: 774 if (rdev->flags & RADEON_IS_PCIE) 775 rdev->asic = &r300_asic_pcie; 776 else 777 rdev->asic = &r300_asic; 778 break; 779 case CHIP_R420: 780 case CHIP_R423: 781 case CHIP_RV410: 782 rdev->asic = &r420_asic; 783 /* handle macs */ 784 if (rdev->bios == NULL) { 785 rdev->asic->get_engine_clock = &radeon_legacy_get_engine_clock; 786 rdev->asic->set_engine_clock = &radeon_legacy_set_engine_clock; 787 rdev->asic->get_memory_clock = &radeon_legacy_get_memory_clock; 788 rdev->asic->set_memory_clock = NULL; 789 } 790 break; 791 case CHIP_RS400: 792 case CHIP_RS480: 793 rdev->asic = &rs400_asic; 794 break; 795 case CHIP_RS600: 796 rdev->asic = &rs600_asic; 797 break; 798 case CHIP_RS690: 799 case CHIP_RS740: 800 rdev->asic = &rs690_asic; 801 break; 802 case CHIP_RV515: 803 rdev->asic = &rv515_asic; 804 break; 805 case CHIP_R520: 806 case CHIP_RV530: 807 case CHIP_RV560: 808 case CHIP_RV570: 809 case CHIP_R580: 810 rdev->asic = &r520_asic; 811 break; 812 case CHIP_R600: 813 case CHIP_RV610: 814 case CHIP_RV630: 815 case CHIP_RV620: 816 case CHIP_RV635: 817 case CHIP_RV670: 818 rdev->asic = &r600_asic; 819 break; 820 case CHIP_RS780: 821 case CHIP_RS880: 822 rdev->asic = &rs780_asic; 823 break; 824 case CHIP_RV770: 825 case CHIP_RV730: 826 case CHIP_RV710: 827 case CHIP_RV740: 828 rdev->asic = &rv770_asic; 829 break; 830 case CHIP_CEDAR: 831 case CHIP_REDWOOD: 832 case CHIP_JUNIPER: 833 case CHIP_CYPRESS: 834 case CHIP_HEMLOCK: 835 rdev->asic = &evergreen_asic; 836 break; 837 default: 838 return -EINVAL; 839 } 840 841 if (rdev->flags & RADEON_IS_IGP) { 842 rdev->asic->get_memory_clock = NULL; 843 rdev->asic->set_memory_clock = NULL; 844 } 845 846 /* set the number of crtcs */ 847 if (rdev->flags & RADEON_SINGLE_CRTC) 848 rdev->num_crtc = 1; 849 else { 850 if (ASIC_IS_DCE4(rdev)) 851 rdev->num_crtc = 6; 852 else 853 rdev->num_crtc = 2; 854 } 855 856 return 0; 857} 858