1/* 2 * Copyright 2009 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 25/* NVIDIA context programs handle a number of other conditions which are 26 * not implemented in our versions. It's not clear why NVIDIA context 27 * programs have this code, nor whether it's strictly necessary for 28 * correct operation. We'll implement additional handling if/when we 29 * discover it's necessary. 30 * 31 * - On context save, NVIDIA set 0x400314 bit 0 to 1 if the "3D state" 32 * flag is set, this gets saved into the context. 33 * - On context save, the context program for all cards load nsource 34 * into a flag register and check for ILLEGAL_MTHD. If it's set, 35 * opcode 0x60000d is called before resuming normal operation. 36 * - Some context programs check more conditions than the above. NV44 37 * checks: ((nsource & 0x0857) || (0x400718 & 0x0100) || (intr & 0x0001)) 38 * and calls 0x60000d before resuming normal operation. 39 * - At the very beginning of NVIDIA's context programs, flag 9 is checked 40 * and if true 0x800001 is called with count=0, pos=0, the flag is cleared 41 * and then the ctxprog is aborted. It looks like a complicated NOP, 42 * its purpose is unknown. 43 * - In the section of code that loads the per-vs state, NVIDIA check 44 * flag 10. If it's set, they only transfer the small 0x300 byte block 45 * of state + the state for a single vs as opposed to the state for 46 * all vs units. It doesn't seem likely that it'll occur in normal 47 * operation, especially seeing as it appears NVIDIA may have screwed 48 * up the ctxprogs for some cards and have an invalid instruction 49 * rather than a cp_lsr(ctx, dwords_for_1_vs_unit) instruction. 50 * - There's a number of places where context offset 0 (where we place 51 * the PRAMIN offset of the context) is loaded into either 0x408000, 52 * 0x408004 or 0x408008. Not sure what's up there either. 53 * - The ctxprogs for some cards save 0x400a00 again during the cleanup 54 * path for auto-loadctx. 55 */ 56 57#define CP_FLAG_CLEAR 0 58#define CP_FLAG_SET 1 59#define CP_FLAG_SWAP_DIRECTION ((0 * 32) + 0) 60#define CP_FLAG_SWAP_DIRECTION_LOAD 0 61#define CP_FLAG_SWAP_DIRECTION_SAVE 1 62#define CP_FLAG_USER_SAVE ((0 * 32) + 5) 63#define CP_FLAG_USER_SAVE_NOT_PENDING 0 64#define CP_FLAG_USER_SAVE_PENDING 1 65#define CP_FLAG_USER_LOAD ((0 * 32) + 6) 66#define CP_FLAG_USER_LOAD_NOT_PENDING 0 67#define CP_FLAG_USER_LOAD_PENDING 1 68#define CP_FLAG_STATUS ((3 * 32) + 0) 69#define CP_FLAG_STATUS_IDLE 0 70#define CP_FLAG_STATUS_BUSY 1 71#define CP_FLAG_AUTO_SAVE ((3 * 32) + 4) 72#define CP_FLAG_AUTO_SAVE_NOT_PENDING 0 73#define CP_FLAG_AUTO_SAVE_PENDING 1 74#define CP_FLAG_AUTO_LOAD ((3 * 32) + 5) 75#define CP_FLAG_AUTO_LOAD_NOT_PENDING 0 76#define CP_FLAG_AUTO_LOAD_PENDING 1 77#define CP_FLAG_UNK54 ((3 * 32) + 6) 78#define CP_FLAG_UNK54_CLEAR 0 79#define CP_FLAG_UNK54_SET 1 80#define CP_FLAG_ALWAYS ((3 * 32) + 8) 81#define CP_FLAG_ALWAYS_FALSE 0 82#define CP_FLAG_ALWAYS_TRUE 1 83#define CP_FLAG_UNK57 ((3 * 32) + 9) 84#define CP_FLAG_UNK57_CLEAR 0 85#define CP_FLAG_UNK57_SET 1 86 87#define CP_CTX 0x00100000 88#define CP_CTX_COUNT 0x000fc000 89#define CP_CTX_COUNT_SHIFT 14 90#define CP_CTX_REG 0x00003fff 91#define CP_LOAD_SR 0x00200000 92#define CP_LOAD_SR_VALUE 0x000fffff 93#define CP_BRA 0x00400000 94#define CP_BRA_IP 0x0000ff00 95#define CP_BRA_IP_SHIFT 8 96#define CP_BRA_IF_CLEAR 0x00000080 97#define CP_BRA_FLAG 0x0000007f 98#define CP_WAIT 0x00500000 99#define CP_WAIT_SET 0x00000080 100#define CP_WAIT_FLAG 0x0000007f 101#define CP_SET 0x00700000 102#define CP_SET_1 0x00000080 103#define CP_SET_FLAG 0x0000007f 104#define CP_NEXT_TO_SWAP 0x00600007 105#define CP_NEXT_TO_CURRENT 0x00600009 106#define CP_SET_CONTEXT_POINTER 0x0060000a 107#define CP_END 0x0060000e 108#define CP_LOAD_MAGIC_UNK01 0x00800001 /* unknown */ 109#define CP_LOAD_MAGIC_NV44TCL 0x00800029 /* per-vs state (0x4497) */ 110#define CP_LOAD_MAGIC_NV40TCL 0x00800041 /* per-vs state (0x4097) */ 111 112#include "drmP.h" 113#include "nouveau_drv.h" 114#include "nouveau_grctx.h" 115 116/* TODO: 117 * - get vs count from 0x1540 118 */ 119 120static int 121nv40_graph_4097(struct drm_device *dev) 122{ 123 struct drm_nouveau_private *dev_priv = dev->dev_private; 124 125 if ((dev_priv->chipset & 0xf0) == 0x60) 126 return 0; 127 128 return !!(0x0baf & (1 << dev_priv->chipset)); 129} 130 131static int 132nv40_graph_vs_count(struct drm_device *dev) 133{ 134 struct drm_nouveau_private *dev_priv = dev->dev_private; 135 136 switch (dev_priv->chipset) { 137 case 0x47: 138 case 0x49: 139 case 0x4b: 140 return 8; 141 case 0x40: 142 return 6; 143 case 0x41: 144 case 0x42: 145 return 5; 146 case 0x43: 147 case 0x44: 148 case 0x46: 149 case 0x4a: 150 return 3; 151 case 0x4c: 152 case 0x4e: 153 case 0x67: 154 default: 155 return 1; 156 } 157} 158 159 160enum cp_label { 161 cp_check_load = 1, 162 cp_setup_auto_load, 163 cp_setup_load, 164 cp_setup_save, 165 cp_swap_state, 166 cp_swap_state3d_3_is_save, 167 cp_prepare_exit, 168 cp_exit, 169}; 170 171static void 172nv40_graph_construct_general(struct nouveau_grctx *ctx) 173{ 174 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private; 175 int i; 176 177 cp_ctx(ctx, 0x4000a4, 1); 178 gr_def(ctx, 0x4000a4, 0x00000008); 179 cp_ctx(ctx, 0x400144, 58); 180 gr_def(ctx, 0x400144, 0x00000001); 181 cp_ctx(ctx, 0x400314, 1); 182 gr_def(ctx, 0x400314, 0x00000000); 183 cp_ctx(ctx, 0x400400, 10); 184 cp_ctx(ctx, 0x400480, 10); 185 cp_ctx(ctx, 0x400500, 19); 186 gr_def(ctx, 0x400514, 0x00040000); 187 gr_def(ctx, 0x400524, 0x55555555); 188 gr_def(ctx, 0x400528, 0x55555555); 189 gr_def(ctx, 0x40052c, 0x55555555); 190 gr_def(ctx, 0x400530, 0x55555555); 191 cp_ctx(ctx, 0x400560, 6); 192 gr_def(ctx, 0x400568, 0x0000ffff); 193 gr_def(ctx, 0x40056c, 0x0000ffff); 194 cp_ctx(ctx, 0x40057c, 5); 195 cp_ctx(ctx, 0x400710, 3); 196 gr_def(ctx, 0x400710, 0x20010001); 197 gr_def(ctx, 0x400714, 0x0f73ef00); 198 cp_ctx(ctx, 0x400724, 1); 199 gr_def(ctx, 0x400724, 0x02008821); 200 cp_ctx(ctx, 0x400770, 3); 201 if (dev_priv->chipset == 0x40) { 202 cp_ctx(ctx, 0x400814, 4); 203 cp_ctx(ctx, 0x400828, 5); 204 cp_ctx(ctx, 0x400840, 5); 205 gr_def(ctx, 0x400850, 0x00000040); 206 cp_ctx(ctx, 0x400858, 4); 207 gr_def(ctx, 0x400858, 0x00000040); 208 gr_def(ctx, 0x40085c, 0x00000040); 209 gr_def(ctx, 0x400864, 0x80000000); 210 cp_ctx(ctx, 0x40086c, 9); 211 gr_def(ctx, 0x40086c, 0x80000000); 212 gr_def(ctx, 0x400870, 0x80000000); 213 gr_def(ctx, 0x400874, 0x80000000); 214 gr_def(ctx, 0x400878, 0x80000000); 215 gr_def(ctx, 0x400888, 0x00000040); 216 gr_def(ctx, 0x40088c, 0x80000000); 217 cp_ctx(ctx, 0x4009c0, 8); 218 gr_def(ctx, 0x4009cc, 0x80000000); 219 gr_def(ctx, 0x4009dc, 0x80000000); 220 } else { 221 cp_ctx(ctx, 0x400840, 20); 222 if (!nv40_graph_4097(ctx->dev)) { 223 for (i = 0; i < 8; i++) 224 gr_def(ctx, 0x400860 + (i * 4), 0x00000001); 225 } 226 gr_def(ctx, 0x400880, 0x00000040); 227 gr_def(ctx, 0x400884, 0x00000040); 228 gr_def(ctx, 0x400888, 0x00000040); 229 cp_ctx(ctx, 0x400894, 11); 230 gr_def(ctx, 0x400894, 0x00000040); 231 if (nv40_graph_4097(ctx->dev)) { 232 for (i = 0; i < 8; i++) 233 gr_def(ctx, 0x4008a0 + (i * 4), 0x80000000); 234 } 235 cp_ctx(ctx, 0x4008e0, 2); 236 cp_ctx(ctx, 0x4008f8, 2); 237 if (dev_priv->chipset == 0x4c || 238 (dev_priv->chipset & 0xf0) == 0x60) 239 cp_ctx(ctx, 0x4009f8, 1); 240 } 241 cp_ctx(ctx, 0x400a00, 73); 242 gr_def(ctx, 0x400b0c, 0x0b0b0b0c); 243 cp_ctx(ctx, 0x401000, 4); 244 cp_ctx(ctx, 0x405004, 1); 245 switch (dev_priv->chipset) { 246 case 0x47: 247 case 0x49: 248 case 0x4b: 249 cp_ctx(ctx, 0x403448, 1); 250 gr_def(ctx, 0x403448, 0x00001010); 251 break; 252 default: 253 cp_ctx(ctx, 0x403440, 1); 254 switch (dev_priv->chipset) { 255 case 0x40: 256 gr_def(ctx, 0x403440, 0x00000010); 257 break; 258 case 0x44: 259 case 0x46: 260 case 0x4a: 261 gr_def(ctx, 0x403440, 0x00003010); 262 break; 263 case 0x41: 264 case 0x42: 265 case 0x43: 266 case 0x4c: 267 case 0x4e: 268 case 0x67: 269 default: 270 gr_def(ctx, 0x403440, 0x00001010); 271 break; 272 } 273 break; 274 } 275} 276 277static void 278nv40_graph_construct_state3d(struct nouveau_grctx *ctx) 279{ 280 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private; 281 int i; 282 283 if (dev_priv->chipset == 0x40) { 284 cp_ctx(ctx, 0x401880, 51); 285 gr_def(ctx, 0x401940, 0x00000100); 286 } else 287 if (dev_priv->chipset == 0x46 || dev_priv->chipset == 0x47 || 288 dev_priv->chipset == 0x49 || dev_priv->chipset == 0x4b) { 289 cp_ctx(ctx, 0x401880, 32); 290 for (i = 0; i < 16; i++) 291 gr_def(ctx, 0x401880 + (i * 4), 0x00000111); 292 if (dev_priv->chipset == 0x46) 293 cp_ctx(ctx, 0x401900, 16); 294 cp_ctx(ctx, 0x401940, 3); 295 } 296 cp_ctx(ctx, 0x40194c, 18); 297 gr_def(ctx, 0x401954, 0x00000111); 298 gr_def(ctx, 0x401958, 0x00080060); 299 gr_def(ctx, 0x401974, 0x00000080); 300 gr_def(ctx, 0x401978, 0xffff0000); 301 gr_def(ctx, 0x40197c, 0x00000001); 302 gr_def(ctx, 0x401990, 0x46400000); 303 if (dev_priv->chipset == 0x40) { 304 cp_ctx(ctx, 0x4019a0, 2); 305 cp_ctx(ctx, 0x4019ac, 5); 306 } else { 307 cp_ctx(ctx, 0x4019a0, 1); 308 cp_ctx(ctx, 0x4019b4, 3); 309 } 310 gr_def(ctx, 0x4019bc, 0xffff0000); 311 switch (dev_priv->chipset) { 312 case 0x46: 313 case 0x47: 314 case 0x49: 315 case 0x4b: 316 cp_ctx(ctx, 0x4019c0, 18); 317 for (i = 0; i < 16; i++) 318 gr_def(ctx, 0x4019c0 + (i * 4), 0x88888888); 319 break; 320 } 321 cp_ctx(ctx, 0x401a08, 8); 322 gr_def(ctx, 0x401a10, 0x0fff0000); 323 gr_def(ctx, 0x401a14, 0x0fff0000); 324 gr_def(ctx, 0x401a1c, 0x00011100); 325 cp_ctx(ctx, 0x401a2c, 4); 326 cp_ctx(ctx, 0x401a44, 26); 327 for (i = 0; i < 16; i++) 328 gr_def(ctx, 0x401a44 + (i * 4), 0x07ff0000); 329 gr_def(ctx, 0x401a8c, 0x4b7fffff); 330 if (dev_priv->chipset == 0x40) { 331 cp_ctx(ctx, 0x401ab8, 3); 332 } else { 333 cp_ctx(ctx, 0x401ab8, 1); 334 cp_ctx(ctx, 0x401ac0, 1); 335 } 336 cp_ctx(ctx, 0x401ad0, 8); 337 gr_def(ctx, 0x401ad0, 0x30201000); 338 gr_def(ctx, 0x401ad4, 0x70605040); 339 gr_def(ctx, 0x401ad8, 0xb8a89888); 340 gr_def(ctx, 0x401adc, 0xf8e8d8c8); 341 cp_ctx(ctx, 0x401b10, dev_priv->chipset == 0x40 ? 2 : 1); 342 gr_def(ctx, 0x401b10, 0x40100000); 343 cp_ctx(ctx, 0x401b18, dev_priv->chipset == 0x40 ? 6 : 5); 344 gr_def(ctx, 0x401b28, dev_priv->chipset == 0x40 ? 345 0x00000004 : 0x00000000); 346 cp_ctx(ctx, 0x401b30, 25); 347 gr_def(ctx, 0x401b34, 0x0000ffff); 348 gr_def(ctx, 0x401b68, 0x435185d6); 349 gr_def(ctx, 0x401b6c, 0x2155b699); 350 gr_def(ctx, 0x401b70, 0xfedcba98); 351 gr_def(ctx, 0x401b74, 0x00000098); 352 gr_def(ctx, 0x401b84, 0xffffffff); 353 gr_def(ctx, 0x401b88, 0x00ff7000); 354 gr_def(ctx, 0x401b8c, 0x0000ffff); 355 if (dev_priv->chipset != 0x44 && dev_priv->chipset != 0x4a && 356 dev_priv->chipset != 0x4e) 357 cp_ctx(ctx, 0x401b94, 1); 358 cp_ctx(ctx, 0x401b98, 8); 359 gr_def(ctx, 0x401b9c, 0x00ff0000); 360 cp_ctx(ctx, 0x401bc0, 9); 361 gr_def(ctx, 0x401be0, 0x00ffff00); 362 cp_ctx(ctx, 0x401c00, 192); 363 for (i = 0; i < 16; i++) { /* fragment texture units */ 364 gr_def(ctx, 0x401c40 + (i * 4), 0x00018488); 365 gr_def(ctx, 0x401c80 + (i * 4), 0x00028202); 366 gr_def(ctx, 0x401d00 + (i * 4), 0x0000aae4); 367 gr_def(ctx, 0x401d40 + (i * 4), 0x01012000); 368 gr_def(ctx, 0x401d80 + (i * 4), 0x00080008); 369 gr_def(ctx, 0x401e00 + (i * 4), 0x00100008); 370 } 371 for (i = 0; i < 4; i++) { /* vertex texture units */ 372 gr_def(ctx, 0x401e90 + (i * 4), 0x0001bc80); 373 gr_def(ctx, 0x401ea0 + (i * 4), 0x00000202); 374 gr_def(ctx, 0x401ec0 + (i * 4), 0x00000008); 375 gr_def(ctx, 0x401ee0 + (i * 4), 0x00080008); 376 } 377 cp_ctx(ctx, 0x400f5c, 3); 378 gr_def(ctx, 0x400f5c, 0x00000002); 379 cp_ctx(ctx, 0x400f84, 1); 380} 381 382static void 383nv40_graph_construct_state3d_2(struct nouveau_grctx *ctx) 384{ 385 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private; 386 int i; 387 388 cp_ctx(ctx, 0x402000, 1); 389 cp_ctx(ctx, 0x402404, dev_priv->chipset == 0x40 ? 1 : 2); 390 switch (dev_priv->chipset) { 391 case 0x40: 392 gr_def(ctx, 0x402404, 0x00000001); 393 break; 394 case 0x4c: 395 case 0x4e: 396 case 0x67: 397 gr_def(ctx, 0x402404, 0x00000020); 398 break; 399 case 0x46: 400 case 0x49: 401 case 0x4b: 402 gr_def(ctx, 0x402404, 0x00000421); 403 break; 404 default: 405 gr_def(ctx, 0x402404, 0x00000021); 406 } 407 if (dev_priv->chipset != 0x40) 408 gr_def(ctx, 0x402408, 0x030c30c3); 409 switch (dev_priv->chipset) { 410 case 0x44: 411 case 0x46: 412 case 0x4a: 413 case 0x4c: 414 case 0x4e: 415 case 0x67: 416 cp_ctx(ctx, 0x402440, 1); 417 gr_def(ctx, 0x402440, 0x00011001); 418 break; 419 default: 420 break; 421 } 422 cp_ctx(ctx, 0x402480, dev_priv->chipset == 0x40 ? 8 : 9); 423 gr_def(ctx, 0x402488, 0x3e020200); 424 gr_def(ctx, 0x40248c, 0x00ffffff); 425 switch (dev_priv->chipset) { 426 case 0x40: 427 gr_def(ctx, 0x402490, 0x60103f00); 428 break; 429 case 0x47: 430 gr_def(ctx, 0x402490, 0x40103f00); 431 break; 432 case 0x41: 433 case 0x42: 434 case 0x49: 435 case 0x4b: 436 gr_def(ctx, 0x402490, 0x20103f00); 437 break; 438 default: 439 gr_def(ctx, 0x402490, 0x0c103f00); 440 break; 441 } 442 gr_def(ctx, 0x40249c, dev_priv->chipset <= 0x43 ? 443 0x00020000 : 0x00040000); 444 cp_ctx(ctx, 0x402500, 31); 445 gr_def(ctx, 0x402530, 0x00008100); 446 if (dev_priv->chipset == 0x40) 447 cp_ctx(ctx, 0x40257c, 6); 448 cp_ctx(ctx, 0x402594, 16); 449 cp_ctx(ctx, 0x402800, 17); 450 gr_def(ctx, 0x402800, 0x00000001); 451 switch (dev_priv->chipset) { 452 case 0x47: 453 case 0x49: 454 case 0x4b: 455 cp_ctx(ctx, 0x402864, 1); 456 gr_def(ctx, 0x402864, 0x00001001); 457 cp_ctx(ctx, 0x402870, 3); 458 gr_def(ctx, 0x402878, 0x00000003); 459 if (dev_priv->chipset != 0x47) { /* belong at end!! */ 460 cp_ctx(ctx, 0x402900, 1); 461 cp_ctx(ctx, 0x402940, 1); 462 cp_ctx(ctx, 0x402980, 1); 463 cp_ctx(ctx, 0x4029c0, 1); 464 cp_ctx(ctx, 0x402a00, 1); 465 cp_ctx(ctx, 0x402a40, 1); 466 cp_ctx(ctx, 0x402a80, 1); 467 cp_ctx(ctx, 0x402ac0, 1); 468 } 469 break; 470 case 0x40: 471 cp_ctx(ctx, 0x402844, 1); 472 gr_def(ctx, 0x402844, 0x00000001); 473 cp_ctx(ctx, 0x402850, 1); 474 break; 475 default: 476 cp_ctx(ctx, 0x402844, 1); 477 gr_def(ctx, 0x402844, 0x00001001); 478 cp_ctx(ctx, 0x402850, 2); 479 gr_def(ctx, 0x402854, 0x00000003); 480 break; 481 } 482 483 cp_ctx(ctx, 0x402c00, 4); 484 gr_def(ctx, 0x402c00, dev_priv->chipset == 0x40 ? 485 0x80800001 : 0x00888001); 486 switch (dev_priv->chipset) { 487 case 0x47: 488 case 0x49: 489 case 0x4b: 490 cp_ctx(ctx, 0x402c20, 40); 491 for (i = 0; i < 32; i++) 492 gr_def(ctx, 0x402c40 + (i * 4), 0xffffffff); 493 cp_ctx(ctx, 0x4030b8, 13); 494 gr_def(ctx, 0x4030dc, 0x00000005); 495 gr_def(ctx, 0x4030e8, 0x0000ffff); 496 break; 497 default: 498 cp_ctx(ctx, 0x402c10, 4); 499 if (dev_priv->chipset == 0x40) 500 cp_ctx(ctx, 0x402c20, 36); 501 else 502 if (dev_priv->chipset <= 0x42) 503 cp_ctx(ctx, 0x402c20, 24); 504 else 505 if (dev_priv->chipset <= 0x4a) 506 cp_ctx(ctx, 0x402c20, 16); 507 else 508 cp_ctx(ctx, 0x402c20, 8); 509 cp_ctx(ctx, 0x402cb0, dev_priv->chipset == 0x40 ? 12 : 13); 510 gr_def(ctx, 0x402cd4, 0x00000005); 511 if (dev_priv->chipset != 0x40) 512 gr_def(ctx, 0x402ce0, 0x0000ffff); 513 break; 514 } 515 516 cp_ctx(ctx, 0x403400, dev_priv->chipset == 0x40 ? 4 : 3); 517 cp_ctx(ctx, 0x403410, dev_priv->chipset == 0x40 ? 4 : 3); 518 cp_ctx(ctx, 0x403420, nv40_graph_vs_count(ctx->dev)); 519 for (i = 0; i < nv40_graph_vs_count(ctx->dev); i++) 520 gr_def(ctx, 0x403420 + (i * 4), 0x00005555); 521 522 if (dev_priv->chipset != 0x40) { 523 cp_ctx(ctx, 0x403600, 1); 524 gr_def(ctx, 0x403600, 0x00000001); 525 } 526 cp_ctx(ctx, 0x403800, 1); 527 528 cp_ctx(ctx, 0x403c18, 1); 529 gr_def(ctx, 0x403c18, 0x00000001); 530 switch (dev_priv->chipset) { 531 case 0x46: 532 case 0x47: 533 case 0x49: 534 case 0x4b: 535 cp_ctx(ctx, 0x405018, 1); 536 gr_def(ctx, 0x405018, 0x08e00001); 537 cp_ctx(ctx, 0x405c24, 1); 538 gr_def(ctx, 0x405c24, 0x000e3000); 539 break; 540 } 541 if (dev_priv->chipset != 0x4e) 542 cp_ctx(ctx, 0x405800, 11); 543 cp_ctx(ctx, 0x407000, 1); 544} 545 546static void 547nv40_graph_construct_state3d_3(struct nouveau_grctx *ctx) 548{ 549 int len = nv40_graph_4097(ctx->dev) ? 0x0684 : 0x0084; 550 551 cp_out (ctx, 0x300000); 552 cp_lsr (ctx, len - 4); 553 cp_bra (ctx, SWAP_DIRECTION, SAVE, cp_swap_state3d_3_is_save); 554 cp_lsr (ctx, len); 555 cp_name(ctx, cp_swap_state3d_3_is_save); 556 cp_out (ctx, 0x800001); 557 558 ctx->ctxvals_pos += len; 559} 560 561static void 562nv40_graph_construct_shader(struct nouveau_grctx *ctx) 563{ 564 struct drm_device *dev = ctx->dev; 565 struct drm_nouveau_private *dev_priv = dev->dev_private; 566 struct nouveau_gpuobj *obj = ctx->data; 567 int vs, vs_nr, vs_len, vs_nr_b0, vs_nr_b1, b0_offset, b1_offset; 568 int offset, i; 569 570 vs_nr = nv40_graph_vs_count(ctx->dev); 571 vs_nr_b0 = 363; 572 vs_nr_b1 = dev_priv->chipset == 0x40 ? 128 : 64; 573 if (dev_priv->chipset == 0x40) { 574 b0_offset = 0x2200/4; /* 33a0 */ 575 b1_offset = 0x55a0/4; /* 1500 */ 576 vs_len = 0x6aa0/4; 577 } else 578 if (dev_priv->chipset == 0x41 || dev_priv->chipset == 0x42) { 579 b0_offset = 0x2200/4; /* 2200 */ 580 b1_offset = 0x4400/4; /* 0b00 */ 581 vs_len = 0x4f00/4; 582 } else { 583 b0_offset = 0x1d40/4; /* 2200 */ 584 b1_offset = 0x3f40/4; /* 0b00 : 0a40 */ 585 vs_len = nv40_graph_4097(dev) ? 0x4a40/4 : 0x4980/4; 586 } 587 588 cp_lsr(ctx, vs_len * vs_nr + 0x300/4); 589 cp_out(ctx, nv40_graph_4097(dev) ? 0x800041 : 0x800029); 590 591 offset = ctx->ctxvals_pos; 592 ctx->ctxvals_pos += (0x0300/4 + (vs_nr * vs_len)); 593 594 if (ctx->mode != NOUVEAU_GRCTX_VALS) 595 return; 596 597 offset += 0x0280/4; 598 for (i = 0; i < 16; i++, offset += 2) 599 nv_wo32(dev, obj, offset, 0x3f800000); 600 601 for (vs = 0; vs < vs_nr; vs++, offset += vs_len) { 602 for (i = 0; i < vs_nr_b0 * 6; i += 6) 603 nv_wo32(dev, obj, offset + b0_offset + i, 0x00000001); 604 for (i = 0; i < vs_nr_b1 * 4; i += 4) 605 nv_wo32(dev, obj, offset + b1_offset + i, 0x3f800000); 606 } 607} 608 609void 610nv40_grctx_init(struct nouveau_grctx *ctx) 611{ 612 /* decide whether we're loading/unloading the context */ 613 cp_bra (ctx, AUTO_SAVE, PENDING, cp_setup_save); 614 cp_bra (ctx, USER_SAVE, PENDING, cp_setup_save); 615 616 cp_name(ctx, cp_check_load); 617 cp_bra (ctx, AUTO_LOAD, PENDING, cp_setup_auto_load); 618 cp_bra (ctx, USER_LOAD, PENDING, cp_setup_load); 619 cp_bra (ctx, ALWAYS, TRUE, cp_exit); 620 621 /* setup for context load */ 622 cp_name(ctx, cp_setup_auto_load); 623 cp_wait(ctx, STATUS, IDLE); 624 cp_out (ctx, CP_NEXT_TO_SWAP); 625 cp_name(ctx, cp_setup_load); 626 cp_wait(ctx, STATUS, IDLE); 627 cp_set (ctx, SWAP_DIRECTION, LOAD); 628 cp_out (ctx, 0x00910880); /* ?? */ 629 cp_out (ctx, 0x00901ffe); /* ?? */ 630 cp_out (ctx, 0x01940000); /* ?? */ 631 cp_lsr (ctx, 0x20); 632 cp_out (ctx, 0x0060000b); /* ?? */ 633 cp_wait(ctx, UNK57, CLEAR); 634 cp_out (ctx, 0x0060000c); /* ?? */ 635 cp_bra (ctx, ALWAYS, TRUE, cp_swap_state); 636 637 /* setup for context save */ 638 cp_name(ctx, cp_setup_save); 639 cp_set (ctx, SWAP_DIRECTION, SAVE); 640 641 /* general PGRAPH state */ 642 cp_name(ctx, cp_swap_state); 643 cp_pos (ctx, 0x00020/4); 644 nv40_graph_construct_general(ctx); 645 cp_wait(ctx, STATUS, IDLE); 646 647 /* 3D state, block 1 */ 648 cp_bra (ctx, UNK54, CLEAR, cp_prepare_exit); 649 nv40_graph_construct_state3d(ctx); 650 cp_wait(ctx, STATUS, IDLE); 651 652 /* 3D state, block 2 */ 653 nv40_graph_construct_state3d_2(ctx); 654 655 /* Some other block of "random" state */ 656 nv40_graph_construct_state3d_3(ctx); 657 658 /* Per-vertex shader state */ 659 cp_pos (ctx, ctx->ctxvals_pos); 660 nv40_graph_construct_shader(ctx); 661 662 /* pre-exit state updates */ 663 cp_name(ctx, cp_prepare_exit); 664 cp_bra (ctx, SWAP_DIRECTION, SAVE, cp_check_load); 665 cp_bra (ctx, USER_SAVE, PENDING, cp_exit); 666 cp_out (ctx, CP_NEXT_TO_CURRENT); 667 668 cp_name(ctx, cp_exit); 669 cp_set (ctx, USER_SAVE, NOT_PENDING); 670 cp_set (ctx, USER_LOAD, NOT_PENDING); 671 cp_out (ctx, CP_END); 672} 673