1/* 2 * Copyright �� 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Keith Packard <keithp@keithp.com> 25 * 26 */ 27 28#include <linux/i2c.h> 29#include <linux/slab.h> 30#include "drmP.h" 31#include "drm.h" 32#include "drm_crtc.h" 33#include "drm_crtc_helper.h" 34#include "intel_drv.h" 35#include "i915_drm.h" 36#include "i915_drv.h" 37#include "drm_dp_helper.h" 38 39 40#define DP_LINK_STATUS_SIZE 6 41#define DP_LINK_CHECK_TIMEOUT (10 * 1000) 42 43#define DP_LINK_CONFIGURATION_SIZE 9 44 45#define IS_eDP(i) ((i)->base.type == INTEL_OUTPUT_EDP) 46#define IS_PCH_eDP(i) ((i)->is_pch_edp) 47 48struct intel_dp { 49 struct intel_encoder base; 50 uint32_t output_reg; 51 uint32_t DP; 52 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; 53 bool has_audio; 54 int dpms_mode; 55 uint8_t link_bw; 56 uint8_t lane_count; 57 uint8_t dpcd[4]; 58 struct i2c_adapter adapter; 59 struct i2c_algo_dp_aux_data algo; 60 bool is_pch_edp; 61}; 62 63static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) 64{ 65 return container_of(enc_to_intel_encoder(encoder), struct intel_dp, base); 66} 67 68static void intel_dp_link_train(struct intel_dp *intel_dp); 69static void intel_dp_link_down(struct intel_dp *intel_dp); 70 71void 72intel_edp_link_config (struct intel_encoder *intel_encoder, 73 int *lane_num, int *link_bw) 74{ 75 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); 76 77 *lane_num = intel_dp->lane_count; 78 if (intel_dp->link_bw == DP_LINK_BW_1_62) 79 *link_bw = 162000; 80 else if (intel_dp->link_bw == DP_LINK_BW_2_7) 81 *link_bw = 270000; 82} 83 84static int 85intel_dp_max_lane_count(struct intel_dp *intel_dp) 86{ 87 int max_lane_count = 4; 88 89 if (intel_dp->dpcd[0] >= 0x11) { 90 max_lane_count = intel_dp->dpcd[2] & 0x1f; 91 switch (max_lane_count) { 92 case 1: case 2: case 4: 93 break; 94 default: 95 max_lane_count = 4; 96 } 97 } 98 return max_lane_count; 99} 100 101static int 102intel_dp_max_link_bw(struct intel_dp *intel_dp) 103{ 104 int max_link_bw = intel_dp->dpcd[1]; 105 106 switch (max_link_bw) { 107 case DP_LINK_BW_1_62: 108 case DP_LINK_BW_2_7: 109 break; 110 default: 111 max_link_bw = DP_LINK_BW_1_62; 112 break; 113 } 114 return max_link_bw; 115} 116 117static int 118intel_dp_link_clock(uint8_t link_bw) 119{ 120 if (link_bw == DP_LINK_BW_2_7) 121 return 270000; 122 else 123 return 162000; 124} 125 126/* I think this is a fiction */ 127static int 128intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock) 129{ 130 struct drm_i915_private *dev_priv = dev->dev_private; 131 132 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) 133 return (pixel_clock * dev_priv->edp_bpp) / 8; 134 else 135 return pixel_clock * 3; 136} 137 138static int 139intel_dp_max_data_rate(int max_link_clock, int max_lanes) 140{ 141 return (max_link_clock * max_lanes * 8) / 10; 142} 143 144static int 145intel_dp_mode_valid(struct drm_connector *connector, 146 struct drm_display_mode *mode) 147{ 148 struct drm_encoder *encoder = intel_attached_encoder(connector); 149 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 150 struct drm_device *dev = connector->dev; 151 struct drm_i915_private *dev_priv = dev->dev_private; 152 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp)); 153 int max_lanes = intel_dp_max_lane_count(intel_dp); 154 155 if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) && 156 dev_priv->panel_fixed_mode) { 157 if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay) 158 return MODE_PANEL; 159 160 if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay) 161 return MODE_PANEL; 162 } 163 164 /* only refuse the mode on non eDP since we have seen some wierd eDP panels 165 which are outside spec tolerances but somehow work by magic */ 166 if (!IS_eDP(intel_dp) && 167 (intel_dp_link_required(connector->dev, intel_dp, mode->clock) 168 > intel_dp_max_data_rate(max_link_clock, max_lanes))) 169 return MODE_CLOCK_HIGH; 170 171 if (mode->clock < 10000) 172 return MODE_CLOCK_LOW; 173 174 return MODE_OK; 175} 176 177static uint32_t 178pack_aux(uint8_t *src, int src_bytes) 179{ 180 int i; 181 uint32_t v = 0; 182 183 if (src_bytes > 4) 184 src_bytes = 4; 185 for (i = 0; i < src_bytes; i++) 186 v |= ((uint32_t) src[i]) << ((3-i) * 8); 187 return v; 188} 189 190static void 191unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) 192{ 193 int i; 194 if (dst_bytes > 4) 195 dst_bytes = 4; 196 for (i = 0; i < dst_bytes; i++) 197 dst[i] = src >> ((3-i) * 8); 198} 199 200/* hrawclock is 1/4 the FSB frequency */ 201static int 202intel_hrawclk(struct drm_device *dev) 203{ 204 struct drm_i915_private *dev_priv = dev->dev_private; 205 uint32_t clkcfg; 206 207 clkcfg = I915_READ(CLKCFG); 208 switch (clkcfg & CLKCFG_FSB_MASK) { 209 case CLKCFG_FSB_400: 210 return 100; 211 case CLKCFG_FSB_533: 212 return 133; 213 case CLKCFG_FSB_667: 214 return 166; 215 case CLKCFG_FSB_800: 216 return 200; 217 case CLKCFG_FSB_1067: 218 return 266; 219 case CLKCFG_FSB_1333: 220 return 333; 221 /* these two are just a guess; one of them might be right */ 222 case CLKCFG_FSB_1600: 223 case CLKCFG_FSB_1600_ALT: 224 return 400; 225 default: 226 return 133; 227 } 228} 229 230static int 231intel_dp_aux_ch(struct intel_dp *intel_dp, 232 uint8_t *send, int send_bytes, 233 uint8_t *recv, int recv_size) 234{ 235 uint32_t output_reg = intel_dp->output_reg; 236 struct drm_device *dev = intel_dp->base.enc.dev; 237 struct drm_i915_private *dev_priv = dev->dev_private; 238 uint32_t ch_ctl = output_reg + 0x10; 239 uint32_t ch_data = ch_ctl + 4; 240 int i; 241 int recv_bytes; 242 uint32_t status; 243 uint32_t aux_clock_divider; 244 int try, precharge; 245 246 /* The clock divider is based off the hrawclk, 247 * and would like to run at 2MHz. So, take the 248 * hrawclk value and divide by 2 and use that 249 */ 250 if (IS_eDP(intel_dp)) { 251 if (IS_GEN6(dev)) 252 aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */ 253 else 254 aux_clock_divider = 225; /* eDP input clock at 450Mhz */ 255 } else if (HAS_PCH_SPLIT(dev)) 256 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */ 257 else 258 aux_clock_divider = intel_hrawclk(dev) / 2; 259 260 if (IS_GEN6(dev)) 261 precharge = 3; 262 else 263 precharge = 5; 264 265 if (I915_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) { 266 DRM_ERROR("dp_aux_ch not started status 0x%08x\n", 267 I915_READ(ch_ctl)); 268 return -EBUSY; 269 } 270 271 /* Must try at least 3 times according to DP spec */ 272 for (try = 0; try < 5; try++) { 273 /* Load the send data into the aux channel data registers */ 274 for (i = 0; i < send_bytes; i += 4) 275 I915_WRITE(ch_data + i, 276 pack_aux(send + i, send_bytes - i)); 277 278 /* Send the command and wait for it to complete */ 279 I915_WRITE(ch_ctl, 280 DP_AUX_CH_CTL_SEND_BUSY | 281 DP_AUX_CH_CTL_TIME_OUT_400us | 282 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 283 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 284 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | 285 DP_AUX_CH_CTL_DONE | 286 DP_AUX_CH_CTL_TIME_OUT_ERROR | 287 DP_AUX_CH_CTL_RECEIVE_ERROR); 288 for (;;) { 289 status = I915_READ(ch_ctl); 290 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) 291 break; 292 udelay(100); 293 } 294 295 /* Clear done status and any errors */ 296 I915_WRITE(ch_ctl, 297 status | 298 DP_AUX_CH_CTL_DONE | 299 DP_AUX_CH_CTL_TIME_OUT_ERROR | 300 DP_AUX_CH_CTL_RECEIVE_ERROR); 301 if (status & DP_AUX_CH_CTL_DONE) 302 break; 303 } 304 305 if ((status & DP_AUX_CH_CTL_DONE) == 0) { 306 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); 307 return -EBUSY; 308 } 309 310 /* Check for timeout or receive error. 311 * Timeouts occur when the sink is not connected 312 */ 313 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 314 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); 315 return -EIO; 316 } 317 318 /* Timeouts occur when the device isn't connected, so they're 319 * "normal" -- don't fill the kernel log with these */ 320 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { 321 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); 322 return -ETIMEDOUT; 323 } 324 325 /* Unload any bytes sent back from the other side */ 326 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> 327 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); 328 if (recv_bytes > recv_size) 329 recv_bytes = recv_size; 330 331 for (i = 0; i < recv_bytes; i += 4) 332 unpack_aux(I915_READ(ch_data + i), 333 recv + i, recv_bytes - i); 334 335 return recv_bytes; 336} 337 338/* Write data to the aux channel in native mode */ 339static int 340intel_dp_aux_native_write(struct intel_dp *intel_dp, 341 uint16_t address, uint8_t *send, int send_bytes) 342{ 343 int ret; 344 uint8_t msg[20]; 345 int msg_bytes; 346 uint8_t ack; 347 348 if (send_bytes > 16) 349 return -1; 350 msg[0] = AUX_NATIVE_WRITE << 4; 351 msg[1] = address >> 8; 352 msg[2] = address & 0xff; 353 msg[3] = send_bytes - 1; 354 memcpy(&msg[4], send, send_bytes); 355 msg_bytes = send_bytes + 4; 356 for (;;) { 357 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1); 358 if (ret < 0) 359 return ret; 360 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) 361 break; 362 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) 363 udelay(100); 364 else 365 return -EIO; 366 } 367 return send_bytes; 368} 369 370/* Write a single byte to the aux channel in native mode */ 371static int 372intel_dp_aux_native_write_1(struct intel_dp *intel_dp, 373 uint16_t address, uint8_t byte) 374{ 375 return intel_dp_aux_native_write(intel_dp, address, &byte, 1); 376} 377 378/* read bytes from a native aux channel */ 379static int 380intel_dp_aux_native_read(struct intel_dp *intel_dp, 381 uint16_t address, uint8_t *recv, int recv_bytes) 382{ 383 uint8_t msg[4]; 384 int msg_bytes; 385 uint8_t reply[20]; 386 int reply_bytes; 387 uint8_t ack; 388 int ret; 389 390 msg[0] = AUX_NATIVE_READ << 4; 391 msg[1] = address >> 8; 392 msg[2] = address & 0xff; 393 msg[3] = recv_bytes - 1; 394 395 msg_bytes = 4; 396 reply_bytes = recv_bytes + 1; 397 398 for (;;) { 399 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, 400 reply, reply_bytes); 401 if (ret == 0) 402 return -EPROTO; 403 if (ret < 0) 404 return ret; 405 ack = reply[0]; 406 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) { 407 memcpy(recv, reply + 1, ret - 1); 408 return ret - 1; 409 } 410 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) 411 udelay(100); 412 else 413 return -EIO; 414 } 415} 416 417static int 418intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 419 uint8_t write_byte, uint8_t *read_byte) 420{ 421 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; 422 struct intel_dp *intel_dp = container_of(adapter, 423 struct intel_dp, 424 adapter); 425 uint16_t address = algo_data->address; 426 uint8_t msg[5]; 427 uint8_t reply[2]; 428 unsigned retry; 429 int msg_bytes; 430 int reply_bytes; 431 int ret; 432 433 /* Set up the command byte */ 434 if (mode & MODE_I2C_READ) 435 msg[0] = AUX_I2C_READ << 4; 436 else 437 msg[0] = AUX_I2C_WRITE << 4; 438 439 if (!(mode & MODE_I2C_STOP)) 440 msg[0] |= AUX_I2C_MOT << 4; 441 442 msg[1] = address >> 8; 443 msg[2] = address; 444 445 switch (mode) { 446 case MODE_I2C_WRITE: 447 msg[3] = 0; 448 msg[4] = write_byte; 449 msg_bytes = 5; 450 reply_bytes = 1; 451 break; 452 case MODE_I2C_READ: 453 msg[3] = 0; 454 msg_bytes = 4; 455 reply_bytes = 2; 456 break; 457 default: 458 msg_bytes = 3; 459 reply_bytes = 1; 460 break; 461 } 462 463 for (retry = 0; retry < 5; retry++) { 464 ret = intel_dp_aux_ch(intel_dp, 465 msg, msg_bytes, 466 reply, reply_bytes); 467 if (ret < 0) { 468 DRM_DEBUG_KMS("aux_ch failed %d\n", ret); 469 return ret; 470 } 471 472 switch (reply[0] & AUX_NATIVE_REPLY_MASK) { 473 case AUX_NATIVE_REPLY_ACK: 474 /* I2C-over-AUX Reply field is only valid 475 * when paired with AUX ACK. 476 */ 477 break; 478 case AUX_NATIVE_REPLY_NACK: 479 DRM_DEBUG_KMS("aux_ch native nack\n"); 480 return -EREMOTEIO; 481 case AUX_NATIVE_REPLY_DEFER: 482 udelay(100); 483 continue; 484 default: 485 DRM_ERROR("aux_ch invalid native reply 0x%02x\n", 486 reply[0]); 487 return -EREMOTEIO; 488 } 489 490 switch (reply[0] & AUX_I2C_REPLY_MASK) { 491 case AUX_I2C_REPLY_ACK: 492 if (mode == MODE_I2C_READ) { 493 *read_byte = reply[1]; 494 } 495 return reply_bytes - 1; 496 case AUX_I2C_REPLY_NACK: 497 DRM_DEBUG_KMS("aux_i2c nack\n"); 498 return -EREMOTEIO; 499 case AUX_I2C_REPLY_DEFER: 500 DRM_DEBUG_KMS("aux_i2c defer\n"); 501 udelay(100); 502 break; 503 default: 504 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]); 505 return -EREMOTEIO; 506 } 507 } 508 509 DRM_ERROR("too many retries, giving up\n"); 510 return -EREMOTEIO; 511} 512 513static int 514intel_dp_i2c_init(struct intel_dp *intel_dp, 515 struct intel_connector *intel_connector, const char *name) 516{ 517 DRM_DEBUG_KMS("i2c_init %s\n", name); 518 intel_dp->algo.running = false; 519 intel_dp->algo.address = 0; 520 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch; 521 522 memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter)); 523 intel_dp->adapter.owner = THIS_MODULE; 524 intel_dp->adapter.class = I2C_CLASS_DDC; 525 strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); 526 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; 527 intel_dp->adapter.algo_data = &intel_dp->algo; 528 intel_dp->adapter.dev.parent = &intel_connector->base.kdev; 529 530 return i2c_dp_aux_add_bus(&intel_dp->adapter); 531} 532 533static bool 534intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, 535 struct drm_display_mode *adjusted_mode) 536{ 537 struct drm_device *dev = encoder->dev; 538 struct drm_i915_private *dev_priv = dev->dev_private; 539 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 540 int lane_count, clock; 541 int max_lane_count = intel_dp_max_lane_count(intel_dp); 542 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; 543 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; 544 545 if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) && 546 dev_priv->panel_fixed_mode) { 547 intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode); 548 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN, 549 mode, adjusted_mode); 550 /* 551 * the mode->clock is used to calculate the Data&Link M/N 552 * of the pipe. For the eDP the fixed clock should be used. 553 */ 554 mode->clock = dev_priv->panel_fixed_mode->clock; 555 } 556 557 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { 558 for (clock = 0; clock <= max_clock; clock++) { 559 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count); 560 561 if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock) 562 <= link_avail) { 563 intel_dp->link_bw = bws[clock]; 564 intel_dp->lane_count = lane_count; 565 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); 566 DRM_DEBUG_KMS("Display port link bw %02x lane " 567 "count %d clock %d\n", 568 intel_dp->link_bw, intel_dp->lane_count, 569 adjusted_mode->clock); 570 return true; 571 } 572 } 573 } 574 575 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) { 576 /* okay we failed just pick the highest */ 577 intel_dp->lane_count = max_lane_count; 578 intel_dp->link_bw = bws[max_clock]; 579 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); 580 DRM_DEBUG_KMS("Force picking display port link bw %02x lane " 581 "count %d clock %d\n", 582 intel_dp->link_bw, intel_dp->lane_count, 583 adjusted_mode->clock); 584 585 return true; 586 } 587 588 return false; 589} 590 591struct intel_dp_m_n { 592 uint32_t tu; 593 uint32_t gmch_m; 594 uint32_t gmch_n; 595 uint32_t link_m; 596 uint32_t link_n; 597}; 598 599static void 600intel_reduce_ratio(uint32_t *num, uint32_t *den) 601{ 602 while (*num > 0xffffff || *den > 0xffffff) { 603 *num >>= 1; 604 *den >>= 1; 605 } 606} 607 608static void 609intel_dp_compute_m_n(int bpp, 610 int nlanes, 611 int pixel_clock, 612 int link_clock, 613 struct intel_dp_m_n *m_n) 614{ 615 m_n->tu = 64; 616 m_n->gmch_m = (pixel_clock * bpp) >> 3; 617 m_n->gmch_n = link_clock * nlanes; 618 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); 619 m_n->link_m = pixel_clock; 620 m_n->link_n = link_clock; 621 intel_reduce_ratio(&m_n->link_m, &m_n->link_n); 622} 623 624bool intel_pch_has_edp(struct drm_crtc *crtc) 625{ 626 struct drm_device *dev = crtc->dev; 627 struct drm_mode_config *mode_config = &dev->mode_config; 628 struct drm_encoder *encoder; 629 630 list_for_each_entry(encoder, &mode_config->encoder_list, head) { 631 struct intel_dp *intel_dp; 632 633 if (encoder->crtc != crtc) 634 continue; 635 636 intel_dp = enc_to_intel_dp(encoder); 637 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) 638 return intel_dp->is_pch_edp; 639 } 640 return false; 641} 642 643void 644intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, 645 struct drm_display_mode *adjusted_mode) 646{ 647 struct drm_device *dev = crtc->dev; 648 struct drm_mode_config *mode_config = &dev->mode_config; 649 struct drm_encoder *encoder; 650 struct drm_i915_private *dev_priv = dev->dev_private; 651 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 652 int lane_count = 4, bpp = 24; 653 struct intel_dp_m_n m_n; 654 655 /* 656 * Find the lane count in the intel_encoder private 657 */ 658 list_for_each_entry(encoder, &mode_config->encoder_list, head) { 659 struct intel_dp *intel_dp; 660 661 if (encoder->crtc != crtc) 662 continue; 663 664 intel_dp = enc_to_intel_dp(encoder); 665 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) { 666 lane_count = intel_dp->lane_count; 667 if (IS_PCH_eDP(intel_dp)) 668 bpp = dev_priv->edp_bpp; 669 break; 670 } 671 } 672 673 /* 674 * Compute the GMCH and Link ratios. The '3' here is 675 * the number of bytes_per_pixel post-LUT, which we always 676 * set up for 8-bits of R/G/B, or 3 bytes total. 677 */ 678 intel_dp_compute_m_n(bpp, lane_count, 679 mode->clock, adjusted_mode->clock, &m_n); 680 681 if (HAS_PCH_SPLIT(dev)) { 682 if (intel_crtc->pipe == 0) { 683 I915_WRITE(TRANSA_DATA_M1, 684 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | 685 m_n.gmch_m); 686 I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n); 687 I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m); 688 I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n); 689 } else { 690 I915_WRITE(TRANSB_DATA_M1, 691 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | 692 m_n.gmch_m); 693 I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n); 694 I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m); 695 I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n); 696 } 697 } else { 698 if (intel_crtc->pipe == 0) { 699 I915_WRITE(PIPEA_GMCH_DATA_M, 700 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | 701 m_n.gmch_m); 702 I915_WRITE(PIPEA_GMCH_DATA_N, 703 m_n.gmch_n); 704 I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m); 705 I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n); 706 } else { 707 I915_WRITE(PIPEB_GMCH_DATA_M, 708 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | 709 m_n.gmch_m); 710 I915_WRITE(PIPEB_GMCH_DATA_N, 711 m_n.gmch_n); 712 I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m); 713 I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n); 714 } 715 } 716} 717 718static void 719intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, 720 struct drm_display_mode *adjusted_mode) 721{ 722 struct drm_device *dev = encoder->dev; 723 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 724 struct drm_crtc *crtc = intel_dp->base.enc.crtc; 725 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 726 727 intel_dp->DP = (DP_VOLTAGE_0_4 | 728 DP_PRE_EMPHASIS_0); 729 730 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 731 intel_dp->DP |= DP_SYNC_HS_HIGH; 732 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 733 intel_dp->DP |= DP_SYNC_VS_HIGH; 734 735 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) 736 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 737 else 738 intel_dp->DP |= DP_LINK_TRAIN_OFF; 739 740 switch (intel_dp->lane_count) { 741 case 1: 742 intel_dp->DP |= DP_PORT_WIDTH_1; 743 break; 744 case 2: 745 intel_dp->DP |= DP_PORT_WIDTH_2; 746 break; 747 case 4: 748 intel_dp->DP |= DP_PORT_WIDTH_4; 749 break; 750 } 751 if (intel_dp->has_audio) 752 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; 753 754 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); 755 intel_dp->link_configuration[0] = intel_dp->link_bw; 756 intel_dp->link_configuration[1] = intel_dp->lane_count; 757 758 /* 759 * Check for DPCD version > 1.1 and enhanced framing support 760 */ 761 if (intel_dp->dpcd[0] >= 0x11 && (intel_dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)) { 762 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 763 intel_dp->DP |= DP_ENHANCED_FRAMING; 764 } 765 766 /* CPT DP's pipe select is decided in TRANS_DP_CTL */ 767 if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev)) 768 intel_dp->DP |= DP_PIPEB_SELECT; 769 770 if (IS_eDP(intel_dp)) { 771 /* don't miss out required setting for eDP */ 772 intel_dp->DP |= DP_PLL_ENABLE; 773 if (adjusted_mode->clock < 200000) 774 intel_dp->DP |= DP_PLL_FREQ_160MHZ; 775 else 776 intel_dp->DP |= DP_PLL_FREQ_270MHZ; 777 } 778} 779 780static void ironlake_edp_panel_on (struct drm_device *dev) 781{ 782 struct drm_i915_private *dev_priv = dev->dev_private; 783 u32 pp; 784 785 if (I915_READ(PCH_PP_STATUS) & PP_ON) 786 return; 787 788 pp = I915_READ(PCH_PP_CONTROL); 789 790 pp &= ~PANEL_POWER_RESET; 791 I915_WRITE(PCH_PP_CONTROL, pp); 792 POSTING_READ(PCH_PP_CONTROL); 793 794 pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON; 795 I915_WRITE(PCH_PP_CONTROL, pp); 796 797 if (wait_for(I915_READ(PCH_PP_STATUS) & PP_ON, 5000, 10)) 798 DRM_ERROR("panel on wait timed out: 0x%08x\n", 799 I915_READ(PCH_PP_STATUS)); 800 801 pp &= ~(PANEL_UNLOCK_REGS | EDP_FORCE_VDD); 802 pp |= PANEL_POWER_RESET; /* restore panel reset bit */ 803 I915_WRITE(PCH_PP_CONTROL, pp); 804 POSTING_READ(PCH_PP_CONTROL); 805} 806 807static void ironlake_edp_panel_off (struct drm_device *dev) 808{ 809 struct drm_i915_private *dev_priv = dev->dev_private; 810 u32 pp; 811 812 pp = I915_READ(PCH_PP_CONTROL); 813 814 pp &= ~PANEL_POWER_RESET; 815 I915_WRITE(PCH_PP_CONTROL, pp); 816 POSTING_READ(PCH_PP_CONTROL); 817 818 pp &= ~POWER_TARGET_ON; 819 I915_WRITE(PCH_PP_CONTROL, pp); 820 821 if (wait_for((I915_READ(PCH_PP_STATUS) & PP_ON) == 0, 5000, 10)) 822 DRM_ERROR("panel off wait timed out: 0x%08x\n", 823 I915_READ(PCH_PP_STATUS)); 824 825 /* Make sure VDD is enabled so DP AUX will work */ 826 pp |= EDP_FORCE_VDD | PANEL_POWER_RESET; /* restore panel reset bit */ 827 I915_WRITE(PCH_PP_CONTROL, pp); 828 POSTING_READ(PCH_PP_CONTROL); 829} 830 831static void ironlake_edp_backlight_on (struct drm_device *dev) 832{ 833 struct drm_i915_private *dev_priv = dev->dev_private; 834 u32 pp; 835 836 DRM_DEBUG_KMS("\n"); 837 pp = I915_READ(PCH_PP_CONTROL); 838 pp |= EDP_BLC_ENABLE; 839 I915_WRITE(PCH_PP_CONTROL, pp); 840} 841 842static void ironlake_edp_backlight_off (struct drm_device *dev) 843{ 844 struct drm_i915_private *dev_priv = dev->dev_private; 845 u32 pp; 846 847 DRM_DEBUG_KMS("\n"); 848 pp = I915_READ(PCH_PP_CONTROL); 849 pp &= ~EDP_BLC_ENABLE; 850 I915_WRITE(PCH_PP_CONTROL, pp); 851} 852 853static void ironlake_edp_pll_on(struct drm_encoder *encoder) 854{ 855 struct drm_device *dev = encoder->dev; 856 struct drm_i915_private *dev_priv = dev->dev_private; 857 u32 dpa_ctl; 858 859 DRM_DEBUG_KMS("\n"); 860 dpa_ctl = I915_READ(DP_A); 861 dpa_ctl &= ~DP_PLL_ENABLE; 862 I915_WRITE(DP_A, dpa_ctl); 863} 864 865static void ironlake_edp_pll_off(struct drm_encoder *encoder) 866{ 867 struct drm_device *dev = encoder->dev; 868 struct drm_i915_private *dev_priv = dev->dev_private; 869 u32 dpa_ctl; 870 871 dpa_ctl = I915_READ(DP_A); 872 dpa_ctl |= DP_PLL_ENABLE; 873 I915_WRITE(DP_A, dpa_ctl); 874 udelay(200); 875} 876 877static void intel_dp_prepare(struct drm_encoder *encoder) 878{ 879 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 880 struct drm_device *dev = encoder->dev; 881 struct drm_i915_private *dev_priv = dev->dev_private; 882 uint32_t dp_reg = I915_READ(intel_dp->output_reg); 883 884 if (IS_eDP(intel_dp)) { 885 ironlake_edp_backlight_off(dev); 886 ironlake_edp_panel_on(dev); 887 ironlake_edp_pll_on(encoder); 888 } 889 if (dp_reg & DP_PORT_EN) 890 intel_dp_link_down(intel_dp); 891} 892 893static void intel_dp_commit(struct drm_encoder *encoder) 894{ 895 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 896 struct drm_device *dev = encoder->dev; 897 struct drm_i915_private *dev_priv = dev->dev_private; 898 uint32_t dp_reg = I915_READ(intel_dp->output_reg); 899 900 if (!(dp_reg & DP_PORT_EN)) { 901 intel_dp_link_train(intel_dp); 902 } 903 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) 904 ironlake_edp_backlight_on(dev); 905} 906 907static void 908intel_dp_dpms(struct drm_encoder *encoder, int mode) 909{ 910 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 911 struct drm_device *dev = encoder->dev; 912 struct drm_i915_private *dev_priv = dev->dev_private; 913 uint32_t dp_reg = I915_READ(intel_dp->output_reg); 914 915 if (mode != DRM_MODE_DPMS_ON) { 916 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) { 917 ironlake_edp_backlight_off(dev); 918 ironlake_edp_panel_off(dev); 919 } 920 if (dp_reg & DP_PORT_EN) 921 intel_dp_link_down(intel_dp); 922 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) 923 ironlake_edp_pll_off(encoder); 924 } else { 925 if (!(dp_reg & DP_PORT_EN)) { 926 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) 927 ironlake_edp_panel_on(dev); 928 intel_dp_link_train(intel_dp); 929 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) 930 ironlake_edp_backlight_on(dev); 931 } 932 } 933 intel_dp->dpms_mode = mode; 934} 935 936/* 937 * Fetch AUX CH registers 0x202 - 0x207 which contain 938 * link status information 939 */ 940static bool 941intel_dp_get_link_status(struct intel_dp *intel_dp, 942 uint8_t link_status[DP_LINK_STATUS_SIZE]) 943{ 944 int ret; 945 946 ret = intel_dp_aux_native_read(intel_dp, 947 DP_LANE0_1_STATUS, 948 link_status, DP_LINK_STATUS_SIZE); 949 if (ret != DP_LINK_STATUS_SIZE) 950 return false; 951 return true; 952} 953 954static uint8_t 955intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE], 956 int r) 957{ 958 return link_status[r - DP_LANE0_1_STATUS]; 959} 960 961static uint8_t 962intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE], 963 int lane) 964{ 965 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 966 int s = ((lane & 1) ? 967 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : 968 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); 969 uint8_t l = intel_dp_link_status(link_status, i); 970 971 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; 972} 973 974static uint8_t 975intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE], 976 int lane) 977{ 978 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 979 int s = ((lane & 1) ? 980 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : 981 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); 982 uint8_t l = intel_dp_link_status(link_status, i); 983 984 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; 985} 986 987 988 989/* 990 * These are source-specific values; current Intel hardware supports 991 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB 992 */ 993#define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800 994 995static uint8_t 996intel_dp_pre_emphasis_max(uint8_t voltage_swing) 997{ 998 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 999 case DP_TRAIN_VOLTAGE_SWING_400: 1000 return DP_TRAIN_PRE_EMPHASIS_6; 1001 case DP_TRAIN_VOLTAGE_SWING_600: 1002 return DP_TRAIN_PRE_EMPHASIS_6; 1003 case DP_TRAIN_VOLTAGE_SWING_800: 1004 return DP_TRAIN_PRE_EMPHASIS_3_5; 1005 case DP_TRAIN_VOLTAGE_SWING_1200: 1006 default: 1007 return DP_TRAIN_PRE_EMPHASIS_0; 1008 } 1009} 1010 1011static void 1012intel_get_adjust_train(struct intel_dp *intel_dp, 1013 uint8_t link_status[DP_LINK_STATUS_SIZE], 1014 int lane_count, 1015 uint8_t train_set[4]) 1016{ 1017 uint8_t v = 0; 1018 uint8_t p = 0; 1019 int lane; 1020 1021 for (lane = 0; lane < lane_count; lane++) { 1022 uint8_t this_v = intel_get_adjust_request_voltage(link_status, lane); 1023 uint8_t this_p = intel_get_adjust_request_pre_emphasis(link_status, lane); 1024 1025 if (this_v > v) 1026 v = this_v; 1027 if (this_p > p) 1028 p = this_p; 1029 } 1030 1031 if (v >= I830_DP_VOLTAGE_MAX) 1032 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED; 1033 1034 if (p >= intel_dp_pre_emphasis_max(v)) 1035 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 1036 1037 for (lane = 0; lane < 4; lane++) 1038 train_set[lane] = v | p; 1039} 1040 1041static uint32_t 1042intel_dp_signal_levels(uint8_t train_set, int lane_count) 1043{ 1044 uint32_t signal_levels = 0; 1045 1046 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 1047 case DP_TRAIN_VOLTAGE_SWING_400: 1048 default: 1049 signal_levels |= DP_VOLTAGE_0_4; 1050 break; 1051 case DP_TRAIN_VOLTAGE_SWING_600: 1052 signal_levels |= DP_VOLTAGE_0_6; 1053 break; 1054 case DP_TRAIN_VOLTAGE_SWING_800: 1055 signal_levels |= DP_VOLTAGE_0_8; 1056 break; 1057 case DP_TRAIN_VOLTAGE_SWING_1200: 1058 signal_levels |= DP_VOLTAGE_1_2; 1059 break; 1060 } 1061 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 1062 case DP_TRAIN_PRE_EMPHASIS_0: 1063 default: 1064 signal_levels |= DP_PRE_EMPHASIS_0; 1065 break; 1066 case DP_TRAIN_PRE_EMPHASIS_3_5: 1067 signal_levels |= DP_PRE_EMPHASIS_3_5; 1068 break; 1069 case DP_TRAIN_PRE_EMPHASIS_6: 1070 signal_levels |= DP_PRE_EMPHASIS_6; 1071 break; 1072 case DP_TRAIN_PRE_EMPHASIS_9_5: 1073 signal_levels |= DP_PRE_EMPHASIS_9_5; 1074 break; 1075 } 1076 return signal_levels; 1077} 1078 1079/* Gen6's DP voltage swing and pre-emphasis control */ 1080static uint32_t 1081intel_gen6_edp_signal_levels(uint8_t train_set) 1082{ 1083 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1084 DP_TRAIN_PRE_EMPHASIS_MASK); 1085 switch (signal_levels) { 1086 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 1087 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 1088 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 1089 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 1090 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; 1091 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 1092 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: 1093 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; 1094 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 1095 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 1096 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; 1097 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 1098 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: 1099 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; 1100 default: 1101 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 1102 "0x%x\n", signal_levels); 1103 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 1104 } 1105} 1106 1107static uint8_t 1108intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE], 1109 int lane) 1110{ 1111 int i = DP_LANE0_1_STATUS + (lane >> 1); 1112 int s = (lane & 1) * 4; 1113 uint8_t l = intel_dp_link_status(link_status, i); 1114 1115 return (l >> s) & 0xf; 1116} 1117 1118/* Check for clock recovery is done on all channels */ 1119static bool 1120intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) 1121{ 1122 int lane; 1123 uint8_t lane_status; 1124 1125 for (lane = 0; lane < lane_count; lane++) { 1126 lane_status = intel_get_lane_status(link_status, lane); 1127 if ((lane_status & DP_LANE_CR_DONE) == 0) 1128 return false; 1129 } 1130 return true; 1131} 1132 1133/* Check to see if channel eq is done on all channels */ 1134#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\ 1135 DP_LANE_CHANNEL_EQ_DONE|\ 1136 DP_LANE_SYMBOL_LOCKED) 1137static bool 1138intel_channel_eq_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) 1139{ 1140 uint8_t lane_align; 1141 uint8_t lane_status; 1142 int lane; 1143 1144 lane_align = intel_dp_link_status(link_status, 1145 DP_LANE_ALIGN_STATUS_UPDATED); 1146 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) 1147 return false; 1148 for (lane = 0; lane < lane_count; lane++) { 1149 lane_status = intel_get_lane_status(link_status, lane); 1150 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS) 1151 return false; 1152 } 1153 return true; 1154} 1155 1156static bool 1157intel_dp_set_link_train(struct intel_dp *intel_dp, 1158 uint32_t dp_reg_value, 1159 uint8_t dp_train_pat, 1160 uint8_t train_set[4]) 1161{ 1162 struct drm_device *dev = intel_dp->base.enc.dev; 1163 struct drm_i915_private *dev_priv = dev->dev_private; 1164 int ret; 1165 1166 I915_WRITE(intel_dp->output_reg, dp_reg_value); 1167 POSTING_READ(intel_dp->output_reg); 1168 1169 intel_dp_aux_native_write_1(intel_dp, 1170 DP_TRAINING_PATTERN_SET, 1171 dp_train_pat); 1172 1173 ret = intel_dp_aux_native_write(intel_dp, 1174 DP_TRAINING_LANE0_SET, train_set, 4); 1175 if (ret != 4) 1176 return false; 1177 1178 return true; 1179} 1180 1181static void 1182intel_dp_link_train(struct intel_dp *intel_dp) 1183{ 1184 struct drm_device *dev = intel_dp->base.enc.dev; 1185 struct drm_i915_private *dev_priv = dev->dev_private; 1186 uint8_t train_set[4]; 1187 uint8_t link_status[DP_LINK_STATUS_SIZE]; 1188 int i; 1189 uint8_t voltage; 1190 bool clock_recovery = false; 1191 bool channel_eq = false; 1192 int tries; 1193 u32 reg; 1194 uint32_t DP = intel_dp->DP; 1195 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.enc.crtc); 1196 1197 /* Enable output, wait for it to become active */ 1198 I915_WRITE(intel_dp->output_reg, intel_dp->DP); 1199 POSTING_READ(intel_dp->output_reg); 1200 intel_wait_for_vblank(dev, intel_crtc->pipe); 1201 1202 /* Write the link configuration data */ 1203 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, 1204 intel_dp->link_configuration, 1205 DP_LINK_CONFIGURATION_SIZE); 1206 1207 DP |= DP_PORT_EN; 1208 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) 1209 DP &= ~DP_LINK_TRAIN_MASK_CPT; 1210 else 1211 DP &= ~DP_LINK_TRAIN_MASK; 1212 memset(train_set, 0, 4); 1213 voltage = 0xff; 1214 tries = 0; 1215 clock_recovery = false; 1216 for (;;) { 1217 /* Use train_set[0] to set the voltage and pre emphasis values */ 1218 uint32_t signal_levels; 1219 if (IS_GEN6(dev) && IS_eDP(intel_dp)) { 1220 signal_levels = intel_gen6_edp_signal_levels(train_set[0]); 1221 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; 1222 } else { 1223 signal_levels = intel_dp_signal_levels(train_set[0], intel_dp->lane_count); 1224 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; 1225 } 1226 1227 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) 1228 reg = DP | DP_LINK_TRAIN_PAT_1_CPT; 1229 else 1230 reg = DP | DP_LINK_TRAIN_PAT_1; 1231 1232 if (!intel_dp_set_link_train(intel_dp, reg, 1233 DP_TRAINING_PATTERN_1, train_set)) 1234 break; 1235 /* Set training pattern 1 */ 1236 1237 udelay(100); 1238 if (!intel_dp_get_link_status(intel_dp, link_status)) 1239 break; 1240 1241 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) { 1242 clock_recovery = true; 1243 break; 1244 } 1245 1246 /* Check to see if we've tried the max voltage */ 1247 for (i = 0; i < intel_dp->lane_count; i++) 1248 if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) 1249 break; 1250 if (i == intel_dp->lane_count) 1251 break; 1252 1253 /* Check to see if we've tried the same voltage 5 times */ 1254 if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { 1255 ++tries; 1256 if (tries == 5) 1257 break; 1258 } else 1259 tries = 0; 1260 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 1261 1262 /* Compute new train_set as requested by target */ 1263 intel_get_adjust_train(intel_dp, link_status, intel_dp->lane_count, train_set); 1264 } 1265 1266 /* channel equalization */ 1267 tries = 0; 1268 channel_eq = false; 1269 for (;;) { 1270 /* Use train_set[0] to set the voltage and pre emphasis values */ 1271 uint32_t signal_levels; 1272 1273 if (IS_GEN6(dev) && IS_eDP(intel_dp)) { 1274 signal_levels = intel_gen6_edp_signal_levels(train_set[0]); 1275 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; 1276 } else { 1277 signal_levels = intel_dp_signal_levels(train_set[0], intel_dp->lane_count); 1278 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; 1279 } 1280 1281 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) 1282 reg = DP | DP_LINK_TRAIN_PAT_2_CPT; 1283 else 1284 reg = DP | DP_LINK_TRAIN_PAT_2; 1285 1286 /* channel eq pattern */ 1287 if (!intel_dp_set_link_train(intel_dp, reg, 1288 DP_TRAINING_PATTERN_2, train_set)) 1289 break; 1290 1291 udelay(400); 1292 if (!intel_dp_get_link_status(intel_dp, link_status)) 1293 break; 1294 1295 if (intel_channel_eq_ok(link_status, intel_dp->lane_count)) { 1296 channel_eq = true; 1297 break; 1298 } 1299 1300 /* Try 5 times */ 1301 if (tries > 5) 1302 break; 1303 1304 /* Compute new train_set as requested by target */ 1305 intel_get_adjust_train(intel_dp, link_status, intel_dp->lane_count, train_set); 1306 ++tries; 1307 } 1308 1309 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) 1310 reg = DP | DP_LINK_TRAIN_OFF_CPT; 1311 else 1312 reg = DP | DP_LINK_TRAIN_OFF; 1313 1314 I915_WRITE(intel_dp->output_reg, reg); 1315 POSTING_READ(intel_dp->output_reg); 1316 intel_dp_aux_native_write_1(intel_dp, 1317 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE); 1318} 1319 1320static void 1321intel_dp_link_down(struct intel_dp *intel_dp) 1322{ 1323 struct drm_device *dev = intel_dp->base.enc.dev; 1324 struct drm_i915_private *dev_priv = dev->dev_private; 1325 uint32_t DP = intel_dp->DP; 1326 1327 DRM_DEBUG_KMS("\n"); 1328 1329 if (IS_eDP(intel_dp)) { 1330 DP &= ~DP_PLL_ENABLE; 1331 I915_WRITE(intel_dp->output_reg, DP); 1332 POSTING_READ(intel_dp->output_reg); 1333 udelay(100); 1334 } 1335 1336 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) { 1337 DP &= ~DP_LINK_TRAIN_MASK_CPT; 1338 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); 1339 POSTING_READ(intel_dp->output_reg); 1340 } else { 1341 DP &= ~DP_LINK_TRAIN_MASK; 1342 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); 1343 POSTING_READ(intel_dp->output_reg); 1344 } 1345 1346 udelay(17000); 1347 1348 if (IS_eDP(intel_dp)) 1349 DP |= DP_LINK_TRAIN_OFF; 1350 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); 1351 POSTING_READ(intel_dp->output_reg); 1352} 1353 1354/* 1355 * According to DP spec 1356 * 5.1.2: 1357 * 1. Read DPCD 1358 * 2. Configure link according to Receiver Capabilities 1359 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 1360 * 4. Check link status on receipt of hot-plug interrupt 1361 */ 1362 1363static void 1364intel_dp_check_link_status(struct intel_dp *intel_dp) 1365{ 1366 uint8_t link_status[DP_LINK_STATUS_SIZE]; 1367 1368 if (!intel_dp->base.enc.crtc) 1369 return; 1370 1371 if (!intel_dp_get_link_status(intel_dp, link_status)) { 1372 intel_dp_link_down(intel_dp); 1373 return; 1374 } 1375 1376 if (!intel_channel_eq_ok(link_status, intel_dp->lane_count)) 1377 intel_dp_link_train(intel_dp); 1378} 1379 1380static enum drm_connector_status 1381ironlake_dp_detect(struct drm_connector *connector) 1382{ 1383 struct drm_encoder *encoder = intel_attached_encoder(connector); 1384 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1385 enum drm_connector_status status; 1386 1387 status = connector_status_disconnected; 1388 if (intel_dp_aux_native_read(intel_dp, 1389 0x000, intel_dp->dpcd, 1390 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd)) 1391 { 1392 if (intel_dp->dpcd[0] != 0) 1393 status = connector_status_connected; 1394 } 1395 DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", intel_dp->dpcd[0], 1396 intel_dp->dpcd[1], intel_dp->dpcd[2], intel_dp->dpcd[3]); 1397 return status; 1398} 1399 1400/** 1401 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection. 1402 * 1403 * \return true if DP port is connected. 1404 * \return false if DP port is disconnected. 1405 */ 1406static enum drm_connector_status 1407intel_dp_detect(struct drm_connector *connector, bool force) 1408{ 1409 struct drm_encoder *encoder = intel_attached_encoder(connector); 1410 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1411 struct drm_device *dev = intel_dp->base.enc.dev; 1412 struct drm_i915_private *dev_priv = dev->dev_private; 1413 uint32_t temp, bit; 1414 enum drm_connector_status status; 1415 1416 intel_dp->has_audio = false; 1417 1418 if (HAS_PCH_SPLIT(dev)) 1419 return ironlake_dp_detect(connector); 1420 1421 switch (intel_dp->output_reg) { 1422 case DP_B: 1423 bit = DPB_HOTPLUG_INT_STATUS; 1424 break; 1425 case DP_C: 1426 bit = DPC_HOTPLUG_INT_STATUS; 1427 break; 1428 case DP_D: 1429 bit = DPD_HOTPLUG_INT_STATUS; 1430 break; 1431 default: 1432 return connector_status_unknown; 1433 } 1434 1435 temp = I915_READ(PORT_HOTPLUG_STAT); 1436 1437 if ((temp & bit) == 0) 1438 return connector_status_disconnected; 1439 1440 status = connector_status_disconnected; 1441 if (intel_dp_aux_native_read(intel_dp, 1442 0x000, intel_dp->dpcd, 1443 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd)) 1444 { 1445 if (intel_dp->dpcd[0] != 0) 1446 status = connector_status_connected; 1447 } 1448 return status; 1449} 1450 1451static int intel_dp_get_modes(struct drm_connector *connector) 1452{ 1453 struct drm_encoder *encoder = intel_attached_encoder(connector); 1454 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1455 struct drm_device *dev = intel_dp->base.enc.dev; 1456 struct drm_i915_private *dev_priv = dev->dev_private; 1457 int ret; 1458 1459 /* We should parse the EDID data and find out if it has an audio sink 1460 */ 1461 1462 ret = intel_ddc_get_modes(connector, intel_dp->base.ddc_bus); 1463 if (ret) { 1464 if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) && 1465 !dev_priv->panel_fixed_mode) { 1466 struct drm_display_mode *newmode; 1467 list_for_each_entry(newmode, &connector->probed_modes, 1468 head) { 1469 if (newmode->type & DRM_MODE_TYPE_PREFERRED) { 1470 dev_priv->panel_fixed_mode = 1471 drm_mode_duplicate(dev, newmode); 1472 break; 1473 } 1474 } 1475 } 1476 1477 return ret; 1478 } 1479 1480 /* if eDP has no EDID, try to use fixed panel mode from VBT */ 1481 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) { 1482 if (dev_priv->panel_fixed_mode != NULL) { 1483 struct drm_display_mode *mode; 1484 mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode); 1485 drm_mode_probed_add(connector, mode); 1486 return 1; 1487 } 1488 } 1489 return 0; 1490} 1491 1492static void 1493intel_dp_destroy (struct drm_connector *connector) 1494{ 1495 drm_sysfs_connector_remove(connector); 1496 drm_connector_cleanup(connector); 1497 kfree(connector); 1498} 1499 1500static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { 1501 .dpms = intel_dp_dpms, 1502 .mode_fixup = intel_dp_mode_fixup, 1503 .prepare = intel_dp_prepare, 1504 .mode_set = intel_dp_mode_set, 1505 .commit = intel_dp_commit, 1506}; 1507 1508static const struct drm_connector_funcs intel_dp_connector_funcs = { 1509 .dpms = drm_helper_connector_dpms, 1510 .detect = intel_dp_detect, 1511 .fill_modes = drm_helper_probe_single_connector_modes, 1512 .destroy = intel_dp_destroy, 1513}; 1514 1515static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { 1516 .get_modes = intel_dp_get_modes, 1517 .mode_valid = intel_dp_mode_valid, 1518 .best_encoder = intel_attached_encoder, 1519}; 1520 1521static const struct drm_encoder_funcs intel_dp_enc_funcs = { 1522 .destroy = intel_encoder_destroy, 1523}; 1524 1525void 1526intel_dp_hot_plug(struct intel_encoder *intel_encoder) 1527{ 1528 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); 1529 1530 if (intel_dp->dpms_mode == DRM_MODE_DPMS_ON) 1531 intel_dp_check_link_status(intel_dp); 1532} 1533 1534/* Return which DP Port should be selected for Transcoder DP control */ 1535int 1536intel_trans_dp_port_sel (struct drm_crtc *crtc) 1537{ 1538 struct drm_device *dev = crtc->dev; 1539 struct drm_mode_config *mode_config = &dev->mode_config; 1540 struct drm_encoder *encoder; 1541 1542 list_for_each_entry(encoder, &mode_config->encoder_list, head) { 1543 struct intel_dp *intel_dp; 1544 1545 if (encoder->crtc != crtc) 1546 continue; 1547 1548 intel_dp = enc_to_intel_dp(encoder); 1549 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) 1550 return intel_dp->output_reg; 1551 } 1552 1553 return -1; 1554} 1555 1556/* check the VBT to see whether the eDP is on DP-D port */ 1557bool intel_dpd_is_edp(struct drm_device *dev) 1558{ 1559 struct drm_i915_private *dev_priv = dev->dev_private; 1560 struct child_device_config *p_child; 1561 int i; 1562 1563 if (!dev_priv->child_dev_num) 1564 return false; 1565 1566 for (i = 0; i < dev_priv->child_dev_num; i++) { 1567 p_child = dev_priv->child_dev + i; 1568 1569 if (p_child->dvo_port == PORT_IDPD && 1570 p_child->device_type == DEVICE_TYPE_eDP) 1571 return true; 1572 } 1573 return false; 1574} 1575 1576void 1577intel_dp_init(struct drm_device *dev, int output_reg) 1578{ 1579 struct drm_i915_private *dev_priv = dev->dev_private; 1580 struct drm_connector *connector; 1581 struct intel_dp *intel_dp; 1582 struct intel_encoder *intel_encoder; 1583 struct intel_connector *intel_connector; 1584 const char *name = NULL; 1585 int type; 1586 1587 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL); 1588 if (!intel_dp) 1589 return; 1590 1591 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); 1592 if (!intel_connector) { 1593 kfree(intel_dp); 1594 return; 1595 } 1596 intel_encoder = &intel_dp->base; 1597 1598 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D) 1599 if (intel_dpd_is_edp(dev)) 1600 intel_dp->is_pch_edp = true; 1601 1602 if (output_reg == DP_A || IS_PCH_eDP(intel_dp)) { 1603 type = DRM_MODE_CONNECTOR_eDP; 1604 intel_encoder->type = INTEL_OUTPUT_EDP; 1605 } else { 1606 type = DRM_MODE_CONNECTOR_DisplayPort; 1607 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 1608 } 1609 1610 connector = &intel_connector->base; 1611 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); 1612 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); 1613 1614 connector->polled = DRM_CONNECTOR_POLL_HPD; 1615 1616 if (output_reg == DP_B || output_reg == PCH_DP_B) 1617 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT); 1618 else if (output_reg == DP_C || output_reg == PCH_DP_C) 1619 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT); 1620 else if (output_reg == DP_D || output_reg == PCH_DP_D) 1621 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT); 1622 1623 if (IS_eDP(intel_dp)) 1624 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT); 1625 1626 intel_encoder->crtc_mask = (1 << 0) | (1 << 1); 1627 connector->interlace_allowed = true; 1628 connector->doublescan_allowed = 0; 1629 1630 intel_dp->output_reg = output_reg; 1631 intel_dp->has_audio = false; 1632 intel_dp->dpms_mode = DRM_MODE_DPMS_ON; 1633 1634 drm_encoder_init(dev, &intel_encoder->enc, &intel_dp_enc_funcs, 1635 DRM_MODE_ENCODER_TMDS); 1636 drm_encoder_helper_add(&intel_encoder->enc, &intel_dp_helper_funcs); 1637 1638 drm_mode_connector_attach_encoder(&intel_connector->base, 1639 &intel_encoder->enc); 1640 drm_sysfs_connector_add(connector); 1641 1642 /* Set up the DDC bus. */ 1643 switch (output_reg) { 1644 case DP_A: 1645 name = "DPDDC-A"; 1646 break; 1647 case DP_B: 1648 case PCH_DP_B: 1649 dev_priv->hotplug_supported_mask |= 1650 HDMIB_HOTPLUG_INT_STATUS; 1651 name = "DPDDC-B"; 1652 break; 1653 case DP_C: 1654 case PCH_DP_C: 1655 dev_priv->hotplug_supported_mask |= 1656 HDMIC_HOTPLUG_INT_STATUS; 1657 name = "DPDDC-C"; 1658 break; 1659 case DP_D: 1660 case PCH_DP_D: 1661 dev_priv->hotplug_supported_mask |= 1662 HDMID_HOTPLUG_INT_STATUS; 1663 name = "DPDDC-D"; 1664 break; 1665 } 1666 1667 intel_dp_i2c_init(intel_dp, intel_connector, name); 1668 1669 intel_encoder->ddc_bus = &intel_dp->adapter; 1670 intel_encoder->hot_plug = intel_dp_hot_plug; 1671 1672 if (output_reg == DP_A || IS_PCH_eDP(intel_dp)) { 1673 /* initialize panel mode from VBT if available for eDP */ 1674 if (dev_priv->lfp_lvds_vbt_mode) { 1675 dev_priv->panel_fixed_mode = 1676 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); 1677 if (dev_priv->panel_fixed_mode) { 1678 dev_priv->panel_fixed_mode->type |= 1679 DRM_MODE_TYPE_PREFERRED; 1680 } 1681 } 1682 } 1683 1684 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 1685 * 0xd. Failure to do so will result in spurious interrupts being 1686 * generated on the port when a cable is not attached. 1687 */ 1688 if (IS_G4X(dev) && !IS_GM45(dev)) { 1689 u32 temp = I915_READ(PEG_BAND_GAP_DATA); 1690 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); 1691 } 1692} 1693