1/* Intel i7 core/Nehalem Memory Controller kernel module 2 * 3 * This driver supports yhe memory controllers found on the Intel 4 * processor families i7core, i7core 7xx/8xx, i5core, Xeon 35xx, 5 * Xeon 55xx and Xeon 56xx also known as Nehalem, Nehalem-EP, Lynnfield 6 * and Westmere-EP. 7 * 8 * This file may be distributed under the terms of the 9 * GNU General Public License version 2 only. 10 * 11 * Copyright (c) 2009-2010 by: 12 * Mauro Carvalho Chehab <mchehab@redhat.com> 13 * 14 * Red Hat Inc. http://www.redhat.com 15 * 16 * Forked and adapted from the i5400_edac driver 17 * 18 * Based on the following public Intel datasheets: 19 * Intel Core i7 Processor Extreme Edition and Intel Core i7 Processor 20 * Datasheet, Volume 2: 21 * http://download.intel.com/design/processor/datashts/320835.pdf 22 * Intel Xeon Processor 5500 Series Datasheet Volume 2 23 * http://www.intel.com/Assets/PDF/datasheet/321322.pdf 24 * also available at: 25 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf 26 */ 27 28#include <linux/module.h> 29#include <linux/init.h> 30#include <linux/pci.h> 31#include <linux/pci_ids.h> 32#include <linux/slab.h> 33#include <linux/delay.h> 34#include <linux/edac.h> 35#include <linux/mmzone.h> 36#include <linux/edac_mce.h> 37#include <linux/smp.h> 38#include <asm/processor.h> 39 40#include "edac_core.h" 41 42/* 43 * This is used for Nehalem-EP and Nehalem-EX devices, where the non-core 44 * registers start at bus 255, and are not reported by BIOS. 45 * We currently find devices with only 2 sockets. In order to support more QPI 46 * Quick Path Interconnect, just increment this number. 47 */ 48#define MAX_SOCKET_BUSES 2 49 50 51/* 52 * Alter this version for the module when modifications are made 53 */ 54#define I7CORE_REVISION " Ver: 1.0.0 " __DATE__ 55#define EDAC_MOD_STR "i7core_edac" 56 57/* 58 * Debug macros 59 */ 60#define i7core_printk(level, fmt, arg...) \ 61 edac_printk(level, "i7core", fmt, ##arg) 62 63#define i7core_mc_printk(mci, level, fmt, arg...) \ 64 edac_mc_chipset_printk(mci, level, "i7core", fmt, ##arg) 65 66/* 67 * i7core Memory Controller Registers 68 */ 69 70 /* OFFSETS for Device 0 Function 0 */ 71 72#define MC_CFG_CONTROL 0x90 73 74 /* OFFSETS for Device 3 Function 0 */ 75 76#define MC_CONTROL 0x48 77#define MC_STATUS 0x4c 78#define MC_MAX_DOD 0x64 79 80/* 81 * OFFSETS for Device 3 Function 4, as inicated on Xeon 5500 datasheet: 82 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf 83 */ 84 85#define MC_TEST_ERR_RCV1 0x60 86 #define DIMM2_COR_ERR(r) ((r) & 0x7fff) 87 88#define MC_TEST_ERR_RCV0 0x64 89 #define DIMM1_COR_ERR(r) (((r) >> 16) & 0x7fff) 90 #define DIMM0_COR_ERR(r) ((r) & 0x7fff) 91 92/* OFFSETS for Device 3 Function 2, as inicated on Xeon 5500 datasheet */ 93#define MC_COR_ECC_CNT_0 0x80 94#define MC_COR_ECC_CNT_1 0x84 95#define MC_COR_ECC_CNT_2 0x88 96#define MC_COR_ECC_CNT_3 0x8c 97#define MC_COR_ECC_CNT_4 0x90 98#define MC_COR_ECC_CNT_5 0x94 99 100#define DIMM_TOP_COR_ERR(r) (((r) >> 16) & 0x7fff) 101#define DIMM_BOT_COR_ERR(r) ((r) & 0x7fff) 102 103 104 /* OFFSETS for Devices 4,5 and 6 Function 0 */ 105 106#define MC_CHANNEL_DIMM_INIT_PARAMS 0x58 107 #define THREE_DIMMS_PRESENT (1 << 24) 108 #define SINGLE_QUAD_RANK_PRESENT (1 << 23) 109 #define QUAD_RANK_PRESENT (1 << 22) 110 #define REGISTERED_DIMM (1 << 15) 111 112#define MC_CHANNEL_MAPPER 0x60 113 #define RDLCH(r, ch) ((((r) >> (3 + (ch * 6))) & 0x07) - 1) 114 #define WRLCH(r, ch) ((((r) >> (ch * 6)) & 0x07) - 1) 115 116#define MC_CHANNEL_RANK_PRESENT 0x7c 117 #define RANK_PRESENT_MASK 0xffff 118 119#define MC_CHANNEL_ADDR_MATCH 0xf0 120#define MC_CHANNEL_ERROR_MASK 0xf8 121#define MC_CHANNEL_ERROR_INJECT 0xfc 122 #define INJECT_ADDR_PARITY 0x10 123 #define INJECT_ECC 0x08 124 #define MASK_CACHELINE 0x06 125 #define MASK_FULL_CACHELINE 0x06 126 #define MASK_MSB32_CACHELINE 0x04 127 #define MASK_LSB32_CACHELINE 0x02 128 #define NO_MASK_CACHELINE 0x00 129 #define REPEAT_EN 0x01 130 131 /* OFFSETS for Devices 4,5 and 6 Function 1 */ 132 133#define MC_DOD_CH_DIMM0 0x48 134#define MC_DOD_CH_DIMM1 0x4c 135#define MC_DOD_CH_DIMM2 0x50 136 #define RANKOFFSET_MASK ((1 << 12) | (1 << 11) | (1 << 10)) 137 #define RANKOFFSET(x) ((x & RANKOFFSET_MASK) >> 10) 138 #define DIMM_PRESENT_MASK (1 << 9) 139 #define DIMM_PRESENT(x) (((x) & DIMM_PRESENT_MASK) >> 9) 140 #define MC_DOD_NUMBANK_MASK ((1 << 8) | (1 << 7)) 141 #define MC_DOD_NUMBANK(x) (((x) & MC_DOD_NUMBANK_MASK) >> 7) 142 #define MC_DOD_NUMRANK_MASK ((1 << 6) | (1 << 5)) 143 #define MC_DOD_NUMRANK(x) (((x) & MC_DOD_NUMRANK_MASK) >> 5) 144 #define MC_DOD_NUMROW_MASK ((1 << 4) | (1 << 3) | (1 << 2)) 145 #define MC_DOD_NUMROW(x) (((x) & MC_DOD_NUMROW_MASK) >> 2) 146 #define MC_DOD_NUMCOL_MASK 3 147 #define MC_DOD_NUMCOL(x) ((x) & MC_DOD_NUMCOL_MASK) 148 149#define MC_RANK_PRESENT 0x7c 150 151#define MC_SAG_CH_0 0x80 152#define MC_SAG_CH_1 0x84 153#define MC_SAG_CH_2 0x88 154#define MC_SAG_CH_3 0x8c 155#define MC_SAG_CH_4 0x90 156#define MC_SAG_CH_5 0x94 157#define MC_SAG_CH_6 0x98 158#define MC_SAG_CH_7 0x9c 159 160#define MC_RIR_LIMIT_CH_0 0x40 161#define MC_RIR_LIMIT_CH_1 0x44 162#define MC_RIR_LIMIT_CH_2 0x48 163#define MC_RIR_LIMIT_CH_3 0x4C 164#define MC_RIR_LIMIT_CH_4 0x50 165#define MC_RIR_LIMIT_CH_5 0x54 166#define MC_RIR_LIMIT_CH_6 0x58 167#define MC_RIR_LIMIT_CH_7 0x5C 168#define MC_RIR_LIMIT_MASK ((1 << 10) - 1) 169 170#define MC_RIR_WAY_CH 0x80 171 #define MC_RIR_WAY_OFFSET_MASK (((1 << 14) - 1) & ~0x7) 172 #define MC_RIR_WAY_RANK_MASK 0x7 173 174/* 175 * i7core structs 176 */ 177 178#define NUM_CHANS 3 179#define MAX_DIMMS 3 /* Max DIMMS per channel */ 180#define MAX_MCR_FUNC 4 181#define MAX_CHAN_FUNC 3 182 183struct i7core_info { 184 u32 mc_control; 185 u32 mc_status; 186 u32 max_dod; 187 u32 ch_map; 188}; 189 190 191struct i7core_inject { 192 int enable; 193 194 u32 section; 195 u32 type; 196 u32 eccmask; 197 198 /* Error address mask */ 199 int channel, dimm, rank, bank, page, col; 200}; 201 202struct i7core_channel { 203 u32 ranks; 204 u32 dimms; 205}; 206 207struct pci_id_descr { 208 int dev; 209 int func; 210 int dev_id; 211 int optional; 212}; 213 214struct pci_id_table { 215 struct pci_id_descr *descr; 216 int n_devs; 217}; 218 219struct i7core_dev { 220 struct list_head list; 221 u8 socket; 222 struct pci_dev **pdev; 223 int n_devs; 224 struct mem_ctl_info *mci; 225}; 226 227struct i7core_pvt { 228 struct pci_dev *pci_noncore; 229 struct pci_dev *pci_mcr[MAX_MCR_FUNC + 1]; 230 struct pci_dev *pci_ch[NUM_CHANS][MAX_CHAN_FUNC + 1]; 231 232 struct i7core_dev *i7core_dev; 233 234 struct i7core_info info; 235 struct i7core_inject inject; 236 struct i7core_channel channel[NUM_CHANS]; 237 238 int channels; /* Number of active channels */ 239 240 int ce_count_available; 241 int csrow_map[NUM_CHANS][MAX_DIMMS]; 242 243 /* ECC corrected errors counts per udimm */ 244 unsigned long udimm_ce_count[MAX_DIMMS]; 245 int udimm_last_ce_count[MAX_DIMMS]; 246 /* ECC corrected errors counts per rdimm */ 247 unsigned long rdimm_ce_count[NUM_CHANS][MAX_DIMMS]; 248 int rdimm_last_ce_count[NUM_CHANS][MAX_DIMMS]; 249 250 unsigned int is_registered; 251 252 /* mcelog glue */ 253 struct edac_mce edac_mce; 254 255 /* Fifo double buffers */ 256 struct mce mce_entry[MCE_LOG_LEN]; 257 struct mce mce_outentry[MCE_LOG_LEN]; 258 259 /* Fifo in/out counters */ 260 unsigned mce_in, mce_out; 261 262 /* Count indicator to show errors not got */ 263 unsigned mce_overrun; 264}; 265 266/* Static vars */ 267static LIST_HEAD(i7core_edac_list); 268static DEFINE_MUTEX(i7core_edac_lock); 269 270#define PCI_DESCR(device, function, device_id) \ 271 .dev = (device), \ 272 .func = (function), \ 273 .dev_id = (device_id) 274 275struct pci_id_descr pci_dev_descr_i7core_nehalem[] = { 276 /* Memory controller */ 277 { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_I7_MCR) }, 278 { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_I7_MC_TAD) }, 279 /* Exists only for RDIMM */ 280 { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_I7_MC_RAS), .optional = 1 }, 281 { PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_I7_MC_TEST) }, 282 283 /* Channel 0 */ 284 { PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH0_CTRL) }, 285 { PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH0_ADDR) }, 286 { PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH0_RANK) }, 287 { PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH0_TC) }, 288 289 /* Channel 1 */ 290 { PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH1_CTRL) }, 291 { PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH1_ADDR) }, 292 { PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH1_RANK) }, 293 { PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH1_TC) }, 294 295 /* Channel 2 */ 296 { PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH2_CTRL) }, 297 { PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH2_ADDR) }, 298 { PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH2_RANK) }, 299 { PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH2_TC) }, 300 301 /* Generic Non-core registers */ 302 /* 303 * This is the PCI device on i7core and on Xeon 35xx (8086:2c41) 304 * On Xeon 55xx, however, it has a different id (8086:2c40). So, 305 * the probing code needs to test for the other address in case of 306 * failure of this one 307 */ 308 { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_I7_NONCORE) }, 309 310}; 311 312struct pci_id_descr pci_dev_descr_lynnfield[] = { 313 { PCI_DESCR( 3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR) }, 314 { PCI_DESCR( 3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD) }, 315 { PCI_DESCR( 3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST) }, 316 317 { PCI_DESCR( 4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL) }, 318 { PCI_DESCR( 4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR) }, 319 { PCI_DESCR( 4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK) }, 320 { PCI_DESCR( 4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC) }, 321 322 { PCI_DESCR( 5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL) }, 323 { PCI_DESCR( 5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR) }, 324 { PCI_DESCR( 5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK) }, 325 { PCI_DESCR( 5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC) }, 326 327 /* 328 * This is the PCI device has an alternate address on some 329 * processors like Core i7 860 330 */ 331 { PCI_DESCR( 0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE) }, 332}; 333 334struct pci_id_descr pci_dev_descr_i7core_westmere[] = { 335 /* Memory controller */ 336 { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR_REV2) }, 337 { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD_REV2) }, 338 /* Exists only for RDIMM */ 339 { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_RAS_REV2), .optional = 1 }, 340 { PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST_REV2) }, 341 342 /* Channel 0 */ 343 { PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL_REV2) }, 344 { PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR_REV2) }, 345 { PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK_REV2) }, 346 { PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC_REV2) }, 347 348 /* Channel 1 */ 349 { PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL_REV2) }, 350 { PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR_REV2) }, 351 { PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK_REV2) }, 352 { PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC_REV2) }, 353 354 /* Channel 2 */ 355 { PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_CTRL_REV2) }, 356 { PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_ADDR_REV2) }, 357 { PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_RANK_REV2) }, 358 { PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_TC_REV2) }, 359 360 /* Generic Non-core registers */ 361 { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_REV2) }, 362 363}; 364 365#define PCI_ID_TABLE_ENTRY(A) { A, ARRAY_SIZE(A) } 366struct pci_id_table pci_dev_table[] = { 367 PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_nehalem), 368 PCI_ID_TABLE_ENTRY(pci_dev_descr_lynnfield), 369 PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_westmere), 370}; 371 372/* 373 * pci_device_id table for which devices we are looking for 374 */ 375static const struct pci_device_id i7core_pci_tbl[] __devinitdata = { 376 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58_HUB_MGMT)}, 377 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNNFIELD_QPI_LINK0)}, 378 {0,} /* 0 terminated list. */ 379}; 380 381static struct edac_pci_ctl_info *i7core_pci; 382 383/**************************************************************************** 384 Anciliary status routines 385 ****************************************************************************/ 386 387 /* MC_CONTROL bits */ 388#define CH_ACTIVE(pvt, ch) ((pvt)->info.mc_control & (1 << (8 + ch))) 389#define ECCx8(pvt) ((pvt)->info.mc_control & (1 << 1)) 390 391 /* MC_STATUS bits */ 392#define ECC_ENABLED(pvt) ((pvt)->info.mc_status & (1 << 4)) 393#define CH_DISABLED(pvt, ch) ((pvt)->info.mc_status & (1 << ch)) 394 395 /* MC_MAX_DOD read functions */ 396static inline int numdimms(u32 dimms) 397{ 398 return (dimms & 0x3) + 1; 399} 400 401static inline int numrank(u32 rank) 402{ 403 static int ranks[4] = { 1, 2, 4, -EINVAL }; 404 405 return ranks[rank & 0x3]; 406} 407 408static inline int numbank(u32 bank) 409{ 410 static int banks[4] = { 4, 8, 16, -EINVAL }; 411 412 return banks[bank & 0x3]; 413} 414 415static inline int numrow(u32 row) 416{ 417 static int rows[8] = { 418 1 << 12, 1 << 13, 1 << 14, 1 << 15, 419 1 << 16, -EINVAL, -EINVAL, -EINVAL, 420 }; 421 422 return rows[row & 0x7]; 423} 424 425static inline int numcol(u32 col) 426{ 427 static int cols[8] = { 428 1 << 10, 1 << 11, 1 << 12, -EINVAL, 429 }; 430 return cols[col & 0x3]; 431} 432 433static struct i7core_dev *get_i7core_dev(u8 socket) 434{ 435 struct i7core_dev *i7core_dev; 436 437 list_for_each_entry(i7core_dev, &i7core_edac_list, list) { 438 if (i7core_dev->socket == socket) 439 return i7core_dev; 440 } 441 442 return NULL; 443} 444 445/**************************************************************************** 446 Memory check routines 447 ****************************************************************************/ 448static struct pci_dev *get_pdev_slot_func(u8 socket, unsigned slot, 449 unsigned func) 450{ 451 struct i7core_dev *i7core_dev = get_i7core_dev(socket); 452 int i; 453 454 if (!i7core_dev) 455 return NULL; 456 457 for (i = 0; i < i7core_dev->n_devs; i++) { 458 if (!i7core_dev->pdev[i]) 459 continue; 460 461 if (PCI_SLOT(i7core_dev->pdev[i]->devfn) == slot && 462 PCI_FUNC(i7core_dev->pdev[i]->devfn) == func) { 463 return i7core_dev->pdev[i]; 464 } 465 } 466 467 return NULL; 468} 469 470/** 471 * i7core_get_active_channels() - gets the number of channels and csrows 472 * @socket: Quick Path Interconnect socket 473 * @channels: Number of channels that will be returned 474 * @csrows: Number of csrows found 475 * 476 * Since EDAC core needs to know in advance the number of available channels 477 * and csrows, in order to allocate memory for csrows/channels, it is needed 478 * to run two similar steps. At the first step, implemented on this function, 479 * it checks the number of csrows/channels present at one socket. 480 * this is used in order to properly allocate the size of mci components. 481 * 482 * It should be noticed that none of the current available datasheets explain 483 * or even mention how csrows are seen by the memory controller. So, we need 484 * to add a fake description for csrows. 485 * So, this driver is attributing one DIMM memory for one csrow. 486 */ 487static int i7core_get_active_channels(u8 socket, unsigned *channels, 488 unsigned *csrows) 489{ 490 struct pci_dev *pdev = NULL; 491 int i, j; 492 u32 status, control; 493 494 *channels = 0; 495 *csrows = 0; 496 497 pdev = get_pdev_slot_func(socket, 3, 0); 498 if (!pdev) { 499 i7core_printk(KERN_ERR, "Couldn't find socket %d fn 3.0!!!\n", 500 socket); 501 return -ENODEV; 502 } 503 504 /* Device 3 function 0 reads */ 505 pci_read_config_dword(pdev, MC_STATUS, &status); 506 pci_read_config_dword(pdev, MC_CONTROL, &control); 507 508 for (i = 0; i < NUM_CHANS; i++) { 509 u32 dimm_dod[3]; 510 /* Check if the channel is active */ 511 if (!(control & (1 << (8 + i)))) 512 continue; 513 514 /* Check if the channel is disabled */ 515 if (status & (1 << i)) 516 continue; 517 518 pdev = get_pdev_slot_func(socket, i + 4, 1); 519 if (!pdev) { 520 i7core_printk(KERN_ERR, "Couldn't find socket %d " 521 "fn %d.%d!!!\n", 522 socket, i + 4, 1); 523 return -ENODEV; 524 } 525 /* Devices 4-6 function 1 */ 526 pci_read_config_dword(pdev, 527 MC_DOD_CH_DIMM0, &dimm_dod[0]); 528 pci_read_config_dword(pdev, 529 MC_DOD_CH_DIMM1, &dimm_dod[1]); 530 pci_read_config_dword(pdev, 531 MC_DOD_CH_DIMM2, &dimm_dod[2]); 532 533 (*channels)++; 534 535 for (j = 0; j < 3; j++) { 536 if (!DIMM_PRESENT(dimm_dod[j])) 537 continue; 538 (*csrows)++; 539 } 540 } 541 542 debugf0("Number of active channels on socket %d: %d\n", 543 socket, *channels); 544 545 return 0; 546} 547 548static int get_dimm_config(struct mem_ctl_info *mci, int *csrow) 549{ 550 struct i7core_pvt *pvt = mci->pvt_info; 551 struct csrow_info *csr; 552 struct pci_dev *pdev; 553 int i, j; 554 unsigned long last_page = 0; 555 enum edac_type mode; 556 enum mem_type mtype; 557 558 /* Get data from the MC register, function 0 */ 559 pdev = pvt->pci_mcr[0]; 560 if (!pdev) 561 return -ENODEV; 562 563 /* Device 3 function 0 reads */ 564 pci_read_config_dword(pdev, MC_CONTROL, &pvt->info.mc_control); 565 pci_read_config_dword(pdev, MC_STATUS, &pvt->info.mc_status); 566 pci_read_config_dword(pdev, MC_MAX_DOD, &pvt->info.max_dod); 567 pci_read_config_dword(pdev, MC_CHANNEL_MAPPER, &pvt->info.ch_map); 568 569 debugf0("QPI %d control=0x%08x status=0x%08x dod=0x%08x map=0x%08x\n", 570 pvt->i7core_dev->socket, pvt->info.mc_control, pvt->info.mc_status, 571 pvt->info.max_dod, pvt->info.ch_map); 572 573 if (ECC_ENABLED(pvt)) { 574 debugf0("ECC enabled with x%d SDCC\n", ECCx8(pvt) ? 8 : 4); 575 if (ECCx8(pvt)) 576 mode = EDAC_S8ECD8ED; 577 else 578 mode = EDAC_S4ECD4ED; 579 } else { 580 debugf0("ECC disabled\n"); 581 mode = EDAC_NONE; 582 } 583 584 debugf0("DOD Max limits: DIMMS: %d, %d-ranked, %d-banked " 585 "x%x x 0x%x\n", 586 numdimms(pvt->info.max_dod), 587 numrank(pvt->info.max_dod >> 2), 588 numbank(pvt->info.max_dod >> 4), 589 numrow(pvt->info.max_dod >> 6), 590 numcol(pvt->info.max_dod >> 9)); 591 592 for (i = 0; i < NUM_CHANS; i++) { 593 u32 data, dimm_dod[3], value[8]; 594 595 if (!pvt->pci_ch[i][0]) 596 continue; 597 598 if (!CH_ACTIVE(pvt, i)) { 599 debugf0("Channel %i is not active\n", i); 600 continue; 601 } 602 if (CH_DISABLED(pvt, i)) { 603 debugf0("Channel %i is disabled\n", i); 604 continue; 605 } 606 607 /* Devices 4-6 function 0 */ 608 pci_read_config_dword(pvt->pci_ch[i][0], 609 MC_CHANNEL_DIMM_INIT_PARAMS, &data); 610 611 pvt->channel[i].ranks = (data & QUAD_RANK_PRESENT) ? 612 4 : 2; 613 614 if (data & REGISTERED_DIMM) 615 mtype = MEM_RDDR3; 616 else 617 mtype = MEM_DDR3; 618 619 /* Devices 4-6 function 1 */ 620 pci_read_config_dword(pvt->pci_ch[i][1], 621 MC_DOD_CH_DIMM0, &dimm_dod[0]); 622 pci_read_config_dword(pvt->pci_ch[i][1], 623 MC_DOD_CH_DIMM1, &dimm_dod[1]); 624 pci_read_config_dword(pvt->pci_ch[i][1], 625 MC_DOD_CH_DIMM2, &dimm_dod[2]); 626 627 debugf0("Ch%d phy rd%d, wr%d (0x%08x): " 628 "%d ranks, %cDIMMs\n", 629 i, 630 RDLCH(pvt->info.ch_map, i), WRLCH(pvt->info.ch_map, i), 631 data, 632 pvt->channel[i].ranks, 633 (data & REGISTERED_DIMM) ? 'R' : 'U'); 634 635 for (j = 0; j < 3; j++) { 636 u32 banks, ranks, rows, cols; 637 u32 size, npages; 638 639 if (!DIMM_PRESENT(dimm_dod[j])) 640 continue; 641 642 banks = numbank(MC_DOD_NUMBANK(dimm_dod[j])); 643 ranks = numrank(MC_DOD_NUMRANK(dimm_dod[j])); 644 rows = numrow(MC_DOD_NUMROW(dimm_dod[j])); 645 cols = numcol(MC_DOD_NUMCOL(dimm_dod[j])); 646 647 /* DDR3 has 8 I/O banks */ 648 size = (rows * cols * banks * ranks) >> (20 - 3); 649 650 pvt->channel[i].dimms++; 651 652 debugf0("\tdimm %d %d Mb offset: %x, " 653 "bank: %d, rank: %d, row: %#x, col: %#x\n", 654 j, size, 655 RANKOFFSET(dimm_dod[j]), 656 banks, ranks, rows, cols); 657 658#if PAGE_SHIFT > 20 659 npages = size >> (PAGE_SHIFT - 20); 660#else 661 npages = size << (20 - PAGE_SHIFT); 662#endif 663 664 csr = &mci->csrows[*csrow]; 665 csr->first_page = last_page + 1; 666 last_page += npages; 667 csr->last_page = last_page; 668 csr->nr_pages = npages; 669 670 csr->page_mask = 0; 671 csr->grain = 8; 672 csr->csrow_idx = *csrow; 673 csr->nr_channels = 1; 674 675 csr->channels[0].chan_idx = i; 676 csr->channels[0].ce_count = 0; 677 678 pvt->csrow_map[i][j] = *csrow; 679 680 switch (banks) { 681 case 4: 682 csr->dtype = DEV_X4; 683 break; 684 case 8: 685 csr->dtype = DEV_X8; 686 break; 687 case 16: 688 csr->dtype = DEV_X16; 689 break; 690 default: 691 csr->dtype = DEV_UNKNOWN; 692 } 693 694 csr->edac_mode = mode; 695 csr->mtype = mtype; 696 697 (*csrow)++; 698 } 699 700 pci_read_config_dword(pdev, MC_SAG_CH_0, &value[0]); 701 pci_read_config_dword(pdev, MC_SAG_CH_1, &value[1]); 702 pci_read_config_dword(pdev, MC_SAG_CH_2, &value[2]); 703 pci_read_config_dword(pdev, MC_SAG_CH_3, &value[3]); 704 pci_read_config_dword(pdev, MC_SAG_CH_4, &value[4]); 705 pci_read_config_dword(pdev, MC_SAG_CH_5, &value[5]); 706 pci_read_config_dword(pdev, MC_SAG_CH_6, &value[6]); 707 pci_read_config_dword(pdev, MC_SAG_CH_7, &value[7]); 708 debugf1("\t[%i] DIVBY3\tREMOVED\tOFFSET\n", i); 709 for (j = 0; j < 8; j++) 710 debugf1("\t\t%#x\t%#x\t%#x\n", 711 (value[j] >> 27) & 0x1, 712 (value[j] >> 24) & 0x7, 713 (value[j] && ((1 << 24) - 1))); 714 } 715 716 return 0; 717} 718 719/**************************************************************************** 720 Error insertion routines 721 ****************************************************************************/ 722 723/* The i7core has independent error injection features per channel. 724 However, to have a simpler code, we don't allow enabling error injection 725 on more than one channel. 726 Also, since a change at an inject parameter will be applied only at enable, 727 we're disabling error injection on all write calls to the sysfs nodes that 728 controls the error code injection. 729 */ 730static int disable_inject(struct mem_ctl_info *mci) 731{ 732 struct i7core_pvt *pvt = mci->pvt_info; 733 734 pvt->inject.enable = 0; 735 736 if (!pvt->pci_ch[pvt->inject.channel][0]) 737 return -ENODEV; 738 739 pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0], 740 MC_CHANNEL_ERROR_INJECT, 0); 741 742 return 0; 743} 744 745/* 746 * i7core inject inject.section 747 * 748 * accept and store error injection inject.section value 749 * bit 0 - refers to the lower 32-byte half cacheline 750 * bit 1 - refers to the upper 32-byte half cacheline 751 */ 752static ssize_t i7core_inject_section_store(struct mem_ctl_info *mci, 753 const char *data, size_t count) 754{ 755 struct i7core_pvt *pvt = mci->pvt_info; 756 unsigned long value; 757 int rc; 758 759 if (pvt->inject.enable) 760 disable_inject(mci); 761 762 rc = strict_strtoul(data, 10, &value); 763 if ((rc < 0) || (value > 3)) 764 return -EIO; 765 766 pvt->inject.section = (u32) value; 767 return count; 768} 769 770static ssize_t i7core_inject_section_show(struct mem_ctl_info *mci, 771 char *data) 772{ 773 struct i7core_pvt *pvt = mci->pvt_info; 774 return sprintf(data, "0x%08x\n", pvt->inject.section); 775} 776 777/* 778 * i7core inject.type 779 * 780 * accept and store error injection inject.section value 781 * bit 0 - repeat enable - Enable error repetition 782 * bit 1 - inject ECC error 783 * bit 2 - inject parity error 784 */ 785static ssize_t i7core_inject_type_store(struct mem_ctl_info *mci, 786 const char *data, size_t count) 787{ 788 struct i7core_pvt *pvt = mci->pvt_info; 789 unsigned long value; 790 int rc; 791 792 if (pvt->inject.enable) 793 disable_inject(mci); 794 795 rc = strict_strtoul(data, 10, &value); 796 if ((rc < 0) || (value > 7)) 797 return -EIO; 798 799 pvt->inject.type = (u32) value; 800 return count; 801} 802 803static ssize_t i7core_inject_type_show(struct mem_ctl_info *mci, 804 char *data) 805{ 806 struct i7core_pvt *pvt = mci->pvt_info; 807 return sprintf(data, "0x%08x\n", pvt->inject.type); 808} 809 810/* 811 * i7core_inject_inject.eccmask_store 812 * 813 * The type of error (UE/CE) will depend on the inject.eccmask value: 814 * Any bits set to a 1 will flip the corresponding ECC bit 815 * Correctable errors can be injected by flipping 1 bit or the bits within 816 * a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or 817 * 23:16 and 31:24). Flipping bits in two symbol pairs will cause an 818 * uncorrectable error to be injected. 819 */ 820static ssize_t i7core_inject_eccmask_store(struct mem_ctl_info *mci, 821 const char *data, size_t count) 822{ 823 struct i7core_pvt *pvt = mci->pvt_info; 824 unsigned long value; 825 int rc; 826 827 if (pvt->inject.enable) 828 disable_inject(mci); 829 830 rc = strict_strtoul(data, 10, &value); 831 if (rc < 0) 832 return -EIO; 833 834 pvt->inject.eccmask = (u32) value; 835 return count; 836} 837 838static ssize_t i7core_inject_eccmask_show(struct mem_ctl_info *mci, 839 char *data) 840{ 841 struct i7core_pvt *pvt = mci->pvt_info; 842 return sprintf(data, "0x%08x\n", pvt->inject.eccmask); 843} 844 845/* 846 * i7core_addrmatch 847 * 848 * The type of error (UE/CE) will depend on the inject.eccmask value: 849 * Any bits set to a 1 will flip the corresponding ECC bit 850 * Correctable errors can be injected by flipping 1 bit or the bits within 851 * a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or 852 * 23:16 and 31:24). Flipping bits in two symbol pairs will cause an 853 * uncorrectable error to be injected. 854 */ 855 856#define DECLARE_ADDR_MATCH(param, limit) \ 857static ssize_t i7core_inject_store_##param( \ 858 struct mem_ctl_info *mci, \ 859 const char *data, size_t count) \ 860{ \ 861 struct i7core_pvt *pvt; \ 862 long value; \ 863 int rc; \ 864 \ 865 debugf1("%s()\n", __func__); \ 866 pvt = mci->pvt_info; \ 867 \ 868 if (pvt->inject.enable) \ 869 disable_inject(mci); \ 870 \ 871 if (!strcasecmp(data, "any") || !strcasecmp(data, "any\n"))\ 872 value = -1; \ 873 else { \ 874 rc = strict_strtoul(data, 10, &value); \ 875 if ((rc < 0) || (value >= limit)) \ 876 return -EIO; \ 877 } \ 878 \ 879 pvt->inject.param = value; \ 880 \ 881 return count; \ 882} \ 883 \ 884static ssize_t i7core_inject_show_##param( \ 885 struct mem_ctl_info *mci, \ 886 char *data) \ 887{ \ 888 struct i7core_pvt *pvt; \ 889 \ 890 pvt = mci->pvt_info; \ 891 debugf1("%s() pvt=%p\n", __func__, pvt); \ 892 if (pvt->inject.param < 0) \ 893 return sprintf(data, "any\n"); \ 894 else \ 895 return sprintf(data, "%d\n", pvt->inject.param);\ 896} 897 898#define ATTR_ADDR_MATCH(param) \ 899 { \ 900 .attr = { \ 901 .name = #param, \ 902 .mode = (S_IRUGO | S_IWUSR) \ 903 }, \ 904 .show = i7core_inject_show_##param, \ 905 .store = i7core_inject_store_##param, \ 906 } 907 908DECLARE_ADDR_MATCH(channel, 3); 909DECLARE_ADDR_MATCH(dimm, 3); 910DECLARE_ADDR_MATCH(rank, 4); 911DECLARE_ADDR_MATCH(bank, 32); 912DECLARE_ADDR_MATCH(page, 0x10000); 913DECLARE_ADDR_MATCH(col, 0x4000); 914 915static int write_and_test(struct pci_dev *dev, int where, u32 val) 916{ 917 u32 read; 918 int count; 919 920 debugf0("setting pci %02x:%02x.%x reg=%02x value=%08x\n", 921 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), 922 where, val); 923 924 for (count = 0; count < 10; count++) { 925 if (count) 926 msleep(100); 927 pci_write_config_dword(dev, where, val); 928 pci_read_config_dword(dev, where, &read); 929 930 if (read == val) 931 return 0; 932 } 933 934 i7core_printk(KERN_ERR, "Error during set pci %02x:%02x.%x reg=%02x " 935 "write=%08x. Read=%08x\n", 936 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), 937 where, val, read); 938 939 return -EINVAL; 940} 941 942static ssize_t i7core_inject_enable_store(struct mem_ctl_info *mci, 943 const char *data, size_t count) 944{ 945 struct i7core_pvt *pvt = mci->pvt_info; 946 u32 injectmask; 947 u64 mask = 0; 948 int rc; 949 long enable; 950 951 if (!pvt->pci_ch[pvt->inject.channel][0]) 952 return 0; 953 954 rc = strict_strtoul(data, 10, &enable); 955 if ((rc < 0)) 956 return 0; 957 958 if (enable) { 959 pvt->inject.enable = 1; 960 } else { 961 disable_inject(mci); 962 return count; 963 } 964 965 /* Sets pvt->inject.dimm mask */ 966 if (pvt->inject.dimm < 0) 967 mask |= 1LL << 41; 968 else { 969 if (pvt->channel[pvt->inject.channel].dimms > 2) 970 mask |= (pvt->inject.dimm & 0x3LL) << 35; 971 else 972 mask |= (pvt->inject.dimm & 0x1LL) << 36; 973 } 974 975 /* Sets pvt->inject.rank mask */ 976 if (pvt->inject.rank < 0) 977 mask |= 1LL << 40; 978 else { 979 if (pvt->channel[pvt->inject.channel].dimms > 2) 980 mask |= (pvt->inject.rank & 0x1LL) << 34; 981 else 982 mask |= (pvt->inject.rank & 0x3LL) << 34; 983 } 984 985 /* Sets pvt->inject.bank mask */ 986 if (pvt->inject.bank < 0) 987 mask |= 1LL << 39; 988 else 989 mask |= (pvt->inject.bank & 0x15LL) << 30; 990 991 /* Sets pvt->inject.page mask */ 992 if (pvt->inject.page < 0) 993 mask |= 1LL << 38; 994 else 995 mask |= (pvt->inject.page & 0xffff) << 14; 996 997 /* Sets pvt->inject.column mask */ 998 if (pvt->inject.col < 0) 999 mask |= 1LL << 37; 1000 else 1001 mask |= (pvt->inject.col & 0x3fff); 1002 1003 /* 1004 * bit 0: REPEAT_EN 1005 * bits 1-2: MASK_HALF_CACHELINE 1006 * bit 3: INJECT_ECC 1007 * bit 4: INJECT_ADDR_PARITY 1008 */ 1009 1010 injectmask = (pvt->inject.type & 1) | 1011 (pvt->inject.section & 0x3) << 1 | 1012 (pvt->inject.type & 0x6) << (3 - 1); 1013 1014 /* Unlock writes to registers - this register is write only */ 1015 pci_write_config_dword(pvt->pci_noncore, 1016 MC_CFG_CONTROL, 0x2); 1017 1018 write_and_test(pvt->pci_ch[pvt->inject.channel][0], 1019 MC_CHANNEL_ADDR_MATCH, mask); 1020 write_and_test(pvt->pci_ch[pvt->inject.channel][0], 1021 MC_CHANNEL_ADDR_MATCH + 4, mask >> 32L); 1022 1023 write_and_test(pvt->pci_ch[pvt->inject.channel][0], 1024 MC_CHANNEL_ERROR_MASK, pvt->inject.eccmask); 1025 1026 write_and_test(pvt->pci_ch[pvt->inject.channel][0], 1027 MC_CHANNEL_ERROR_INJECT, injectmask); 1028 1029 /* 1030 * This is something undocumented, based on my tests 1031 * Without writing 8 to this register, errors aren't injected. Not sure 1032 * why. 1033 */ 1034 pci_write_config_dword(pvt->pci_noncore, 1035 MC_CFG_CONTROL, 8); 1036 1037 debugf0("Error inject addr match 0x%016llx, ecc 0x%08x," 1038 " inject 0x%08x\n", 1039 mask, pvt->inject.eccmask, injectmask); 1040 1041 1042 return count; 1043} 1044 1045static ssize_t i7core_inject_enable_show(struct mem_ctl_info *mci, 1046 char *data) 1047{ 1048 struct i7core_pvt *pvt = mci->pvt_info; 1049 u32 injectmask; 1050 1051 if (!pvt->pci_ch[pvt->inject.channel][0]) 1052 return 0; 1053 1054 pci_read_config_dword(pvt->pci_ch[pvt->inject.channel][0], 1055 MC_CHANNEL_ERROR_INJECT, &injectmask); 1056 1057 debugf0("Inject error read: 0x%018x\n", injectmask); 1058 1059 if (injectmask & 0x0c) 1060 pvt->inject.enable = 1; 1061 1062 return sprintf(data, "%d\n", pvt->inject.enable); 1063} 1064 1065#define DECLARE_COUNTER(param) \ 1066static ssize_t i7core_show_counter_##param( \ 1067 struct mem_ctl_info *mci, \ 1068 char *data) \ 1069{ \ 1070 struct i7core_pvt *pvt = mci->pvt_info; \ 1071 \ 1072 debugf1("%s() \n", __func__); \ 1073 if (!pvt->ce_count_available || (pvt->is_registered)) \ 1074 return sprintf(data, "data unavailable\n"); \ 1075 return sprintf(data, "%lu\n", \ 1076 pvt->udimm_ce_count[param]); \ 1077} 1078 1079#define ATTR_COUNTER(param) \ 1080 { \ 1081 .attr = { \ 1082 .name = __stringify(udimm##param), \ 1083 .mode = (S_IRUGO | S_IWUSR) \ 1084 }, \ 1085 .show = i7core_show_counter_##param \ 1086 } 1087 1088DECLARE_COUNTER(0); 1089DECLARE_COUNTER(1); 1090DECLARE_COUNTER(2); 1091 1092/* 1093 * Sysfs struct 1094 */ 1095 1096 1097static struct mcidev_sysfs_attribute i7core_addrmatch_attrs[] = { 1098 ATTR_ADDR_MATCH(channel), 1099 ATTR_ADDR_MATCH(dimm), 1100 ATTR_ADDR_MATCH(rank), 1101 ATTR_ADDR_MATCH(bank), 1102 ATTR_ADDR_MATCH(page), 1103 ATTR_ADDR_MATCH(col), 1104 { .attr = { .name = NULL } } 1105}; 1106 1107static struct mcidev_sysfs_group i7core_inject_addrmatch = { 1108 .name = "inject_addrmatch", 1109 .mcidev_attr = i7core_addrmatch_attrs, 1110}; 1111 1112static struct mcidev_sysfs_attribute i7core_udimm_counters_attrs[] = { 1113 ATTR_COUNTER(0), 1114 ATTR_COUNTER(1), 1115 ATTR_COUNTER(2), 1116 { .attr = { .name = NULL } } 1117}; 1118 1119static struct mcidev_sysfs_group i7core_udimm_counters = { 1120 .name = "all_channel_counts", 1121 .mcidev_attr = i7core_udimm_counters_attrs, 1122}; 1123 1124static struct mcidev_sysfs_attribute i7core_sysfs_attrs[] = { 1125 { 1126 .attr = { 1127 .name = "inject_section", 1128 .mode = (S_IRUGO | S_IWUSR) 1129 }, 1130 .show = i7core_inject_section_show, 1131 .store = i7core_inject_section_store, 1132 }, { 1133 .attr = { 1134 .name = "inject_type", 1135 .mode = (S_IRUGO | S_IWUSR) 1136 }, 1137 .show = i7core_inject_type_show, 1138 .store = i7core_inject_type_store, 1139 }, { 1140 .attr = { 1141 .name = "inject_eccmask", 1142 .mode = (S_IRUGO | S_IWUSR) 1143 }, 1144 .show = i7core_inject_eccmask_show, 1145 .store = i7core_inject_eccmask_store, 1146 }, { 1147 .grp = &i7core_inject_addrmatch, 1148 }, { 1149 .attr = { 1150 .name = "inject_enable", 1151 .mode = (S_IRUGO | S_IWUSR) 1152 }, 1153 .show = i7core_inject_enable_show, 1154 .store = i7core_inject_enable_store, 1155 }, 1156 { .attr = { .name = NULL } }, /* Reserved for udimm counters */ 1157 { .attr = { .name = NULL } } 1158}; 1159 1160/**************************************************************************** 1161 Device initialization routines: put/get, init/exit 1162 ****************************************************************************/ 1163 1164/* 1165 * i7core_put_devices 'put' all the devices that we have 1166 * reserved via 'get' 1167 */ 1168static void i7core_put_devices(struct i7core_dev *i7core_dev) 1169{ 1170 int i; 1171 1172 debugf0(__FILE__ ": %s()\n", __func__); 1173 for (i = 0; i < i7core_dev->n_devs; i++) { 1174 struct pci_dev *pdev = i7core_dev->pdev[i]; 1175 if (!pdev) 1176 continue; 1177 debugf0("Removing dev %02x:%02x.%d\n", 1178 pdev->bus->number, 1179 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); 1180 pci_dev_put(pdev); 1181 } 1182 kfree(i7core_dev->pdev); 1183 list_del(&i7core_dev->list); 1184 kfree(i7core_dev); 1185} 1186 1187static void i7core_put_all_devices(void) 1188{ 1189 struct i7core_dev *i7core_dev, *tmp; 1190 1191 list_for_each_entry_safe(i7core_dev, tmp, &i7core_edac_list, list) 1192 i7core_put_devices(i7core_dev); 1193} 1194 1195static void __init i7core_xeon_pci_fixup(struct pci_id_table *table) 1196{ 1197 struct pci_dev *pdev = NULL; 1198 int i; 1199 /* 1200 * On Xeon 55xx, the Intel Quckpath Arch Generic Non-core pci buses 1201 * aren't announced by acpi. So, we need to use a legacy scan probing 1202 * to detect them 1203 */ 1204 while (table && table->descr) { 1205 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, table->descr[0].dev_id, NULL); 1206 if (unlikely(!pdev)) { 1207 for (i = 0; i < MAX_SOCKET_BUSES; i++) 1208 pcibios_scan_specific_bus(255-i); 1209 } 1210 pci_dev_put(pdev); 1211 table++; 1212 } 1213} 1214 1215static unsigned i7core_pci_lastbus(void) 1216{ 1217 int last_bus = 0, bus; 1218 struct pci_bus *b = NULL; 1219 1220 while ((b = pci_find_next_bus(b)) != NULL) { 1221 bus = b->number; 1222 debugf0("Found bus %d\n", bus); 1223 if (bus > last_bus) 1224 last_bus = bus; 1225 } 1226 1227 debugf0("Last bus %d\n", last_bus); 1228 1229 return last_bus; 1230} 1231 1232/* 1233 * i7core_get_devices Find and perform 'get' operation on the MCH's 1234 * device/functions we want to reference for this driver 1235 * 1236 * Need to 'get' device 16 func 1 and func 2 1237 */ 1238int i7core_get_onedevice(struct pci_dev **prev, int devno, 1239 struct pci_id_descr *dev_descr, unsigned n_devs, 1240 unsigned last_bus) 1241{ 1242 struct i7core_dev *i7core_dev; 1243 1244 struct pci_dev *pdev = NULL; 1245 u8 bus = 0; 1246 u8 socket = 0; 1247 1248 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 1249 dev_descr->dev_id, *prev); 1250 1251 /* 1252 * On Xeon 55xx, the Intel Quckpath Arch Generic Non-core regs 1253 * is at addr 8086:2c40, instead of 8086:2c41. So, we need 1254 * to probe for the alternate address in case of failure 1255 */ 1256 if (dev_descr->dev_id == PCI_DEVICE_ID_INTEL_I7_NONCORE && !pdev) 1257 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 1258 PCI_DEVICE_ID_INTEL_I7_NONCORE_ALT, *prev); 1259 1260 if (dev_descr->dev_id == PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE && !pdev) 1261 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 1262 PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_ALT, 1263 *prev); 1264 1265 if (!pdev) { 1266 if (*prev) { 1267 *prev = pdev; 1268 return 0; 1269 } 1270 1271 if (dev_descr->optional) 1272 return 0; 1273 1274 if (devno == 0) 1275 return -ENODEV; 1276 1277 i7core_printk(KERN_INFO, 1278 "Device not found: dev %02x.%d PCI ID %04x:%04x\n", 1279 dev_descr->dev, dev_descr->func, 1280 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); 1281 1282 /* End of list, leave */ 1283 return -ENODEV; 1284 } 1285 bus = pdev->bus->number; 1286 1287 socket = last_bus - bus; 1288 1289 i7core_dev = get_i7core_dev(socket); 1290 if (!i7core_dev) { 1291 i7core_dev = kzalloc(sizeof(*i7core_dev), GFP_KERNEL); 1292 if (!i7core_dev) 1293 return -ENOMEM; 1294 i7core_dev->pdev = kzalloc(sizeof(*i7core_dev->pdev) * n_devs, 1295 GFP_KERNEL); 1296 if (!i7core_dev->pdev) { 1297 kfree(i7core_dev); 1298 return -ENOMEM; 1299 } 1300 i7core_dev->socket = socket; 1301 i7core_dev->n_devs = n_devs; 1302 list_add_tail(&i7core_dev->list, &i7core_edac_list); 1303 } 1304 1305 if (i7core_dev->pdev[devno]) { 1306 i7core_printk(KERN_ERR, 1307 "Duplicated device for " 1308 "dev %02x:%02x.%d PCI ID %04x:%04x\n", 1309 bus, dev_descr->dev, dev_descr->func, 1310 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); 1311 pci_dev_put(pdev); 1312 return -ENODEV; 1313 } 1314 1315 i7core_dev->pdev[devno] = pdev; 1316 1317 /* Sanity check */ 1318 if (unlikely(PCI_SLOT(pdev->devfn) != dev_descr->dev || 1319 PCI_FUNC(pdev->devfn) != dev_descr->func)) { 1320 i7core_printk(KERN_ERR, 1321 "Device PCI ID %04x:%04x " 1322 "has dev %02x:%02x.%d instead of dev %02x:%02x.%d\n", 1323 PCI_VENDOR_ID_INTEL, dev_descr->dev_id, 1324 bus, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), 1325 bus, dev_descr->dev, dev_descr->func); 1326 return -ENODEV; 1327 } 1328 1329 /* Be sure that the device is enabled */ 1330 if (unlikely(pci_enable_device(pdev) < 0)) { 1331 i7core_printk(KERN_ERR, 1332 "Couldn't enable " 1333 "dev %02x:%02x.%d PCI ID %04x:%04x\n", 1334 bus, dev_descr->dev, dev_descr->func, 1335 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); 1336 return -ENODEV; 1337 } 1338 1339 debugf0("Detected socket %d dev %02x:%02x.%d PCI ID %04x:%04x\n", 1340 socket, bus, dev_descr->dev, 1341 dev_descr->func, 1342 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); 1343 1344 *prev = pdev; 1345 1346 return 0; 1347} 1348 1349static int i7core_get_devices(struct pci_id_table *table) 1350{ 1351 int i, rc, last_bus; 1352 struct pci_dev *pdev = NULL; 1353 struct pci_id_descr *dev_descr; 1354 1355 last_bus = i7core_pci_lastbus(); 1356 1357 while (table && table->descr) { 1358 dev_descr = table->descr; 1359 for (i = 0; i < table->n_devs; i++) { 1360 pdev = NULL; 1361 do { 1362 rc = i7core_get_onedevice(&pdev, i, 1363 &dev_descr[i], 1364 table->n_devs, 1365 last_bus); 1366 if (rc < 0) { 1367 if (i == 0) { 1368 i = table->n_devs; 1369 break; 1370 } 1371 i7core_put_all_devices(); 1372 return -ENODEV; 1373 } 1374 } while (pdev); 1375 } 1376 table++; 1377 } 1378 1379 return 0; 1380 return 0; 1381} 1382 1383static int mci_bind_devs(struct mem_ctl_info *mci, 1384 struct i7core_dev *i7core_dev) 1385{ 1386 struct i7core_pvt *pvt = mci->pvt_info; 1387 struct pci_dev *pdev; 1388 int i, func, slot; 1389 1390 /* Associates i7core_dev and mci for future usage */ 1391 pvt->i7core_dev = i7core_dev; 1392 i7core_dev->mci = mci; 1393 1394 pvt->is_registered = 0; 1395 for (i = 0; i < i7core_dev->n_devs; i++) { 1396 pdev = i7core_dev->pdev[i]; 1397 if (!pdev) 1398 continue; 1399 1400 func = PCI_FUNC(pdev->devfn); 1401 slot = PCI_SLOT(pdev->devfn); 1402 if (slot == 3) { 1403 if (unlikely(func > MAX_MCR_FUNC)) 1404 goto error; 1405 pvt->pci_mcr[func] = pdev; 1406 } else if (likely(slot >= 4 && slot < 4 + NUM_CHANS)) { 1407 if (unlikely(func > MAX_CHAN_FUNC)) 1408 goto error; 1409 pvt->pci_ch[slot - 4][func] = pdev; 1410 } else if (!slot && !func) 1411 pvt->pci_noncore = pdev; 1412 else 1413 goto error; 1414 1415 debugf0("Associated fn %d.%d, dev = %p, socket %d\n", 1416 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), 1417 pdev, i7core_dev->socket); 1418 1419 if (PCI_SLOT(pdev->devfn) == 3 && 1420 PCI_FUNC(pdev->devfn) == 2) 1421 pvt->is_registered = 1; 1422 } 1423 1424 /* 1425 * Add extra nodes to count errors on udimm 1426 * For registered memory, this is not needed, since the counters 1427 * are already displayed at the standard locations 1428 */ 1429 if (!pvt->is_registered) 1430 i7core_sysfs_attrs[ARRAY_SIZE(i7core_sysfs_attrs)-2].grp = 1431 &i7core_udimm_counters; 1432 1433 return 0; 1434 1435error: 1436 i7core_printk(KERN_ERR, "Device %d, function %d " 1437 "is out of the expected range\n", 1438 slot, func); 1439 return -EINVAL; 1440} 1441 1442/**************************************************************************** 1443 Error check routines 1444 ****************************************************************************/ 1445static void i7core_rdimm_update_csrow(struct mem_ctl_info *mci, 1446 int chan, int dimm, int add) 1447{ 1448 char *msg; 1449 struct i7core_pvt *pvt = mci->pvt_info; 1450 int row = pvt->csrow_map[chan][dimm], i; 1451 1452 for (i = 0; i < add; i++) { 1453 msg = kasprintf(GFP_KERNEL, "Corrected error " 1454 "(Socket=%d channel=%d dimm=%d)", 1455 pvt->i7core_dev->socket, chan, dimm); 1456 1457 edac_mc_handle_fbd_ce(mci, row, 0, msg); 1458 kfree (msg); 1459 } 1460} 1461 1462static void i7core_rdimm_update_ce_count(struct mem_ctl_info *mci, 1463 int chan, int new0, int new1, int new2) 1464{ 1465 struct i7core_pvt *pvt = mci->pvt_info; 1466 int add0 = 0, add1 = 0, add2 = 0; 1467 /* Updates CE counters if it is not the first time here */ 1468 if (pvt->ce_count_available) { 1469 /* Updates CE counters */ 1470 1471 add2 = new2 - pvt->rdimm_last_ce_count[chan][2]; 1472 add1 = new1 - pvt->rdimm_last_ce_count[chan][1]; 1473 add0 = new0 - pvt->rdimm_last_ce_count[chan][0]; 1474 1475 if (add2 < 0) 1476 add2 += 0x7fff; 1477 pvt->rdimm_ce_count[chan][2] += add2; 1478 1479 if (add1 < 0) 1480 add1 += 0x7fff; 1481 pvt->rdimm_ce_count[chan][1] += add1; 1482 1483 if (add0 < 0) 1484 add0 += 0x7fff; 1485 pvt->rdimm_ce_count[chan][0] += add0; 1486 } else 1487 pvt->ce_count_available = 1; 1488 1489 /* Store the new values */ 1490 pvt->rdimm_last_ce_count[chan][2] = new2; 1491 pvt->rdimm_last_ce_count[chan][1] = new1; 1492 pvt->rdimm_last_ce_count[chan][0] = new0; 1493 1494 /*updated the edac core */ 1495 if (add0 != 0) 1496 i7core_rdimm_update_csrow(mci, chan, 0, add0); 1497 if (add1 != 0) 1498 i7core_rdimm_update_csrow(mci, chan, 1, add1); 1499 if (add2 != 0) 1500 i7core_rdimm_update_csrow(mci, chan, 2, add2); 1501 1502} 1503 1504static void i7core_rdimm_check_mc_ecc_err(struct mem_ctl_info *mci) 1505{ 1506 struct i7core_pvt *pvt = mci->pvt_info; 1507 u32 rcv[3][2]; 1508 int i, new0, new1, new2; 1509 1510 /*Read DEV 3: FUN 2: MC_COR_ECC_CNT regs directly*/ 1511 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_0, 1512 &rcv[0][0]); 1513 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_1, 1514 &rcv[0][1]); 1515 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_2, 1516 &rcv[1][0]); 1517 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_3, 1518 &rcv[1][1]); 1519 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_4, 1520 &rcv[2][0]); 1521 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_5, 1522 &rcv[2][1]); 1523 for (i = 0 ; i < 3; i++) { 1524 debugf3("MC_COR_ECC_CNT%d = 0x%x; MC_COR_ECC_CNT%d = 0x%x\n", 1525 (i * 2), rcv[i][0], (i * 2) + 1, rcv[i][1]); 1526 /*if the channel has 3 dimms*/ 1527 if (pvt->channel[i].dimms > 2) { 1528 new0 = DIMM_BOT_COR_ERR(rcv[i][0]); 1529 new1 = DIMM_TOP_COR_ERR(rcv[i][0]); 1530 new2 = DIMM_BOT_COR_ERR(rcv[i][1]); 1531 } else { 1532 new0 = DIMM_TOP_COR_ERR(rcv[i][0]) + 1533 DIMM_BOT_COR_ERR(rcv[i][0]); 1534 new1 = DIMM_TOP_COR_ERR(rcv[i][1]) + 1535 DIMM_BOT_COR_ERR(rcv[i][1]); 1536 new2 = 0; 1537 } 1538 1539 i7core_rdimm_update_ce_count(mci, i, new0, new1, new2); 1540 } 1541} 1542 1543/* This function is based on the device 3 function 4 registers as described on: 1544 * Intel Xeon Processor 5500 Series Datasheet Volume 2 1545 * http://www.intel.com/Assets/PDF/datasheet/321322.pdf 1546 * also available at: 1547 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf 1548 */ 1549static void i7core_udimm_check_mc_ecc_err(struct mem_ctl_info *mci) 1550{ 1551 struct i7core_pvt *pvt = mci->pvt_info; 1552 u32 rcv1, rcv0; 1553 int new0, new1, new2; 1554 1555 if (!pvt->pci_mcr[4]) { 1556 debugf0("%s MCR registers not found\n", __func__); 1557 return; 1558 } 1559 1560 /* Corrected test errors */ 1561 pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV1, &rcv1); 1562 pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV0, &rcv0); 1563 1564 /* Store the new values */ 1565 new2 = DIMM2_COR_ERR(rcv1); 1566 new1 = DIMM1_COR_ERR(rcv0); 1567 new0 = DIMM0_COR_ERR(rcv0); 1568 1569 /* Updates CE counters if it is not the first time here */ 1570 if (pvt->ce_count_available) { 1571 /* Updates CE counters */ 1572 int add0, add1, add2; 1573 1574 add2 = new2 - pvt->udimm_last_ce_count[2]; 1575 add1 = new1 - pvt->udimm_last_ce_count[1]; 1576 add0 = new0 - pvt->udimm_last_ce_count[0]; 1577 1578 if (add2 < 0) 1579 add2 += 0x7fff; 1580 pvt->udimm_ce_count[2] += add2; 1581 1582 if (add1 < 0) 1583 add1 += 0x7fff; 1584 pvt->udimm_ce_count[1] += add1; 1585 1586 if (add0 < 0) 1587 add0 += 0x7fff; 1588 pvt->udimm_ce_count[0] += add0; 1589 1590 if (add0 | add1 | add2) 1591 i7core_printk(KERN_ERR, "New Corrected error(s): " 1592 "dimm0: +%d, dimm1: +%d, dimm2 +%d\n", 1593 add0, add1, add2); 1594 } else 1595 pvt->ce_count_available = 1; 1596 1597 /* Store the new values */ 1598 pvt->udimm_last_ce_count[2] = new2; 1599 pvt->udimm_last_ce_count[1] = new1; 1600 pvt->udimm_last_ce_count[0] = new0; 1601} 1602 1603/* 1604 * According with tables E-11 and E-12 of chapter E.3.3 of Intel 64 and IA-32 1605 * Architectures Software Developer���s Manual Volume 3B. 1606 * Nehalem are defined as family 0x06, model 0x1a 1607 * 1608 * The MCA registers used here are the following ones: 1609 * struct mce field MCA Register 1610 * m->status MSR_IA32_MC8_STATUS 1611 * m->addr MSR_IA32_MC8_ADDR 1612 * m->misc MSR_IA32_MC8_MISC 1613 * In the case of Nehalem, the error information is masked at .status and .misc 1614 * fields 1615 */ 1616static void i7core_mce_output_error(struct mem_ctl_info *mci, 1617 struct mce *m) 1618{ 1619 struct i7core_pvt *pvt = mci->pvt_info; 1620 char *type, *optype, *err, *msg; 1621 unsigned long error = m->status & 0x1ff0000l; 1622 u32 optypenum = (m->status >> 4) & 0x07; 1623 u32 core_err_cnt = (m->status >> 38) && 0x7fff; 1624 u32 dimm = (m->misc >> 16) & 0x3; 1625 u32 channel = (m->misc >> 18) & 0x3; 1626 u32 syndrome = m->misc >> 32; 1627 u32 errnum = find_first_bit(&error, 32); 1628 int csrow; 1629 1630 if (m->mcgstatus & 1) 1631 type = "FATAL"; 1632 else 1633 type = "NON_FATAL"; 1634 1635 switch (optypenum) { 1636 case 0: 1637 optype = "generic undef request"; 1638 break; 1639 case 1: 1640 optype = "read error"; 1641 break; 1642 case 2: 1643 optype = "write error"; 1644 break; 1645 case 3: 1646 optype = "addr/cmd error"; 1647 break; 1648 case 4: 1649 optype = "scrubbing error"; 1650 break; 1651 default: 1652 optype = "reserved"; 1653 break; 1654 } 1655 1656 switch (errnum) { 1657 case 16: 1658 err = "read ECC error"; 1659 break; 1660 case 17: 1661 err = "RAS ECC error"; 1662 break; 1663 case 18: 1664 err = "write parity error"; 1665 break; 1666 case 19: 1667 err = "redundacy loss"; 1668 break; 1669 case 20: 1670 err = "reserved"; 1671 break; 1672 case 21: 1673 err = "memory range error"; 1674 break; 1675 case 22: 1676 err = "RTID out of range"; 1677 break; 1678 case 23: 1679 err = "address parity error"; 1680 break; 1681 case 24: 1682 err = "byte enable parity error"; 1683 break; 1684 default: 1685 err = "unknown"; 1686 } 1687 1688 msg = kasprintf(GFP_ATOMIC, 1689 "%s (addr = 0x%08llx, cpu=%d, Dimm=%d, Channel=%d, " 1690 "syndrome=0x%08x, count=%d, Err=%08llx:%08llx (%s: %s))\n", 1691 type, (long long) m->addr, m->cpu, dimm, channel, 1692 syndrome, core_err_cnt, (long long)m->status, 1693 (long long)m->misc, optype, err); 1694 1695 debugf0("%s", msg); 1696 1697 csrow = pvt->csrow_map[channel][dimm]; 1698 1699 /* Call the helper to output message */ 1700 if (m->mcgstatus & 1) 1701 edac_mc_handle_fbd_ue(mci, csrow, 0, 1702 0, msg); 1703 else if (!pvt->is_registered) 1704 edac_mc_handle_fbd_ce(mci, csrow, 1705 0, msg); 1706 1707 kfree(msg); 1708} 1709 1710/* 1711 * i7core_check_error Retrieve and process errors reported by the 1712 * hardware. Called by the Core module. 1713 */ 1714static void i7core_check_error(struct mem_ctl_info *mci) 1715{ 1716 struct i7core_pvt *pvt = mci->pvt_info; 1717 int i; 1718 unsigned count = 0; 1719 struct mce *m; 1720 1721 /* 1722 * MCE first step: Copy all mce errors into a temporary buffer 1723 * We use a double buffering here, to reduce the risk of 1724 * loosing an error. 1725 */ 1726 smp_rmb(); 1727 count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in) 1728 % MCE_LOG_LEN; 1729 if (!count) 1730 goto check_ce_error; 1731 1732 m = pvt->mce_outentry; 1733 if (pvt->mce_in + count > MCE_LOG_LEN) { 1734 unsigned l = MCE_LOG_LEN - pvt->mce_in; 1735 1736 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * l); 1737 smp_wmb(); 1738 pvt->mce_in = 0; 1739 count -= l; 1740 m += l; 1741 } 1742 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * count); 1743 smp_wmb(); 1744 pvt->mce_in += count; 1745 1746 smp_rmb(); 1747 if (pvt->mce_overrun) { 1748 i7core_printk(KERN_ERR, "Lost %d memory errors\n", 1749 pvt->mce_overrun); 1750 smp_wmb(); 1751 pvt->mce_overrun = 0; 1752 } 1753 1754 /* 1755 * MCE second step: parse errors and display 1756 */ 1757 for (i = 0; i < count; i++) 1758 i7core_mce_output_error(mci, &pvt->mce_outentry[i]); 1759 1760 /* 1761 * Now, let's increment CE error counts 1762 */ 1763check_ce_error: 1764 if (!pvt->is_registered) 1765 i7core_udimm_check_mc_ecc_err(mci); 1766 else 1767 i7core_rdimm_check_mc_ecc_err(mci); 1768} 1769 1770/* 1771 * i7core_mce_check_error Replicates mcelog routine to get errors 1772 * This routine simply queues mcelog errors, and 1773 * return. The error itself should be handled later 1774 * by i7core_check_error. 1775 * WARNING: As this routine should be called at NMI time, extra care should 1776 * be taken to avoid deadlocks, and to be as fast as possible. 1777 */ 1778static int i7core_mce_check_error(void *priv, struct mce *mce) 1779{ 1780 struct mem_ctl_info *mci = priv; 1781 struct i7core_pvt *pvt = mci->pvt_info; 1782 1783 /* 1784 * Just let mcelog handle it if the error is 1785 * outside the memory controller 1786 */ 1787 if (((mce->status & 0xffff) >> 7) != 1) 1788 return 0; 1789 1790 /* Bank 8 registers are the only ones that we know how to handle */ 1791 if (mce->bank != 8) 1792 return 0; 1793 1794#ifdef CONFIG_SMP 1795 /* Only handle if it is the right mc controller */ 1796 if (cpu_data(mce->cpu).phys_proc_id != pvt->i7core_dev->socket) 1797 return 0; 1798#endif 1799 1800 smp_rmb(); 1801 if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) { 1802 smp_wmb(); 1803 pvt->mce_overrun++; 1804 return 0; 1805 } 1806 1807 /* Copy memory error at the ringbuffer */ 1808 memcpy(&pvt->mce_entry[pvt->mce_out], mce, sizeof(*mce)); 1809 smp_wmb(); 1810 pvt->mce_out = (pvt->mce_out + 1) % MCE_LOG_LEN; 1811 1812 /* Handle fatal errors immediately */ 1813 if (mce->mcgstatus & 1) 1814 i7core_check_error(mci); 1815 1816 /* Advice mcelog that the error were handled */ 1817 return 1; 1818} 1819 1820static int i7core_register_mci(struct i7core_dev *i7core_dev, 1821 int num_channels, int num_csrows) 1822{ 1823 struct mem_ctl_info *mci; 1824 struct i7core_pvt *pvt; 1825 int csrow = 0; 1826 int rc; 1827 1828 /* allocate a new MC control structure */ 1829 mci = edac_mc_alloc(sizeof(*pvt), num_csrows, num_channels, 1830 i7core_dev->socket); 1831 if (unlikely(!mci)) 1832 return -ENOMEM; 1833 1834 debugf0("MC: " __FILE__ ": %s(): mci = %p\n", __func__, mci); 1835 1836 /* record ptr to the generic device */ 1837 mci->dev = &i7core_dev->pdev[0]->dev; 1838 1839 pvt = mci->pvt_info; 1840 memset(pvt, 0, sizeof(*pvt)); 1841 1842 mci->mtype_cap = MEM_FLAG_DDR3; 1843 mci->edac_ctl_cap = EDAC_FLAG_NONE; 1844 mci->edac_cap = EDAC_FLAG_NONE; 1845 mci->mod_name = "i7core_edac.c"; 1846 mci->mod_ver = I7CORE_REVISION; 1847 mci->ctl_name = kasprintf(GFP_KERNEL, "i7 core #%d", 1848 i7core_dev->socket); 1849 mci->dev_name = pci_name(i7core_dev->pdev[0]); 1850 mci->ctl_page_to_phys = NULL; 1851 mci->mc_driver_sysfs_attributes = i7core_sysfs_attrs; 1852 /* Set the function pointer to an actual operation function */ 1853 mci->edac_check = i7core_check_error; 1854 1855 /* Store pci devices at mci for faster access */ 1856 rc = mci_bind_devs(mci, i7core_dev); 1857 if (unlikely(rc < 0)) 1858 goto fail; 1859 1860 /* Get dimm basic config */ 1861 get_dimm_config(mci, &csrow); 1862 1863 /* add this new MC control structure to EDAC's list of MCs */ 1864 if (unlikely(edac_mc_add_mc(mci))) { 1865 debugf0("MC: " __FILE__ 1866 ": %s(): failed edac_mc_add_mc()\n", __func__); 1867 1868 rc = -EINVAL; 1869 goto fail; 1870 } 1871 1872 /* allocating generic PCI control info */ 1873 i7core_pci = edac_pci_create_generic_ctl(&i7core_dev->pdev[0]->dev, 1874 EDAC_MOD_STR); 1875 if (unlikely(!i7core_pci)) { 1876 printk(KERN_WARNING 1877 "%s(): Unable to create PCI control\n", 1878 __func__); 1879 printk(KERN_WARNING 1880 "%s(): PCI error report via EDAC not setup\n", 1881 __func__); 1882 } 1883 1884 /* Default error mask is any memory */ 1885 pvt->inject.channel = 0; 1886 pvt->inject.dimm = -1; 1887 pvt->inject.rank = -1; 1888 pvt->inject.bank = -1; 1889 pvt->inject.page = -1; 1890 pvt->inject.col = -1; 1891 1892 /* Registers on edac_mce in order to receive memory errors */ 1893 pvt->edac_mce.priv = mci; 1894 pvt->edac_mce.check_error = i7core_mce_check_error; 1895 1896 rc = edac_mce_register(&pvt->edac_mce); 1897 if (unlikely(rc < 0)) { 1898 debugf0("MC: " __FILE__ 1899 ": %s(): failed edac_mce_register()\n", __func__); 1900 } 1901 1902fail: 1903 if (rc < 0) 1904 edac_mc_free(mci); 1905 return rc; 1906} 1907 1908/* 1909 * i7core_probe Probe for ONE instance of device to see if it is 1910 * present. 1911 * return: 1912 * 0 for FOUND a device 1913 * < 0 for error code 1914 */ 1915 1916static int probed = 0; 1917 1918static int __devinit i7core_probe(struct pci_dev *pdev, 1919 const struct pci_device_id *id) 1920{ 1921 int rc; 1922 struct i7core_dev *i7core_dev; 1923 1924 /* get the pci devices we want to reserve for our use */ 1925 mutex_lock(&i7core_edac_lock); 1926 1927 /* 1928 * All memory controllers are allocated at the first pass. 1929 */ 1930 if (unlikely(probed >= 1)) { 1931 mutex_unlock(&i7core_edac_lock); 1932 return -EINVAL; 1933 } 1934 probed++; 1935 1936 rc = i7core_get_devices(pci_dev_table); 1937 if (unlikely(rc < 0)) 1938 goto fail0; 1939 1940 list_for_each_entry(i7core_dev, &i7core_edac_list, list) { 1941 int channels; 1942 int csrows; 1943 1944 /* Check the number of active and not disabled channels */ 1945 rc = i7core_get_active_channels(i7core_dev->socket, 1946 &channels, &csrows); 1947 if (unlikely(rc < 0)) 1948 goto fail1; 1949 1950 rc = i7core_register_mci(i7core_dev, channels, csrows); 1951 if (unlikely(rc < 0)) 1952 goto fail1; 1953 } 1954 1955 i7core_printk(KERN_INFO, "Driver loaded.\n"); 1956 1957 mutex_unlock(&i7core_edac_lock); 1958 return 0; 1959 1960fail1: 1961 i7core_put_all_devices(); 1962fail0: 1963 mutex_unlock(&i7core_edac_lock); 1964 return rc; 1965} 1966 1967/* 1968 * i7core_remove destructor for one instance of device 1969 * 1970 */ 1971static void __devexit i7core_remove(struct pci_dev *pdev) 1972{ 1973 struct mem_ctl_info *mci; 1974 struct i7core_dev *i7core_dev, *tmp; 1975 1976 debugf0(__FILE__ ": %s()\n", __func__); 1977 1978 if (i7core_pci) 1979 edac_pci_release_generic_ctl(i7core_pci); 1980 1981 /* 1982 * we have a trouble here: pdev value for removal will be wrong, since 1983 * it will point to the X58 register used to detect that the machine 1984 * is a Nehalem or upper design. However, due to the way several PCI 1985 * devices are grouped together to provide MC functionality, we need 1986 * to use a different method for releasing the devices 1987 */ 1988 1989 mutex_lock(&i7core_edac_lock); 1990 list_for_each_entry_safe(i7core_dev, tmp, &i7core_edac_list, list) { 1991 mci = edac_mc_del_mc(&i7core_dev->pdev[0]->dev); 1992 if (mci) { 1993 struct i7core_pvt *pvt = mci->pvt_info; 1994 1995 i7core_dev = pvt->i7core_dev; 1996 edac_mce_unregister(&pvt->edac_mce); 1997 kfree(mci->ctl_name); 1998 edac_mc_free(mci); 1999 i7core_put_devices(i7core_dev); 2000 } else { 2001 i7core_printk(KERN_ERR, 2002 "Couldn't find mci for socket %d\n", 2003 i7core_dev->socket); 2004 } 2005 } 2006 probed--; 2007 2008 mutex_unlock(&i7core_edac_lock); 2009} 2010 2011MODULE_DEVICE_TABLE(pci, i7core_pci_tbl); 2012 2013/* 2014 * i7core_driver pci_driver structure for this module 2015 * 2016 */ 2017static struct pci_driver i7core_driver = { 2018 .name = "i7core_edac", 2019 .probe = i7core_probe, 2020 .remove = __devexit_p(i7core_remove), 2021 .id_table = i7core_pci_tbl, 2022}; 2023 2024/* 2025 * i7core_init Module entry function 2026 * Try to initialize this module for its devices 2027 */ 2028static int __init i7core_init(void) 2029{ 2030 int pci_rc; 2031 2032 debugf2("MC: " __FILE__ ": %s()\n", __func__); 2033 2034 /* Ensure that the OPSTATE is set correctly for POLL or NMI */ 2035 opstate_init(); 2036 2037 i7core_xeon_pci_fixup(pci_dev_table); 2038 2039 pci_rc = pci_register_driver(&i7core_driver); 2040 2041 if (pci_rc >= 0) 2042 return 0; 2043 2044 i7core_printk(KERN_ERR, "Failed to register device with error %d.\n", 2045 pci_rc); 2046 2047 return pci_rc; 2048} 2049 2050/* 2051 * i7core_exit() Module exit function 2052 * Unregister the driver 2053 */ 2054static void __exit i7core_exit(void) 2055{ 2056 debugf2("MC: " __FILE__ ": %s()\n", __func__); 2057 pci_unregister_driver(&i7core_driver); 2058} 2059 2060module_init(i7core_init); 2061module_exit(i7core_exit); 2062 2063MODULE_LICENSE("GPL"); 2064MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); 2065MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)"); 2066MODULE_DESCRIPTION("MC Driver for Intel i7 Core memory controllers - " 2067 I7CORE_REVISION); 2068 2069module_param(edac_op_state, int, 0444); 2070MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); 2071