1/* 2 * Xilinx SystemACE device driver 3 * 4 * Copyright 2007 Secret Lab Technologies Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published 8 * by the Free Software Foundation. 9 */ 10 11/* 12 * The SystemACE chip is designed to configure FPGAs by loading an FPGA 13 * bitstream from a file on a CF card and squirting it into FPGAs connected 14 * to the SystemACE JTAG chain. It also has the advantage of providing an 15 * MPU interface which can be used to control the FPGA configuration process 16 * and to use the attached CF card for general purpose storage. 17 * 18 * This driver is a block device driver for the SystemACE. 19 * 20 * Initialization: 21 * The driver registers itself as a platform_device driver at module 22 * load time. The platform bus will take care of calling the 23 * ace_probe() method for all SystemACE instances in the system. Any 24 * number of SystemACE instances are supported. ace_probe() calls 25 * ace_setup() which initialized all data structures, reads the CF 26 * id structure and registers the device. 27 * 28 * Processing: 29 * Just about all of the heavy lifting in this driver is performed by 30 * a Finite State Machine (FSM). The driver needs to wait on a number 31 * of events; some raised by interrupts, some which need to be polled 32 * for. Describing all of the behaviour in a FSM seems to be the 33 * easiest way to keep the complexity low and make it easy to 34 * understand what the driver is doing. If the block ops or the 35 * request function need to interact with the hardware, then they 36 * simply need to flag the request and kick of FSM processing. 37 * 38 * The FSM itself is atomic-safe code which can be run from any 39 * context. The general process flow is: 40 * 1. obtain the ace->lock spinlock. 41 * 2. loop on ace_fsm_dostate() until the ace->fsm_continue flag is 42 * cleared. 43 * 3. release the lock. 44 * 45 * Individual states do not sleep in any way. If a condition needs to 46 * be waited for then the state much clear the fsm_continue flag and 47 * either schedule the FSM to be run again at a later time, or expect 48 * an interrupt to call the FSM when the desired condition is met. 49 * 50 * In normal operation, the FSM is processed at interrupt context 51 * either when the driver's tasklet is scheduled, or when an irq is 52 * raised by the hardware. The tasklet can be scheduled at any time. 53 * The request method in particular schedules the tasklet when a new 54 * request has been indicated by the block layer. Once started, the 55 * FSM proceeds as far as it can processing the request until it 56 * needs on a hardware event. At this point, it must yield execution. 57 * 58 * A state has two options when yielding execution: 59 * 1. ace_fsm_yield() 60 * - Call if need to poll for event. 61 * - clears the fsm_continue flag to exit the processing loop 62 * - reschedules the tasklet to run again as soon as possible 63 * 2. ace_fsm_yieldirq() 64 * - Call if an irq is expected from the HW 65 * - clears the fsm_continue flag to exit the processing loop 66 * - does not reschedule the tasklet so the FSM will not be processed 67 * again until an irq is received. 68 * After calling a yield function, the state must return control back 69 * to the FSM main loop. 70 * 71 * Additionally, the driver maintains a kernel timer which can process 72 * the FSM. If the FSM gets stalled, typically due to a missed 73 * interrupt, then the kernel timer will expire and the driver can 74 * continue where it left off. 75 * 76 * To Do: 77 * - Add FPGA configuration control interface. 78 * - Request major number from lanana 79 */ 80 81#undef DEBUG 82 83#include <linux/module.h> 84#include <linux/ctype.h> 85#include <linux/init.h> 86#include <linux/interrupt.h> 87#include <linux/errno.h> 88#include <linux/kernel.h> 89#include <linux/delay.h> 90#include <linux/slab.h> 91#include <linux/blkdev.h> 92#include <linux/smp_lock.h> 93#include <linux/ata.h> 94#include <linux/hdreg.h> 95#include <linux/platform_device.h> 96#if defined(CONFIG_OF) 97#include <linux/of_address.h> 98#include <linux/of_device.h> 99#include <linux/of_platform.h> 100#endif 101 102MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>"); 103MODULE_DESCRIPTION("Xilinx SystemACE device driver"); 104MODULE_LICENSE("GPL"); 105 106/* SystemACE register definitions */ 107#define ACE_BUSMODE (0x00) 108 109#define ACE_STATUS (0x04) 110#define ACE_STATUS_CFGLOCK (0x00000001) 111#define ACE_STATUS_MPULOCK (0x00000002) 112#define ACE_STATUS_CFGERROR (0x00000004) /* config controller error */ 113#define ACE_STATUS_CFCERROR (0x00000008) /* CF controller error */ 114#define ACE_STATUS_CFDETECT (0x00000010) 115#define ACE_STATUS_DATABUFRDY (0x00000020) 116#define ACE_STATUS_DATABUFMODE (0x00000040) 117#define ACE_STATUS_CFGDONE (0x00000080) 118#define ACE_STATUS_RDYFORCFCMD (0x00000100) 119#define ACE_STATUS_CFGMODEPIN (0x00000200) 120#define ACE_STATUS_CFGADDR_MASK (0x0000e000) 121#define ACE_STATUS_CFBSY (0x00020000) 122#define ACE_STATUS_CFRDY (0x00040000) 123#define ACE_STATUS_CFDWF (0x00080000) 124#define ACE_STATUS_CFDSC (0x00100000) 125#define ACE_STATUS_CFDRQ (0x00200000) 126#define ACE_STATUS_CFCORR (0x00400000) 127#define ACE_STATUS_CFERR (0x00800000) 128 129#define ACE_ERROR (0x08) 130#define ACE_CFGLBA (0x0c) 131#define ACE_MPULBA (0x10) 132 133#define ACE_SECCNTCMD (0x14) 134#define ACE_SECCNTCMD_RESET (0x0100) 135#define ACE_SECCNTCMD_IDENTIFY (0x0200) 136#define ACE_SECCNTCMD_READ_DATA (0x0300) 137#define ACE_SECCNTCMD_WRITE_DATA (0x0400) 138#define ACE_SECCNTCMD_ABORT (0x0600) 139 140#define ACE_VERSION (0x16) 141#define ACE_VERSION_REVISION_MASK (0x00FF) 142#define ACE_VERSION_MINOR_MASK (0x0F00) 143#define ACE_VERSION_MAJOR_MASK (0xF000) 144 145#define ACE_CTRL (0x18) 146#define ACE_CTRL_FORCELOCKREQ (0x0001) 147#define ACE_CTRL_LOCKREQ (0x0002) 148#define ACE_CTRL_FORCECFGADDR (0x0004) 149#define ACE_CTRL_FORCECFGMODE (0x0008) 150#define ACE_CTRL_CFGMODE (0x0010) 151#define ACE_CTRL_CFGSTART (0x0020) 152#define ACE_CTRL_CFGSEL (0x0040) 153#define ACE_CTRL_CFGRESET (0x0080) 154#define ACE_CTRL_DATABUFRDYIRQ (0x0100) 155#define ACE_CTRL_ERRORIRQ (0x0200) 156#define ACE_CTRL_CFGDONEIRQ (0x0400) 157#define ACE_CTRL_RESETIRQ (0x0800) 158#define ACE_CTRL_CFGPROG (0x1000) 159#define ACE_CTRL_CFGADDR_MASK (0xe000) 160 161#define ACE_FATSTAT (0x1c) 162 163#define ACE_NUM_MINORS 16 164#define ACE_SECTOR_SIZE (512) 165#define ACE_FIFO_SIZE (32) 166#define ACE_BUF_PER_SECTOR (ACE_SECTOR_SIZE / ACE_FIFO_SIZE) 167 168#define ACE_BUS_WIDTH_8 0 169#define ACE_BUS_WIDTH_16 1 170 171struct ace_reg_ops; 172 173struct ace_device { 174 /* driver state data */ 175 int id; 176 int media_change; 177 int users; 178 struct list_head list; 179 180 /* finite state machine data */ 181 struct tasklet_struct fsm_tasklet; 182 uint fsm_task; /* Current activity (ACE_TASK_*) */ 183 uint fsm_state; /* Current state (ACE_FSM_STATE_*) */ 184 uint fsm_continue_flag; /* cleared to exit FSM mainloop */ 185 uint fsm_iter_num; 186 struct timer_list stall_timer; 187 188 /* Transfer state/result, use for both id and block request */ 189 struct request *req; /* request being processed */ 190 void *data_ptr; /* pointer to I/O buffer */ 191 int data_count; /* number of buffers remaining */ 192 int data_result; /* Result of transfer; 0 := success */ 193 194 int id_req_count; /* count of id requests */ 195 int id_result; 196 struct completion id_completion; /* used when id req finishes */ 197 int in_irq; 198 199 /* Details of hardware device */ 200 resource_size_t physaddr; 201 void __iomem *baseaddr; 202 int irq; 203 int bus_width; /* 0 := 8 bit; 1 := 16 bit */ 204 struct ace_reg_ops *reg_ops; 205 int lock_count; 206 207 /* Block device data structures */ 208 spinlock_t lock; 209 struct device *dev; 210 struct request_queue *queue; 211 struct gendisk *gd; 212 213 /* Inserted CF card parameters */ 214 u16 cf_id[ATA_ID_WORDS]; 215}; 216 217static int ace_major; 218 219/* --------------------------------------------------------------------- 220 * Low level register access 221 */ 222 223struct ace_reg_ops { 224 u16(*in) (struct ace_device * ace, int reg); 225 void (*out) (struct ace_device * ace, int reg, u16 val); 226 void (*datain) (struct ace_device * ace); 227 void (*dataout) (struct ace_device * ace); 228}; 229 230/* 8 Bit bus width */ 231static u16 ace_in_8(struct ace_device *ace, int reg) 232{ 233 void __iomem *r = ace->baseaddr + reg; 234 return in_8(r) | (in_8(r + 1) << 8); 235} 236 237static void ace_out_8(struct ace_device *ace, int reg, u16 val) 238{ 239 void __iomem *r = ace->baseaddr + reg; 240 out_8(r, val); 241 out_8(r + 1, val >> 8); 242} 243 244static void ace_datain_8(struct ace_device *ace) 245{ 246 void __iomem *r = ace->baseaddr + 0x40; 247 u8 *dst = ace->data_ptr; 248 int i = ACE_FIFO_SIZE; 249 while (i--) 250 *dst++ = in_8(r++); 251 ace->data_ptr = dst; 252} 253 254static void ace_dataout_8(struct ace_device *ace) 255{ 256 void __iomem *r = ace->baseaddr + 0x40; 257 u8 *src = ace->data_ptr; 258 int i = ACE_FIFO_SIZE; 259 while (i--) 260 out_8(r++, *src++); 261 ace->data_ptr = src; 262} 263 264static struct ace_reg_ops ace_reg_8_ops = { 265 .in = ace_in_8, 266 .out = ace_out_8, 267 .datain = ace_datain_8, 268 .dataout = ace_dataout_8, 269}; 270 271/* 16 bit big endian bus attachment */ 272static u16 ace_in_be16(struct ace_device *ace, int reg) 273{ 274 return in_be16(ace->baseaddr + reg); 275} 276 277static void ace_out_be16(struct ace_device *ace, int reg, u16 val) 278{ 279 out_be16(ace->baseaddr + reg, val); 280} 281 282static void ace_datain_be16(struct ace_device *ace) 283{ 284 int i = ACE_FIFO_SIZE / 2; 285 u16 *dst = ace->data_ptr; 286 while (i--) 287 *dst++ = in_le16(ace->baseaddr + 0x40); 288 ace->data_ptr = dst; 289} 290 291static void ace_dataout_be16(struct ace_device *ace) 292{ 293 int i = ACE_FIFO_SIZE / 2; 294 u16 *src = ace->data_ptr; 295 while (i--) 296 out_le16(ace->baseaddr + 0x40, *src++); 297 ace->data_ptr = src; 298} 299 300/* 16 bit little endian bus attachment */ 301static u16 ace_in_le16(struct ace_device *ace, int reg) 302{ 303 return in_le16(ace->baseaddr + reg); 304} 305 306static void ace_out_le16(struct ace_device *ace, int reg, u16 val) 307{ 308 out_le16(ace->baseaddr + reg, val); 309} 310 311static void ace_datain_le16(struct ace_device *ace) 312{ 313 int i = ACE_FIFO_SIZE / 2; 314 u16 *dst = ace->data_ptr; 315 while (i--) 316 *dst++ = in_be16(ace->baseaddr + 0x40); 317 ace->data_ptr = dst; 318} 319 320static void ace_dataout_le16(struct ace_device *ace) 321{ 322 int i = ACE_FIFO_SIZE / 2; 323 u16 *src = ace->data_ptr; 324 while (i--) 325 out_be16(ace->baseaddr + 0x40, *src++); 326 ace->data_ptr = src; 327} 328 329static struct ace_reg_ops ace_reg_be16_ops = { 330 .in = ace_in_be16, 331 .out = ace_out_be16, 332 .datain = ace_datain_be16, 333 .dataout = ace_dataout_be16, 334}; 335 336static struct ace_reg_ops ace_reg_le16_ops = { 337 .in = ace_in_le16, 338 .out = ace_out_le16, 339 .datain = ace_datain_le16, 340 .dataout = ace_dataout_le16, 341}; 342 343static inline u16 ace_in(struct ace_device *ace, int reg) 344{ 345 return ace->reg_ops->in(ace, reg); 346} 347 348static inline u32 ace_in32(struct ace_device *ace, int reg) 349{ 350 return ace_in(ace, reg) | (ace_in(ace, reg + 2) << 16); 351} 352 353static inline void ace_out(struct ace_device *ace, int reg, u16 val) 354{ 355 ace->reg_ops->out(ace, reg, val); 356} 357 358static inline void ace_out32(struct ace_device *ace, int reg, u32 val) 359{ 360 ace_out(ace, reg, val); 361 ace_out(ace, reg + 2, val >> 16); 362} 363 364/* --------------------------------------------------------------------- 365 * Debug support functions 366 */ 367 368#if defined(DEBUG) 369static void ace_dump_mem(void *base, int len) 370{ 371 const char *ptr = base; 372 int i, j; 373 374 for (i = 0; i < len; i += 16) { 375 printk(KERN_INFO "%.8x:", i); 376 for (j = 0; j < 16; j++) { 377 if (!(j % 4)) 378 printk(" "); 379 printk("%.2x", ptr[i + j]); 380 } 381 printk(" "); 382 for (j = 0; j < 16; j++) 383 printk("%c", isprint(ptr[i + j]) ? ptr[i + j] : '.'); 384 printk("\n"); 385 } 386} 387#else 388static inline void ace_dump_mem(void *base, int len) 389{ 390} 391#endif 392 393static void ace_dump_regs(struct ace_device *ace) 394{ 395 dev_info(ace->dev, 396 " ctrl: %.8x seccnt/cmd: %.4x ver:%.4x\n" 397 " status:%.8x mpu_lba:%.8x busmode:%4x\n" 398 " error: %.8x cfg_lba:%.8x fatstat:%.4x\n", 399 ace_in32(ace, ACE_CTRL), 400 ace_in(ace, ACE_SECCNTCMD), 401 ace_in(ace, ACE_VERSION), 402 ace_in32(ace, ACE_STATUS), 403 ace_in32(ace, ACE_MPULBA), 404 ace_in(ace, ACE_BUSMODE), 405 ace_in32(ace, ACE_ERROR), 406 ace_in32(ace, ACE_CFGLBA), ace_in(ace, ACE_FATSTAT)); 407} 408 409void ace_fix_driveid(u16 *id) 410{ 411#if defined(__BIG_ENDIAN) 412 int i; 413 414 /* All half words have wrong byte order; swap the bytes */ 415 for (i = 0; i < ATA_ID_WORDS; i++, id++) 416 *id = le16_to_cpu(*id); 417#endif 418} 419 420/* --------------------------------------------------------------------- 421 * Finite State Machine (FSM) implementation 422 */ 423 424/* FSM tasks; used to direct state transitions */ 425#define ACE_TASK_IDLE 0 426#define ACE_TASK_IDENTIFY 1 427#define ACE_TASK_READ 2 428#define ACE_TASK_WRITE 3 429#define ACE_FSM_NUM_TASKS 4 430 431/* FSM state definitions */ 432#define ACE_FSM_STATE_IDLE 0 433#define ACE_FSM_STATE_REQ_LOCK 1 434#define ACE_FSM_STATE_WAIT_LOCK 2 435#define ACE_FSM_STATE_WAIT_CFREADY 3 436#define ACE_FSM_STATE_IDENTIFY_PREPARE 4 437#define ACE_FSM_STATE_IDENTIFY_TRANSFER 5 438#define ACE_FSM_STATE_IDENTIFY_COMPLETE 6 439#define ACE_FSM_STATE_REQ_PREPARE 7 440#define ACE_FSM_STATE_REQ_TRANSFER 8 441#define ACE_FSM_STATE_REQ_COMPLETE 9 442#define ACE_FSM_STATE_ERROR 10 443#define ACE_FSM_NUM_STATES 11 444 445/* Set flag to exit FSM loop and reschedule tasklet */ 446static inline void ace_fsm_yield(struct ace_device *ace) 447{ 448 dev_dbg(ace->dev, "ace_fsm_yield()\n"); 449 tasklet_schedule(&ace->fsm_tasklet); 450 ace->fsm_continue_flag = 0; 451} 452 453/* Set flag to exit FSM loop and wait for IRQ to reschedule tasklet */ 454static inline void ace_fsm_yieldirq(struct ace_device *ace) 455{ 456 dev_dbg(ace->dev, "ace_fsm_yieldirq()\n"); 457 458 if (ace->irq == NO_IRQ) 459 /* No IRQ assigned, so need to poll */ 460 tasklet_schedule(&ace->fsm_tasklet); 461 ace->fsm_continue_flag = 0; 462} 463 464/* Get the next read/write request; ending requests that we don't handle */ 465struct request *ace_get_next_request(struct request_queue * q) 466{ 467 struct request *req; 468 469 while ((req = blk_peek_request(q)) != NULL) { 470 if (req->cmd_type == REQ_TYPE_FS) 471 break; 472 blk_start_request(req); 473 __blk_end_request_all(req, -EIO); 474 } 475 return req; 476} 477 478static void ace_fsm_dostate(struct ace_device *ace) 479{ 480 struct request *req; 481 u32 status; 482 u16 val; 483 int count; 484 485#if defined(DEBUG) 486 dev_dbg(ace->dev, "fsm_state=%i, id_req_count=%i\n", 487 ace->fsm_state, ace->id_req_count); 488#endif 489 490 /* Verify that there is actually a CF in the slot. If not, then 491 * bail out back to the idle state and wake up all the waiters */ 492 status = ace_in32(ace, ACE_STATUS); 493 if ((status & ACE_STATUS_CFDETECT) == 0) { 494 ace->fsm_state = ACE_FSM_STATE_IDLE; 495 ace->media_change = 1; 496 set_capacity(ace->gd, 0); 497 dev_info(ace->dev, "No CF in slot\n"); 498 499 /* Drop all in-flight and pending requests */ 500 if (ace->req) { 501 __blk_end_request_all(ace->req, -EIO); 502 ace->req = NULL; 503 } 504 while ((req = blk_fetch_request(ace->queue)) != NULL) 505 __blk_end_request_all(req, -EIO); 506 507 /* Drop back to IDLE state and notify waiters */ 508 ace->fsm_state = ACE_FSM_STATE_IDLE; 509 ace->id_result = -EIO; 510 while (ace->id_req_count) { 511 complete(&ace->id_completion); 512 ace->id_req_count--; 513 } 514 } 515 516 switch (ace->fsm_state) { 517 case ACE_FSM_STATE_IDLE: 518 /* See if there is anything to do */ 519 if (ace->id_req_count || ace_get_next_request(ace->queue)) { 520 ace->fsm_iter_num++; 521 ace->fsm_state = ACE_FSM_STATE_REQ_LOCK; 522 mod_timer(&ace->stall_timer, jiffies + HZ); 523 if (!timer_pending(&ace->stall_timer)) 524 add_timer(&ace->stall_timer); 525 break; 526 } 527 del_timer(&ace->stall_timer); 528 ace->fsm_continue_flag = 0; 529 break; 530 531 case ACE_FSM_STATE_REQ_LOCK: 532 if (ace_in(ace, ACE_STATUS) & ACE_STATUS_MPULOCK) { 533 /* Already have the lock, jump to next state */ 534 ace->fsm_state = ACE_FSM_STATE_WAIT_CFREADY; 535 break; 536 } 537 538 /* Request the lock */ 539 val = ace_in(ace, ACE_CTRL); 540 ace_out(ace, ACE_CTRL, val | ACE_CTRL_LOCKREQ); 541 ace->fsm_state = ACE_FSM_STATE_WAIT_LOCK; 542 break; 543 544 case ACE_FSM_STATE_WAIT_LOCK: 545 if (ace_in(ace, ACE_STATUS) & ACE_STATUS_MPULOCK) { 546 /* got the lock; move to next state */ 547 ace->fsm_state = ACE_FSM_STATE_WAIT_CFREADY; 548 break; 549 } 550 551 /* wait a bit for the lock */ 552 ace_fsm_yield(ace); 553 break; 554 555 case ACE_FSM_STATE_WAIT_CFREADY: 556 status = ace_in32(ace, ACE_STATUS); 557 if (!(status & ACE_STATUS_RDYFORCFCMD) || 558 (status & ACE_STATUS_CFBSY)) { 559 /* CF card isn't ready; it needs to be polled */ 560 ace_fsm_yield(ace); 561 break; 562 } 563 564 /* Device is ready for command; determine what to do next */ 565 if (ace->id_req_count) 566 ace->fsm_state = ACE_FSM_STATE_IDENTIFY_PREPARE; 567 else 568 ace->fsm_state = ACE_FSM_STATE_REQ_PREPARE; 569 break; 570 571 case ACE_FSM_STATE_IDENTIFY_PREPARE: 572 /* Send identify command */ 573 ace->fsm_task = ACE_TASK_IDENTIFY; 574 ace->data_ptr = ace->cf_id; 575 ace->data_count = ACE_BUF_PER_SECTOR; 576 ace_out(ace, ACE_SECCNTCMD, ACE_SECCNTCMD_IDENTIFY); 577 578 /* As per datasheet, put config controller in reset */ 579 val = ace_in(ace, ACE_CTRL); 580 ace_out(ace, ACE_CTRL, val | ACE_CTRL_CFGRESET); 581 582 /* irq handler takes over from this point; wait for the 583 * transfer to complete */ 584 ace->fsm_state = ACE_FSM_STATE_IDENTIFY_TRANSFER; 585 ace_fsm_yieldirq(ace); 586 break; 587 588 case ACE_FSM_STATE_IDENTIFY_TRANSFER: 589 /* Check that the sysace is ready to receive data */ 590 status = ace_in32(ace, ACE_STATUS); 591 if (status & ACE_STATUS_CFBSY) { 592 dev_dbg(ace->dev, "CFBSY set; t=%i iter=%i dc=%i\n", 593 ace->fsm_task, ace->fsm_iter_num, 594 ace->data_count); 595 ace_fsm_yield(ace); 596 break; 597 } 598 if (!(status & ACE_STATUS_DATABUFRDY)) { 599 ace_fsm_yield(ace); 600 break; 601 } 602 603 /* Transfer the next buffer */ 604 ace->reg_ops->datain(ace); 605 ace->data_count--; 606 607 /* If there are still buffers to be transfers; jump out here */ 608 if (ace->data_count != 0) { 609 ace_fsm_yieldirq(ace); 610 break; 611 } 612 613 /* transfer finished; kick state machine */ 614 dev_dbg(ace->dev, "identify finished\n"); 615 ace->fsm_state = ACE_FSM_STATE_IDENTIFY_COMPLETE; 616 break; 617 618 case ACE_FSM_STATE_IDENTIFY_COMPLETE: 619 ace_fix_driveid(ace->cf_id); 620 ace_dump_mem(ace->cf_id, 512); /* Debug: Dump out disk ID */ 621 622 if (ace->data_result) { 623 /* Error occured, disable the disk */ 624 ace->media_change = 1; 625 set_capacity(ace->gd, 0); 626 dev_err(ace->dev, "error fetching CF id (%i)\n", 627 ace->data_result); 628 } else { 629 ace->media_change = 0; 630 631 /* Record disk parameters */ 632 set_capacity(ace->gd, 633 ata_id_u32(ace->cf_id, ATA_ID_LBA_CAPACITY)); 634 dev_info(ace->dev, "capacity: %i sectors\n", 635 ata_id_u32(ace->cf_id, ATA_ID_LBA_CAPACITY)); 636 } 637 638 /* We're done, drop to IDLE state and notify waiters */ 639 ace->fsm_state = ACE_FSM_STATE_IDLE; 640 ace->id_result = ace->data_result; 641 while (ace->id_req_count) { 642 complete(&ace->id_completion); 643 ace->id_req_count--; 644 } 645 break; 646 647 case ACE_FSM_STATE_REQ_PREPARE: 648 req = ace_get_next_request(ace->queue); 649 if (!req) { 650 ace->fsm_state = ACE_FSM_STATE_IDLE; 651 break; 652 } 653 blk_start_request(req); 654 655 /* Okay, it's a data request, set it up for transfer */ 656 dev_dbg(ace->dev, 657 "request: sec=%llx hcnt=%x, ccnt=%x, dir=%i\n", 658 (unsigned long long)blk_rq_pos(req), 659 blk_rq_sectors(req), blk_rq_cur_sectors(req), 660 rq_data_dir(req)); 661 662 ace->req = req; 663 ace->data_ptr = req->buffer; 664 ace->data_count = blk_rq_cur_sectors(req) * ACE_BUF_PER_SECTOR; 665 ace_out32(ace, ACE_MPULBA, blk_rq_pos(req) & 0x0FFFFFFF); 666 667 count = blk_rq_sectors(req); 668 if (rq_data_dir(req)) { 669 /* Kick off write request */ 670 dev_dbg(ace->dev, "write data\n"); 671 ace->fsm_task = ACE_TASK_WRITE; 672 ace_out(ace, ACE_SECCNTCMD, 673 count | ACE_SECCNTCMD_WRITE_DATA); 674 } else { 675 /* Kick off read request */ 676 dev_dbg(ace->dev, "read data\n"); 677 ace->fsm_task = ACE_TASK_READ; 678 ace_out(ace, ACE_SECCNTCMD, 679 count | ACE_SECCNTCMD_READ_DATA); 680 } 681 682 /* As per datasheet, put config controller in reset */ 683 val = ace_in(ace, ACE_CTRL); 684 ace_out(ace, ACE_CTRL, val | ACE_CTRL_CFGRESET); 685 686 /* Move to the transfer state. The systemace will raise 687 * an interrupt once there is something to do 688 */ 689 ace->fsm_state = ACE_FSM_STATE_REQ_TRANSFER; 690 if (ace->fsm_task == ACE_TASK_READ) 691 ace_fsm_yieldirq(ace); /* wait for data ready */ 692 break; 693 694 case ACE_FSM_STATE_REQ_TRANSFER: 695 /* Check that the sysace is ready to receive data */ 696 status = ace_in32(ace, ACE_STATUS); 697 if (status & ACE_STATUS_CFBSY) { 698 dev_dbg(ace->dev, 699 "CFBSY set; t=%i iter=%i c=%i dc=%i irq=%i\n", 700 ace->fsm_task, ace->fsm_iter_num, 701 blk_rq_cur_sectors(ace->req) * 16, 702 ace->data_count, ace->in_irq); 703 ace_fsm_yield(ace); /* need to poll CFBSY bit */ 704 break; 705 } 706 if (!(status & ACE_STATUS_DATABUFRDY)) { 707 dev_dbg(ace->dev, 708 "DATABUF not set; t=%i iter=%i c=%i dc=%i irq=%i\n", 709 ace->fsm_task, ace->fsm_iter_num, 710 blk_rq_cur_sectors(ace->req) * 16, 711 ace->data_count, ace->in_irq); 712 ace_fsm_yieldirq(ace); 713 break; 714 } 715 716 /* Transfer the next buffer */ 717 if (ace->fsm_task == ACE_TASK_WRITE) 718 ace->reg_ops->dataout(ace); 719 else 720 ace->reg_ops->datain(ace); 721 ace->data_count--; 722 723 /* If there are still buffers to be transfers; jump out here */ 724 if (ace->data_count != 0) { 725 ace_fsm_yieldirq(ace); 726 break; 727 } 728 729 /* bio finished; is there another one? */ 730 if (__blk_end_request_cur(ace->req, 0)) { 731 /* dev_dbg(ace->dev, "next block; h=%u c=%u\n", 732 * blk_rq_sectors(ace->req), 733 * blk_rq_cur_sectors(ace->req)); 734 */ 735 ace->data_ptr = ace->req->buffer; 736 ace->data_count = blk_rq_cur_sectors(ace->req) * 16; 737 ace_fsm_yieldirq(ace); 738 break; 739 } 740 741 ace->fsm_state = ACE_FSM_STATE_REQ_COMPLETE; 742 break; 743 744 case ACE_FSM_STATE_REQ_COMPLETE: 745 ace->req = NULL; 746 747 /* Finished request; go to idle state */ 748 ace->fsm_state = ACE_FSM_STATE_IDLE; 749 break; 750 751 default: 752 ace->fsm_state = ACE_FSM_STATE_IDLE; 753 break; 754 } 755} 756 757static void ace_fsm_tasklet(unsigned long data) 758{ 759 struct ace_device *ace = (void *)data; 760 unsigned long flags; 761 762 spin_lock_irqsave(&ace->lock, flags); 763 764 /* Loop over state machine until told to stop */ 765 ace->fsm_continue_flag = 1; 766 while (ace->fsm_continue_flag) 767 ace_fsm_dostate(ace); 768 769 spin_unlock_irqrestore(&ace->lock, flags); 770} 771 772static void ace_stall_timer(unsigned long data) 773{ 774 struct ace_device *ace = (void *)data; 775 unsigned long flags; 776 777 dev_warn(ace->dev, 778 "kicking stalled fsm; state=%i task=%i iter=%i dc=%i\n", 779 ace->fsm_state, ace->fsm_task, ace->fsm_iter_num, 780 ace->data_count); 781 spin_lock_irqsave(&ace->lock, flags); 782 783 /* Rearm the stall timer *before* entering FSM (which may then 784 * delete the timer) */ 785 mod_timer(&ace->stall_timer, jiffies + HZ); 786 787 /* Loop over state machine until told to stop */ 788 ace->fsm_continue_flag = 1; 789 while (ace->fsm_continue_flag) 790 ace_fsm_dostate(ace); 791 792 spin_unlock_irqrestore(&ace->lock, flags); 793} 794 795/* --------------------------------------------------------------------- 796 * Interrupt handling routines 797 */ 798static int ace_interrupt_checkstate(struct ace_device *ace) 799{ 800 u32 sreg = ace_in32(ace, ACE_STATUS); 801 u16 creg = ace_in(ace, ACE_CTRL); 802 803 /* Check for error occurance */ 804 if ((sreg & (ACE_STATUS_CFGERROR | ACE_STATUS_CFCERROR)) && 805 (creg & ACE_CTRL_ERRORIRQ)) { 806 dev_err(ace->dev, "transfer failure\n"); 807 ace_dump_regs(ace); 808 return -EIO; 809 } 810 811 return 0; 812} 813 814static irqreturn_t ace_interrupt(int irq, void *dev_id) 815{ 816 u16 creg; 817 struct ace_device *ace = dev_id; 818 819 /* be safe and get the lock */ 820 spin_lock(&ace->lock); 821 ace->in_irq = 1; 822 823 /* clear the interrupt */ 824 creg = ace_in(ace, ACE_CTRL); 825 ace_out(ace, ACE_CTRL, creg | ACE_CTRL_RESETIRQ); 826 ace_out(ace, ACE_CTRL, creg); 827 828 /* check for IO failures */ 829 if (ace_interrupt_checkstate(ace)) 830 ace->data_result = -EIO; 831 832 if (ace->fsm_task == 0) { 833 dev_err(ace->dev, 834 "spurious irq; stat=%.8x ctrl=%.8x cmd=%.4x\n", 835 ace_in32(ace, ACE_STATUS), ace_in32(ace, ACE_CTRL), 836 ace_in(ace, ACE_SECCNTCMD)); 837 dev_err(ace->dev, "fsm_task=%i fsm_state=%i data_count=%i\n", 838 ace->fsm_task, ace->fsm_state, ace->data_count); 839 } 840 841 /* Loop over state machine until told to stop */ 842 ace->fsm_continue_flag = 1; 843 while (ace->fsm_continue_flag) 844 ace_fsm_dostate(ace); 845 846 /* done with interrupt; drop the lock */ 847 ace->in_irq = 0; 848 spin_unlock(&ace->lock); 849 850 return IRQ_HANDLED; 851} 852 853/* --------------------------------------------------------------------- 854 * Block ops 855 */ 856static void ace_request(struct request_queue * q) 857{ 858 struct request *req; 859 struct ace_device *ace; 860 861 req = ace_get_next_request(q); 862 863 if (req) { 864 ace = req->rq_disk->private_data; 865 tasklet_schedule(&ace->fsm_tasklet); 866 } 867} 868 869static int ace_media_changed(struct gendisk *gd) 870{ 871 struct ace_device *ace = gd->private_data; 872 dev_dbg(ace->dev, "ace_media_changed(): %i\n", ace->media_change); 873 874 return ace->media_change; 875} 876 877static int ace_revalidate_disk(struct gendisk *gd) 878{ 879 struct ace_device *ace = gd->private_data; 880 unsigned long flags; 881 882 dev_dbg(ace->dev, "ace_revalidate_disk()\n"); 883 884 if (ace->media_change) { 885 dev_dbg(ace->dev, "requesting cf id and scheduling tasklet\n"); 886 887 spin_lock_irqsave(&ace->lock, flags); 888 ace->id_req_count++; 889 spin_unlock_irqrestore(&ace->lock, flags); 890 891 tasklet_schedule(&ace->fsm_tasklet); 892 wait_for_completion(&ace->id_completion); 893 } 894 895 dev_dbg(ace->dev, "revalidate complete\n"); 896 return ace->id_result; 897} 898 899static int ace_open(struct block_device *bdev, fmode_t mode) 900{ 901 struct ace_device *ace = bdev->bd_disk->private_data; 902 unsigned long flags; 903 904 dev_dbg(ace->dev, "ace_open() users=%i\n", ace->users + 1); 905 906 lock_kernel(); 907 spin_lock_irqsave(&ace->lock, flags); 908 ace->users++; 909 spin_unlock_irqrestore(&ace->lock, flags); 910 911 check_disk_change(bdev); 912 unlock_kernel(); 913 914 return 0; 915} 916 917static int ace_release(struct gendisk *disk, fmode_t mode) 918{ 919 struct ace_device *ace = disk->private_data; 920 unsigned long flags; 921 u16 val; 922 923 dev_dbg(ace->dev, "ace_release() users=%i\n", ace->users - 1); 924 925 lock_kernel(); 926 spin_lock_irqsave(&ace->lock, flags); 927 ace->users--; 928 if (ace->users == 0) { 929 val = ace_in(ace, ACE_CTRL); 930 ace_out(ace, ACE_CTRL, val & ~ACE_CTRL_LOCKREQ); 931 } 932 spin_unlock_irqrestore(&ace->lock, flags); 933 unlock_kernel(); 934 return 0; 935} 936 937static int ace_getgeo(struct block_device *bdev, struct hd_geometry *geo) 938{ 939 struct ace_device *ace = bdev->bd_disk->private_data; 940 u16 *cf_id = ace->cf_id; 941 942 dev_dbg(ace->dev, "ace_getgeo()\n"); 943 944 geo->heads = cf_id[ATA_ID_HEADS]; 945 geo->sectors = cf_id[ATA_ID_SECTORS]; 946 geo->cylinders = cf_id[ATA_ID_CYLS]; 947 948 return 0; 949} 950 951static const struct block_device_operations ace_fops = { 952 .owner = THIS_MODULE, 953 .open = ace_open, 954 .release = ace_release, 955 .media_changed = ace_media_changed, 956 .revalidate_disk = ace_revalidate_disk, 957 .getgeo = ace_getgeo, 958}; 959 960/* -------------------------------------------------------------------- 961 * SystemACE device setup/teardown code 962 */ 963static int __devinit ace_setup(struct ace_device *ace) 964{ 965 u16 version; 966 u16 val; 967 int rc; 968 969 dev_dbg(ace->dev, "ace_setup(ace=0x%p)\n", ace); 970 dev_dbg(ace->dev, "physaddr=0x%llx irq=%i\n", 971 (unsigned long long)ace->physaddr, ace->irq); 972 973 spin_lock_init(&ace->lock); 974 init_completion(&ace->id_completion); 975 976 /* 977 * Map the device 978 */ 979 ace->baseaddr = ioremap(ace->physaddr, 0x80); 980 if (!ace->baseaddr) 981 goto err_ioremap; 982 983 /* 984 * Initialize the state machine tasklet and stall timer 985 */ 986 tasklet_init(&ace->fsm_tasklet, ace_fsm_tasklet, (unsigned long)ace); 987 setup_timer(&ace->stall_timer, ace_stall_timer, (unsigned long)ace); 988 989 /* 990 * Initialize the request queue 991 */ 992 ace->queue = blk_init_queue(ace_request, &ace->lock); 993 if (ace->queue == NULL) 994 goto err_blk_initq; 995 blk_queue_logical_block_size(ace->queue, 512); 996 997 /* 998 * Allocate and initialize GD structure 999 */ 1000 ace->gd = alloc_disk(ACE_NUM_MINORS); 1001 if (!ace->gd) 1002 goto err_alloc_disk; 1003 1004 ace->gd->major = ace_major; 1005 ace->gd->first_minor = ace->id * ACE_NUM_MINORS; 1006 ace->gd->fops = &ace_fops; 1007 ace->gd->queue = ace->queue; 1008 ace->gd->private_data = ace; 1009 snprintf(ace->gd->disk_name, 32, "xs%c", ace->id + 'a'); 1010 1011 /* set bus width */ 1012 if (ace->bus_width == ACE_BUS_WIDTH_16) { 1013 /* 0x0101 should work regardless of endianess */ 1014 ace_out_le16(ace, ACE_BUSMODE, 0x0101); 1015 1016 /* read it back to determine endianess */ 1017 if (ace_in_le16(ace, ACE_BUSMODE) == 0x0001) 1018 ace->reg_ops = &ace_reg_le16_ops; 1019 else 1020 ace->reg_ops = &ace_reg_be16_ops; 1021 } else { 1022 ace_out_8(ace, ACE_BUSMODE, 0x00); 1023 ace->reg_ops = &ace_reg_8_ops; 1024 } 1025 1026 /* Make sure version register is sane */ 1027 version = ace_in(ace, ACE_VERSION); 1028 if ((version == 0) || (version == 0xFFFF)) 1029 goto err_read; 1030 1031 /* Put sysace in a sane state by clearing most control reg bits */ 1032 ace_out(ace, ACE_CTRL, ACE_CTRL_FORCECFGMODE | 1033 ACE_CTRL_DATABUFRDYIRQ | ACE_CTRL_ERRORIRQ); 1034 1035 /* Now we can hook up the irq handler */ 1036 if (ace->irq != NO_IRQ) { 1037 rc = request_irq(ace->irq, ace_interrupt, 0, "systemace", ace); 1038 if (rc) { 1039 /* Failure - fall back to polled mode */ 1040 dev_err(ace->dev, "request_irq failed\n"); 1041 ace->irq = NO_IRQ; 1042 } 1043 } 1044 1045 /* Enable interrupts */ 1046 val = ace_in(ace, ACE_CTRL); 1047 val |= ACE_CTRL_DATABUFRDYIRQ | ACE_CTRL_ERRORIRQ; 1048 ace_out(ace, ACE_CTRL, val); 1049 1050 /* Print the identification */ 1051 dev_info(ace->dev, "Xilinx SystemACE revision %i.%i.%i\n", 1052 (version >> 12) & 0xf, (version >> 8) & 0x0f, version & 0xff); 1053 dev_dbg(ace->dev, "physaddr 0x%llx, mapped to 0x%p, irq=%i\n", 1054 (unsigned long long) ace->physaddr, ace->baseaddr, ace->irq); 1055 1056 ace->media_change = 1; 1057 ace_revalidate_disk(ace->gd); 1058 1059 /* Make the sysace device 'live' */ 1060 add_disk(ace->gd); 1061 1062 return 0; 1063 1064err_read: 1065 put_disk(ace->gd); 1066err_alloc_disk: 1067 blk_cleanup_queue(ace->queue); 1068err_blk_initq: 1069 iounmap(ace->baseaddr); 1070err_ioremap: 1071 dev_info(ace->dev, "xsysace: error initializing device at 0x%llx\n", 1072 (unsigned long long) ace->physaddr); 1073 return -ENOMEM; 1074} 1075 1076static void __devexit ace_teardown(struct ace_device *ace) 1077{ 1078 if (ace->gd) { 1079 del_gendisk(ace->gd); 1080 put_disk(ace->gd); 1081 } 1082 1083 if (ace->queue) 1084 blk_cleanup_queue(ace->queue); 1085 1086 tasklet_kill(&ace->fsm_tasklet); 1087 1088 if (ace->irq != NO_IRQ) 1089 free_irq(ace->irq, ace); 1090 1091 iounmap(ace->baseaddr); 1092} 1093 1094static int __devinit 1095ace_alloc(struct device *dev, int id, resource_size_t physaddr, 1096 int irq, int bus_width) 1097{ 1098 struct ace_device *ace; 1099 int rc; 1100 dev_dbg(dev, "ace_alloc(%p)\n", dev); 1101 1102 if (!physaddr) { 1103 rc = -ENODEV; 1104 goto err_noreg; 1105 } 1106 1107 /* Allocate and initialize the ace device structure */ 1108 ace = kzalloc(sizeof(struct ace_device), GFP_KERNEL); 1109 if (!ace) { 1110 rc = -ENOMEM; 1111 goto err_alloc; 1112 } 1113 1114 ace->dev = dev; 1115 ace->id = id; 1116 ace->physaddr = physaddr; 1117 ace->irq = irq; 1118 ace->bus_width = bus_width; 1119 1120 /* Call the setup code */ 1121 rc = ace_setup(ace); 1122 if (rc) 1123 goto err_setup; 1124 1125 dev_set_drvdata(dev, ace); 1126 return 0; 1127 1128err_setup: 1129 dev_set_drvdata(dev, NULL); 1130 kfree(ace); 1131err_alloc: 1132err_noreg: 1133 dev_err(dev, "could not initialize device, err=%i\n", rc); 1134 return rc; 1135} 1136 1137static void __devexit ace_free(struct device *dev) 1138{ 1139 struct ace_device *ace = dev_get_drvdata(dev); 1140 dev_dbg(dev, "ace_free(%p)\n", dev); 1141 1142 if (ace) { 1143 ace_teardown(ace); 1144 dev_set_drvdata(dev, NULL); 1145 kfree(ace); 1146 } 1147} 1148 1149/* --------------------------------------------------------------------- 1150 * Platform Bus Support 1151 */ 1152 1153static int __devinit ace_probe(struct platform_device *dev) 1154{ 1155 resource_size_t physaddr = 0; 1156 int bus_width = ACE_BUS_WIDTH_16; 1157 int id = dev->id; 1158 int irq = NO_IRQ; 1159 int i; 1160 1161 dev_dbg(&dev->dev, "ace_probe(%p)\n", dev); 1162 1163 for (i = 0; i < dev->num_resources; i++) { 1164 if (dev->resource[i].flags & IORESOURCE_MEM) 1165 physaddr = dev->resource[i].start; 1166 if (dev->resource[i].flags & IORESOURCE_IRQ) 1167 irq = dev->resource[i].start; 1168 } 1169 1170 /* Call the bus-independant setup code */ 1171 return ace_alloc(&dev->dev, id, physaddr, irq, bus_width); 1172} 1173 1174/* 1175 * Platform bus remove() method 1176 */ 1177static int __devexit ace_remove(struct platform_device *dev) 1178{ 1179 ace_free(&dev->dev); 1180 return 0; 1181} 1182 1183static struct platform_driver ace_platform_driver = { 1184 .probe = ace_probe, 1185 .remove = __devexit_p(ace_remove), 1186 .driver = { 1187 .owner = THIS_MODULE, 1188 .name = "xsysace", 1189 }, 1190}; 1191 1192/* --------------------------------------------------------------------- 1193 * OF_Platform Bus Support 1194 */ 1195 1196#if defined(CONFIG_OF) 1197static int __devinit 1198ace_of_probe(struct platform_device *op, const struct of_device_id *match) 1199{ 1200 struct resource res; 1201 resource_size_t physaddr; 1202 const u32 *id; 1203 int irq, bus_width, rc; 1204 1205 dev_dbg(&op->dev, "ace_of_probe(%p, %p)\n", op, match); 1206 1207 /* device id */ 1208 id = of_get_property(op->dev.of_node, "port-number", NULL); 1209 1210 /* physaddr */ 1211 rc = of_address_to_resource(op->dev.of_node, 0, &res); 1212 if (rc) { 1213 dev_err(&op->dev, "invalid address\n"); 1214 return rc; 1215 } 1216 physaddr = res.start; 1217 1218 /* irq */ 1219 irq = irq_of_parse_and_map(op->dev.of_node, 0); 1220 1221 /* bus width */ 1222 bus_width = ACE_BUS_WIDTH_16; 1223 if (of_find_property(op->dev.of_node, "8-bit", NULL)) 1224 bus_width = ACE_BUS_WIDTH_8; 1225 1226 /* Call the bus-independant setup code */ 1227 return ace_alloc(&op->dev, id ? *id : 0, physaddr, irq, bus_width); 1228} 1229 1230static int __devexit ace_of_remove(struct platform_device *op) 1231{ 1232 ace_free(&op->dev); 1233 return 0; 1234} 1235 1236/* Match table for of_platform binding */ 1237static const struct of_device_id ace_of_match[] __devinitconst = { 1238 { .compatible = "xlnx,opb-sysace-1.00.b", }, 1239 { .compatible = "xlnx,opb-sysace-1.00.c", }, 1240 { .compatible = "xlnx,xps-sysace-1.00.a", }, 1241 { .compatible = "xlnx,sysace", }, 1242 {}, 1243}; 1244MODULE_DEVICE_TABLE(of, ace_of_match); 1245 1246static struct of_platform_driver ace_of_driver = { 1247 .probe = ace_of_probe, 1248 .remove = __devexit_p(ace_of_remove), 1249 .driver = { 1250 .name = "xsysace", 1251 .owner = THIS_MODULE, 1252 .of_match_table = ace_of_match, 1253 }, 1254}; 1255 1256/* Registration helpers to keep the number of #ifdefs to a minimum */ 1257static inline int __init ace_of_register(void) 1258{ 1259 pr_debug("xsysace: registering OF binding\n"); 1260 return of_register_platform_driver(&ace_of_driver); 1261} 1262 1263static inline void __exit ace_of_unregister(void) 1264{ 1265 of_unregister_platform_driver(&ace_of_driver); 1266} 1267#else /* CONFIG_OF */ 1268/* CONFIG_OF not enabled; do nothing helpers */ 1269static inline int __init ace_of_register(void) { return 0; } 1270static inline void __exit ace_of_unregister(void) { } 1271#endif /* CONFIG_OF */ 1272 1273/* --------------------------------------------------------------------- 1274 * Module init/exit routines 1275 */ 1276static int __init ace_init(void) 1277{ 1278 int rc; 1279 1280 ace_major = register_blkdev(ace_major, "xsysace"); 1281 if (ace_major <= 0) { 1282 rc = -ENOMEM; 1283 goto err_blk; 1284 } 1285 1286 rc = ace_of_register(); 1287 if (rc) 1288 goto err_of; 1289 1290 pr_debug("xsysace: registering platform binding\n"); 1291 rc = platform_driver_register(&ace_platform_driver); 1292 if (rc) 1293 goto err_plat; 1294 1295 pr_info("Xilinx SystemACE device driver, major=%i\n", ace_major); 1296 return 0; 1297 1298err_plat: 1299 ace_of_unregister(); 1300err_of: 1301 unregister_blkdev(ace_major, "xsysace"); 1302err_blk: 1303 printk(KERN_ERR "xsysace: registration failed; err=%i\n", rc); 1304 return rc; 1305} 1306 1307static void __exit ace_exit(void) 1308{ 1309 pr_debug("Unregistering Xilinx SystemACE driver\n"); 1310 platform_driver_unregister(&ace_platform_driver); 1311 ace_of_unregister(); 1312 unregister_blkdev(ace_major, "xsysace"); 1313} 1314 1315module_init(ace_init); 1316module_exit(ace_exit); 1317