1/* 2 * nicstar.c 3 * 4 * Device driver supporting CBR for IDT 77201/77211 "NICStAR" based cards. 5 * 6 * IMPORTANT: The included file nicstarmac.c was NOT WRITTEN BY ME. 7 * It was taken from the frle-0.22 device driver. 8 * As the file doesn't have a copyright notice, in the file 9 * nicstarmac.copyright I put the copyright notice from the 10 * frle-0.22 device driver. 11 * Some code is based on the nicstar driver by M. Welsh. 12 * 13 * Author: Rui Prior (rprior@inescn.pt) 14 * PowerPC support by Jay Talbott (jay_talbott@mcg.mot.com) April 1999 15 * 16 * 17 * (C) INESC 1999 18 */ 19 20/* 21 * IMPORTANT INFORMATION 22 * 23 * There are currently three types of spinlocks: 24 * 25 * 1 - Per card interrupt spinlock (to protect structures and such) 26 * 2 - Per SCQ scq spinlock 27 * 3 - Per card resource spinlock (to access registers, etc.) 28 * 29 * These must NEVER be grabbed in reverse order. 30 * 31 */ 32 33/* Header files */ 34 35#include <linux/module.h> 36#include <linux/kernel.h> 37#include <linux/skbuff.h> 38#include <linux/atmdev.h> 39#include <linux/atm.h> 40#include <linux/pci.h> 41#include <linux/dma-mapping.h> 42#include <linux/types.h> 43#include <linux/string.h> 44#include <linux/delay.h> 45#include <linux/init.h> 46#include <linux/sched.h> 47#include <linux/timer.h> 48#include <linux/interrupt.h> 49#include <linux/bitops.h> 50#include <linux/slab.h> 51#include <linux/idr.h> 52#include <asm/io.h> 53#include <asm/uaccess.h> 54#include <asm/atomic.h> 55#include "nicstar.h" 56#ifdef CONFIG_ATM_NICSTAR_USE_SUNI 57#include "suni.h" 58#endif /* CONFIG_ATM_NICSTAR_USE_SUNI */ 59#ifdef CONFIG_ATM_NICSTAR_USE_IDT77105 60#include "idt77105.h" 61#endif /* CONFIG_ATM_NICSTAR_USE_IDT77105 */ 62 63/* Additional code */ 64 65#include "nicstarmac.c" 66 67/* Configurable parameters */ 68 69#undef PHY_LOOPBACK 70#undef TX_DEBUG 71#undef RX_DEBUG 72#undef GENERAL_DEBUG 73#undef EXTRA_DEBUG 74 75#undef NS_USE_DESTRUCTORS /* For now keep this undefined unless you know 76 you're going to use only raw ATM */ 77 78/* Do not touch these */ 79 80#ifdef TX_DEBUG 81#define TXPRINTK(args...) printk(args) 82#else 83#define TXPRINTK(args...) 84#endif /* TX_DEBUG */ 85 86#ifdef RX_DEBUG 87#define RXPRINTK(args...) printk(args) 88#else 89#define RXPRINTK(args...) 90#endif /* RX_DEBUG */ 91 92#ifdef GENERAL_DEBUG 93#define PRINTK(args...) printk(args) 94#else 95#define PRINTK(args...) 96#endif /* GENERAL_DEBUG */ 97 98#ifdef EXTRA_DEBUG 99#define XPRINTK(args...) printk(args) 100#else 101#define XPRINTK(args...) 102#endif /* EXTRA_DEBUG */ 103 104/* Macros */ 105 106#define CMD_BUSY(card) (readl((card)->membase + STAT) & NS_STAT_CMDBZ) 107 108#define NS_DELAY mdelay(1) 109 110#define PTR_DIFF(a, b) ((u32)((unsigned long)(a) - (unsigned long)(b))) 111 112#ifndef ATM_SKB 113#define ATM_SKB(s) (&(s)->atm) 114#endif 115 116#define scq_virt_to_bus(scq, p) \ 117 (scq->dma + ((unsigned long)(p) - (unsigned long)(scq)->org)) 118 119/* Function declarations */ 120 121static u32 ns_read_sram(ns_dev * card, u32 sram_address); 122static void ns_write_sram(ns_dev * card, u32 sram_address, u32 * value, 123 int count); 124static int __devinit ns_init_card(int i, struct pci_dev *pcidev); 125static void __devinit ns_init_card_error(ns_dev * card, int error); 126static scq_info *get_scq(ns_dev *card, int size, u32 scd); 127static void free_scq(ns_dev *card, scq_info * scq, struct atm_vcc *vcc); 128static void push_rxbufs(ns_dev *, struct sk_buff *); 129static irqreturn_t ns_irq_handler(int irq, void *dev_id); 130static int ns_open(struct atm_vcc *vcc); 131static void ns_close(struct atm_vcc *vcc); 132static void fill_tst(ns_dev * card, int n, vc_map * vc); 133static int ns_send(struct atm_vcc *vcc, struct sk_buff *skb); 134static int push_scqe(ns_dev * card, vc_map * vc, scq_info * scq, ns_scqe * tbd, 135 struct sk_buff *skb); 136static void process_tsq(ns_dev * card); 137static void drain_scq(ns_dev * card, scq_info * scq, int pos); 138static void process_rsq(ns_dev * card); 139static void dequeue_rx(ns_dev * card, ns_rsqe * rsqe); 140#ifdef NS_USE_DESTRUCTORS 141static void ns_sb_destructor(struct sk_buff *sb); 142static void ns_lb_destructor(struct sk_buff *lb); 143static void ns_hb_destructor(struct sk_buff *hb); 144#endif /* NS_USE_DESTRUCTORS */ 145static void recycle_rx_buf(ns_dev * card, struct sk_buff *skb); 146static void recycle_iovec_rx_bufs(ns_dev * card, struct iovec *iov, int count); 147static void recycle_iov_buf(ns_dev * card, struct sk_buff *iovb); 148static void dequeue_sm_buf(ns_dev * card, struct sk_buff *sb); 149static void dequeue_lg_buf(ns_dev * card, struct sk_buff *lb); 150static int ns_proc_read(struct atm_dev *dev, loff_t * pos, char *page); 151static int ns_ioctl(struct atm_dev *dev, unsigned int cmd, void __user * arg); 152#ifdef EXTRA_DEBUG 153static void which_list(ns_dev * card, struct sk_buff *skb); 154#endif 155static void ns_poll(unsigned long arg); 156static int ns_parse_mac(char *mac, unsigned char *esi); 157static void ns_phy_put(struct atm_dev *dev, unsigned char value, 158 unsigned long addr); 159static unsigned char ns_phy_get(struct atm_dev *dev, unsigned long addr); 160 161/* Global variables */ 162 163static struct ns_dev *cards[NS_MAX_CARDS]; 164static unsigned num_cards; 165static struct atmdev_ops atm_ops = { 166 .open = ns_open, 167 .close = ns_close, 168 .ioctl = ns_ioctl, 169 .send = ns_send, 170 .phy_put = ns_phy_put, 171 .phy_get = ns_phy_get, 172 .proc_read = ns_proc_read, 173 .owner = THIS_MODULE, 174}; 175 176static struct timer_list ns_timer; 177static char *mac[NS_MAX_CARDS]; 178module_param_array(mac, charp, NULL, 0); 179MODULE_LICENSE("GPL"); 180 181/* Functions */ 182 183static int __devinit nicstar_init_one(struct pci_dev *pcidev, 184 const struct pci_device_id *ent) 185{ 186 static int index = -1; 187 unsigned int error; 188 189 index++; 190 cards[index] = NULL; 191 192 error = ns_init_card(index, pcidev); 193 if (error) { 194 cards[index--] = NULL; /* don't increment index */ 195 goto err_out; 196 } 197 198 return 0; 199err_out: 200 return -ENODEV; 201} 202 203static void __devexit nicstar_remove_one(struct pci_dev *pcidev) 204{ 205 int i, j; 206 ns_dev *card = pci_get_drvdata(pcidev); 207 struct sk_buff *hb; 208 struct sk_buff *iovb; 209 struct sk_buff *lb; 210 struct sk_buff *sb; 211 212 i = card->index; 213 214 if (cards[i] == NULL) 215 return; 216 217 if (card->atmdev->phy && card->atmdev->phy->stop) 218 card->atmdev->phy->stop(card->atmdev); 219 220 /* Stop everything */ 221 writel(0x00000000, card->membase + CFG); 222 223 /* De-register device */ 224 atm_dev_deregister(card->atmdev); 225 226 /* Disable PCI device */ 227 pci_disable_device(pcidev); 228 229 /* Free up resources */ 230 j = 0; 231 PRINTK("nicstar%d: freeing %d huge buffers.\n", i, card->hbpool.count); 232 while ((hb = skb_dequeue(&card->hbpool.queue)) != NULL) { 233 dev_kfree_skb_any(hb); 234 j++; 235 } 236 PRINTK("nicstar%d: %d huge buffers freed.\n", i, j); 237 j = 0; 238 PRINTK("nicstar%d: freeing %d iovec buffers.\n", i, 239 card->iovpool.count); 240 while ((iovb = skb_dequeue(&card->iovpool.queue)) != NULL) { 241 dev_kfree_skb_any(iovb); 242 j++; 243 } 244 PRINTK("nicstar%d: %d iovec buffers freed.\n", i, j); 245 while ((lb = skb_dequeue(&card->lbpool.queue)) != NULL) 246 dev_kfree_skb_any(lb); 247 while ((sb = skb_dequeue(&card->sbpool.queue)) != NULL) 248 dev_kfree_skb_any(sb); 249 free_scq(card, card->scq0, NULL); 250 for (j = 0; j < NS_FRSCD_NUM; j++) { 251 if (card->scd2vc[j] != NULL) 252 free_scq(card, card->scd2vc[j]->scq, card->scd2vc[j]->tx_vcc); 253 } 254 idr_remove_all(&card->idr); 255 idr_destroy(&card->idr); 256 pci_free_consistent(card->pcidev, NS_RSQSIZE + NS_RSQ_ALIGNMENT, 257 card->rsq.org, card->rsq.dma); 258 pci_free_consistent(card->pcidev, NS_TSQSIZE + NS_TSQ_ALIGNMENT, 259 card->tsq.org, card->tsq.dma); 260 free_irq(card->pcidev->irq, card); 261 iounmap(card->membase); 262 kfree(card); 263} 264 265static struct pci_device_id nicstar_pci_tbl[] __devinitdata = { 266 { PCI_VDEVICE(IDT, PCI_DEVICE_ID_IDT_IDT77201), 0 }, 267 {0,} /* terminate list */ 268}; 269 270MODULE_DEVICE_TABLE(pci, nicstar_pci_tbl); 271 272static struct pci_driver nicstar_driver = { 273 .name = "nicstar", 274 .id_table = nicstar_pci_tbl, 275 .probe = nicstar_init_one, 276 .remove = __devexit_p(nicstar_remove_one), 277}; 278 279static int __init nicstar_init(void) 280{ 281 unsigned error = 0; /* Initialized to remove compile warning */ 282 283 XPRINTK("nicstar: nicstar_init() called.\n"); 284 285 error = pci_register_driver(&nicstar_driver); 286 287 TXPRINTK("nicstar: TX debug enabled.\n"); 288 RXPRINTK("nicstar: RX debug enabled.\n"); 289 PRINTK("nicstar: General debug enabled.\n"); 290#ifdef PHY_LOOPBACK 291 printk("nicstar: using PHY loopback.\n"); 292#endif /* PHY_LOOPBACK */ 293 XPRINTK("nicstar: nicstar_init() returned.\n"); 294 295 if (!error) { 296 init_timer(&ns_timer); 297 ns_timer.expires = jiffies + NS_POLL_PERIOD; 298 ns_timer.data = 0UL; 299 ns_timer.function = ns_poll; 300 add_timer(&ns_timer); 301 } 302 303 return error; 304} 305 306static void __exit nicstar_cleanup(void) 307{ 308 XPRINTK("nicstar: nicstar_cleanup() called.\n"); 309 310 del_timer(&ns_timer); 311 312 pci_unregister_driver(&nicstar_driver); 313 314 XPRINTK("nicstar: nicstar_cleanup() returned.\n"); 315} 316 317static u32 ns_read_sram(ns_dev * card, u32 sram_address) 318{ 319 unsigned long flags; 320 u32 data; 321 sram_address <<= 2; 322 sram_address &= 0x0007FFFC; /* address must be dword aligned */ 323 sram_address |= 0x50000000; /* SRAM read command */ 324 spin_lock_irqsave(&card->res_lock, flags); 325 while (CMD_BUSY(card)) ; 326 writel(sram_address, card->membase + CMD); 327 while (CMD_BUSY(card)) ; 328 data = readl(card->membase + DR0); 329 spin_unlock_irqrestore(&card->res_lock, flags); 330 return data; 331} 332 333static void ns_write_sram(ns_dev * card, u32 sram_address, u32 * value, 334 int count) 335{ 336 unsigned long flags; 337 int i, c; 338 count--; /* count range now is 0..3 instead of 1..4 */ 339 c = count; 340 c <<= 2; /* to use increments of 4 */ 341 spin_lock_irqsave(&card->res_lock, flags); 342 while (CMD_BUSY(card)) ; 343 for (i = 0; i <= c; i += 4) 344 writel(*(value++), card->membase + i); 345 /* Note: DR# registers are the first 4 dwords in nicstar's memspace, 346 so card->membase + DR0 == card->membase */ 347 sram_address <<= 2; 348 sram_address &= 0x0007FFFC; 349 sram_address |= (0x40000000 | count); 350 writel(sram_address, card->membase + CMD); 351 spin_unlock_irqrestore(&card->res_lock, flags); 352} 353 354static int __devinit ns_init_card(int i, struct pci_dev *pcidev) 355{ 356 int j; 357 struct ns_dev *card = NULL; 358 unsigned char pci_latency; 359 unsigned error; 360 u32 data; 361 u32 u32d[4]; 362 u32 ns_cfg_rctsize; 363 int bcount; 364 unsigned long membase; 365 366 error = 0; 367 368 if (pci_enable_device(pcidev)) { 369 printk("nicstar%d: can't enable PCI device\n", i); 370 error = 2; 371 ns_init_card_error(card, error); 372 return error; 373 } 374 if ((pci_set_dma_mask(pcidev, DMA_BIT_MASK(32)) != 0) || 375 (pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(32)) != 0)) { 376 printk(KERN_WARNING 377 "nicstar%d: No suitable DMA available.\n", i); 378 error = 2; 379 ns_init_card_error(card, error); 380 return error; 381 } 382 383 if ((card = kmalloc(sizeof(ns_dev), GFP_KERNEL)) == NULL) { 384 printk 385 ("nicstar%d: can't allocate memory for device structure.\n", 386 i); 387 error = 2; 388 ns_init_card_error(card, error); 389 return error; 390 } 391 cards[i] = card; 392 spin_lock_init(&card->int_lock); 393 spin_lock_init(&card->res_lock); 394 395 pci_set_drvdata(pcidev, card); 396 397 card->index = i; 398 card->atmdev = NULL; 399 card->pcidev = pcidev; 400 membase = pci_resource_start(pcidev, 1); 401 card->membase = ioremap(membase, NS_IOREMAP_SIZE); 402 if (!card->membase) { 403 printk("nicstar%d: can't ioremap() membase.\n", i); 404 error = 3; 405 ns_init_card_error(card, error); 406 return error; 407 } 408 PRINTK("nicstar%d: membase at 0x%p.\n", i, card->membase); 409 410 pci_set_master(pcidev); 411 412 if (pci_read_config_byte(pcidev, PCI_LATENCY_TIMER, &pci_latency) != 0) { 413 printk("nicstar%d: can't read PCI latency timer.\n", i); 414 error = 6; 415 ns_init_card_error(card, error); 416 return error; 417 } 418#ifdef NS_PCI_LATENCY 419 if (pci_latency < NS_PCI_LATENCY) { 420 PRINTK("nicstar%d: setting PCI latency timer to %d.\n", i, 421 NS_PCI_LATENCY); 422 for (j = 1; j < 4; j++) { 423 if (pci_write_config_byte 424 (pcidev, PCI_LATENCY_TIMER, NS_PCI_LATENCY) != 0) 425 break; 426 } 427 if (j == 4) { 428 printk 429 ("nicstar%d: can't set PCI latency timer to %d.\n", 430 i, NS_PCI_LATENCY); 431 error = 7; 432 ns_init_card_error(card, error); 433 return error; 434 } 435 } 436#endif /* NS_PCI_LATENCY */ 437 438 /* Clear timer overflow */ 439 data = readl(card->membase + STAT); 440 if (data & NS_STAT_TMROF) 441 writel(NS_STAT_TMROF, card->membase + STAT); 442 443 /* Software reset */ 444 writel(NS_CFG_SWRST, card->membase + CFG); 445 NS_DELAY; 446 writel(0x00000000, card->membase + CFG); 447 448 /* PHY reset */ 449 writel(0x00000008, card->membase + GP); 450 NS_DELAY; 451 writel(0x00000001, card->membase + GP); 452 NS_DELAY; 453 while (CMD_BUSY(card)) ; 454 writel(NS_CMD_WRITE_UTILITY | 0x00000100, card->membase + CMD); /* Sync UTOPIA with SAR clock */ 455 NS_DELAY; 456 457 /* Detect PHY type */ 458 while (CMD_BUSY(card)) ; 459 writel(NS_CMD_READ_UTILITY | 0x00000200, card->membase + CMD); 460 while (CMD_BUSY(card)) ; 461 data = readl(card->membase + DR0); 462 switch (data) { 463 case 0x00000009: 464 printk("nicstar%d: PHY seems to be 25 Mbps.\n", i); 465 card->max_pcr = ATM_25_PCR; 466 while (CMD_BUSY(card)) ; 467 writel(0x00000008, card->membase + DR0); 468 writel(NS_CMD_WRITE_UTILITY | 0x00000200, card->membase + CMD); 469 /* Clear an eventual pending interrupt */ 470 writel(NS_STAT_SFBQF, card->membase + STAT); 471#ifdef PHY_LOOPBACK 472 while (CMD_BUSY(card)) ; 473 writel(0x00000022, card->membase + DR0); 474 writel(NS_CMD_WRITE_UTILITY | 0x00000202, card->membase + CMD); 475#endif /* PHY_LOOPBACK */ 476 break; 477 case 0x00000030: 478 case 0x00000031: 479 printk("nicstar%d: PHY seems to be 155 Mbps.\n", i); 480 card->max_pcr = ATM_OC3_PCR; 481#ifdef PHY_LOOPBACK 482 while (CMD_BUSY(card)) ; 483 writel(0x00000002, card->membase + DR0); 484 writel(NS_CMD_WRITE_UTILITY | 0x00000205, card->membase + CMD); 485#endif /* PHY_LOOPBACK */ 486 break; 487 default: 488 printk("nicstar%d: unknown PHY type (0x%08X).\n", i, data); 489 error = 8; 490 ns_init_card_error(card, error); 491 return error; 492 } 493 writel(0x00000000, card->membase + GP); 494 495 /* Determine SRAM size */ 496 data = 0x76543210; 497 ns_write_sram(card, 0x1C003, &data, 1); 498 data = 0x89ABCDEF; 499 ns_write_sram(card, 0x14003, &data, 1); 500 if (ns_read_sram(card, 0x14003) == 0x89ABCDEF && 501 ns_read_sram(card, 0x1C003) == 0x76543210) 502 card->sram_size = 128; 503 else 504 card->sram_size = 32; 505 PRINTK("nicstar%d: %dK x 32bit SRAM size.\n", i, card->sram_size); 506 507 card->rct_size = NS_MAX_RCTSIZE; 508 509#if (NS_MAX_RCTSIZE == 4096) 510 if (card->sram_size == 128) 511 printk 512 ("nicstar%d: limiting maximum VCI. See NS_MAX_RCTSIZE in nicstar.h\n", 513 i); 514#elif (NS_MAX_RCTSIZE == 16384) 515 if (card->sram_size == 32) { 516 printk 517 ("nicstar%d: wasting memory. See NS_MAX_RCTSIZE in nicstar.h\n", 518 i); 519 card->rct_size = 4096; 520 } 521#else 522#error NS_MAX_RCTSIZE must be either 4096 or 16384 in nicstar.c 523#endif 524 525 card->vpibits = NS_VPIBITS; 526 if (card->rct_size == 4096) 527 card->vcibits = 12 - NS_VPIBITS; 528 else /* card->rct_size == 16384 */ 529 card->vcibits = 14 - NS_VPIBITS; 530 531 /* Initialize the nicstar eeprom/eprom stuff, for the MAC addr */ 532 if (mac[i] == NULL) 533 nicstar_init_eprom(card->membase); 534 535 /* Set the VPI/VCI MSb mask to zero so we can receive OAM cells */ 536 writel(0x00000000, card->membase + VPM); 537 538 /* Initialize TSQ */ 539 card->tsq.org = pci_alloc_consistent(card->pcidev, 540 NS_TSQSIZE + NS_TSQ_ALIGNMENT, 541 &card->tsq.dma); 542 if (card->tsq.org == NULL) { 543 printk("nicstar%d: can't allocate TSQ.\n", i); 544 error = 10; 545 ns_init_card_error(card, error); 546 return error; 547 } 548 card->tsq.base = PTR_ALIGN(card->tsq.org, NS_TSQ_ALIGNMENT); 549 card->tsq.next = card->tsq.base; 550 card->tsq.last = card->tsq.base + (NS_TSQ_NUM_ENTRIES - 1); 551 for (j = 0; j < NS_TSQ_NUM_ENTRIES; j++) 552 ns_tsi_init(card->tsq.base + j); 553 writel(0x00000000, card->membase + TSQH); 554 writel(ALIGN(card->tsq.dma, NS_TSQ_ALIGNMENT), card->membase + TSQB); 555 PRINTK("nicstar%d: TSQ base at 0x%p.\n", i, card->tsq.base); 556 557 /* Initialize RSQ */ 558 card->rsq.org = pci_alloc_consistent(card->pcidev, 559 NS_RSQSIZE + NS_RSQ_ALIGNMENT, 560 &card->rsq.dma); 561 if (card->rsq.org == NULL) { 562 printk("nicstar%d: can't allocate RSQ.\n", i); 563 error = 11; 564 ns_init_card_error(card, error); 565 return error; 566 } 567 card->rsq.base = PTR_ALIGN(card->rsq.org, NS_RSQ_ALIGNMENT); 568 card->rsq.next = card->rsq.base; 569 card->rsq.last = card->rsq.base + (NS_RSQ_NUM_ENTRIES - 1); 570 for (j = 0; j < NS_RSQ_NUM_ENTRIES; j++) 571 ns_rsqe_init(card->rsq.base + j); 572 writel(0x00000000, card->membase + RSQH); 573 writel(ALIGN(card->rsq.dma, NS_RSQ_ALIGNMENT), card->membase + RSQB); 574 PRINTK("nicstar%d: RSQ base at 0x%p.\n", i, card->rsq.base); 575 576 /* Initialize SCQ0, the only VBR SCQ used */ 577 card->scq1 = NULL; 578 card->scq2 = NULL; 579 card->scq0 = get_scq(card, VBR_SCQSIZE, NS_VRSCD0); 580 if (card->scq0 == NULL) { 581 printk("nicstar%d: can't get SCQ0.\n", i); 582 error = 12; 583 ns_init_card_error(card, error); 584 return error; 585 } 586 u32d[0] = scq_virt_to_bus(card->scq0, card->scq0->base); 587 u32d[1] = (u32) 0x00000000; 588 u32d[2] = (u32) 0xffffffff; 589 u32d[3] = (u32) 0x00000000; 590 ns_write_sram(card, NS_VRSCD0, u32d, 4); 591 ns_write_sram(card, NS_VRSCD1, u32d, 4); /* These last two won't be used */ 592 ns_write_sram(card, NS_VRSCD2, u32d, 4); /* but are initialized, just in case... */ 593 card->scq0->scd = NS_VRSCD0; 594 PRINTK("nicstar%d: VBR-SCQ0 base at 0x%p.\n", i, card->scq0->base); 595 596 /* Initialize TSTs */ 597 card->tst_addr = NS_TST0; 598 card->tst_free_entries = NS_TST_NUM_ENTRIES; 599 data = NS_TST_OPCODE_VARIABLE; 600 for (j = 0; j < NS_TST_NUM_ENTRIES; j++) 601 ns_write_sram(card, NS_TST0 + j, &data, 1); 602 data = ns_tste_make(NS_TST_OPCODE_END, NS_TST0); 603 ns_write_sram(card, NS_TST0 + NS_TST_NUM_ENTRIES, &data, 1); 604 for (j = 0; j < NS_TST_NUM_ENTRIES; j++) 605 ns_write_sram(card, NS_TST1 + j, &data, 1); 606 data = ns_tste_make(NS_TST_OPCODE_END, NS_TST1); 607 ns_write_sram(card, NS_TST1 + NS_TST_NUM_ENTRIES, &data, 1); 608 for (j = 0; j < NS_TST_NUM_ENTRIES; j++) 609 card->tste2vc[j] = NULL; 610 writel(NS_TST0 << 2, card->membase + TSTB); 611 612 /* Initialize RCT. AAL type is set on opening the VC. */ 613#ifdef RCQ_SUPPORT 614 u32d[0] = NS_RCTE_RAWCELLINTEN; 615#else 616 u32d[0] = 0x00000000; 617#endif /* RCQ_SUPPORT */ 618 u32d[1] = 0x00000000; 619 u32d[2] = 0x00000000; 620 u32d[3] = 0xFFFFFFFF; 621 for (j = 0; j < card->rct_size; j++) 622 ns_write_sram(card, j * 4, u32d, 4); 623 624 memset(card->vcmap, 0, NS_MAX_RCTSIZE * sizeof(vc_map)); 625 626 for (j = 0; j < NS_FRSCD_NUM; j++) 627 card->scd2vc[j] = NULL; 628 629 /* Initialize buffer levels */ 630 card->sbnr.min = MIN_SB; 631 card->sbnr.init = NUM_SB; 632 card->sbnr.max = MAX_SB; 633 card->lbnr.min = MIN_LB; 634 card->lbnr.init = NUM_LB; 635 card->lbnr.max = MAX_LB; 636 card->iovnr.min = MIN_IOVB; 637 card->iovnr.init = NUM_IOVB; 638 card->iovnr.max = MAX_IOVB; 639 card->hbnr.min = MIN_HB; 640 card->hbnr.init = NUM_HB; 641 card->hbnr.max = MAX_HB; 642 643 card->sm_handle = 0x00000000; 644 card->sm_addr = 0x00000000; 645 card->lg_handle = 0x00000000; 646 card->lg_addr = 0x00000000; 647 648 card->efbie = 1; /* To prevent push_rxbufs from enabling the interrupt */ 649 650 idr_init(&card->idr); 651 652 /* Pre-allocate some huge buffers */ 653 skb_queue_head_init(&card->hbpool.queue); 654 card->hbpool.count = 0; 655 for (j = 0; j < NUM_HB; j++) { 656 struct sk_buff *hb; 657 hb = __dev_alloc_skb(NS_HBUFSIZE, GFP_KERNEL); 658 if (hb == NULL) { 659 printk 660 ("nicstar%d: can't allocate %dth of %d huge buffers.\n", 661 i, j, NUM_HB); 662 error = 13; 663 ns_init_card_error(card, error); 664 return error; 665 } 666 NS_PRV_BUFTYPE(hb) = BUF_NONE; 667 skb_queue_tail(&card->hbpool.queue, hb); 668 card->hbpool.count++; 669 } 670 671 /* Allocate large buffers */ 672 skb_queue_head_init(&card->lbpool.queue); 673 card->lbpool.count = 0; /* Not used */ 674 for (j = 0; j < NUM_LB; j++) { 675 struct sk_buff *lb; 676 lb = __dev_alloc_skb(NS_LGSKBSIZE, GFP_KERNEL); 677 if (lb == NULL) { 678 printk 679 ("nicstar%d: can't allocate %dth of %d large buffers.\n", 680 i, j, NUM_LB); 681 error = 14; 682 ns_init_card_error(card, error); 683 return error; 684 } 685 NS_PRV_BUFTYPE(lb) = BUF_LG; 686 skb_queue_tail(&card->lbpool.queue, lb); 687 skb_reserve(lb, NS_SMBUFSIZE); 688 push_rxbufs(card, lb); 689 /* Due to the implementation of push_rxbufs() this is 1, not 0 */ 690 if (j == 1) { 691 card->rcbuf = lb; 692 card->rawcell = (struct ns_rcqe *) lb->data; 693 card->rawch = NS_PRV_DMA(lb); 694 } 695 } 696 /* Test for strange behaviour which leads to crashes */ 697 if ((bcount = 698 ns_stat_lfbqc_get(readl(card->membase + STAT))) < card->lbnr.min) { 699 printk 700 ("nicstar%d: Strange... Just allocated %d large buffers and lfbqc = %d.\n", 701 i, j, bcount); 702 error = 14; 703 ns_init_card_error(card, error); 704 return error; 705 } 706 707 /* Allocate small buffers */ 708 skb_queue_head_init(&card->sbpool.queue); 709 card->sbpool.count = 0; /* Not used */ 710 for (j = 0; j < NUM_SB; j++) { 711 struct sk_buff *sb; 712 sb = __dev_alloc_skb(NS_SMSKBSIZE, GFP_KERNEL); 713 if (sb == NULL) { 714 printk 715 ("nicstar%d: can't allocate %dth of %d small buffers.\n", 716 i, j, NUM_SB); 717 error = 15; 718 ns_init_card_error(card, error); 719 return error; 720 } 721 NS_PRV_BUFTYPE(sb) = BUF_SM; 722 skb_queue_tail(&card->sbpool.queue, sb); 723 skb_reserve(sb, NS_AAL0_HEADER); 724 push_rxbufs(card, sb); 725 } 726 /* Test for strange behaviour which leads to crashes */ 727 if ((bcount = 728 ns_stat_sfbqc_get(readl(card->membase + STAT))) < card->sbnr.min) { 729 printk 730 ("nicstar%d: Strange... Just allocated %d small buffers and sfbqc = %d.\n", 731 i, j, bcount); 732 error = 15; 733 ns_init_card_error(card, error); 734 return error; 735 } 736 737 /* Allocate iovec buffers */ 738 skb_queue_head_init(&card->iovpool.queue); 739 card->iovpool.count = 0; 740 for (j = 0; j < NUM_IOVB; j++) { 741 struct sk_buff *iovb; 742 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_KERNEL); 743 if (iovb == NULL) { 744 printk 745 ("nicstar%d: can't allocate %dth of %d iovec buffers.\n", 746 i, j, NUM_IOVB); 747 error = 16; 748 ns_init_card_error(card, error); 749 return error; 750 } 751 NS_PRV_BUFTYPE(iovb) = BUF_NONE; 752 skb_queue_tail(&card->iovpool.queue, iovb); 753 card->iovpool.count++; 754 } 755 756 /* Configure NICStAR */ 757 if (card->rct_size == 4096) 758 ns_cfg_rctsize = NS_CFG_RCTSIZE_4096_ENTRIES; 759 else /* (card->rct_size == 16384) */ 760 ns_cfg_rctsize = NS_CFG_RCTSIZE_16384_ENTRIES; 761 762 card->efbie = 1; 763 764 card->intcnt = 0; 765 if (request_irq 766 (pcidev->irq, &ns_irq_handler, IRQF_SHARED, "nicstar", card) != 0) { 767 printk("nicstar%d: can't allocate IRQ %d.\n", i, pcidev->irq); 768 error = 9; 769 ns_init_card_error(card, error); 770 return error; 771 } 772 773 /* Register device */ 774 card->atmdev = atm_dev_register("nicstar", &atm_ops, -1, NULL); 775 if (card->atmdev == NULL) { 776 printk("nicstar%d: can't register device.\n", i); 777 error = 17; 778 ns_init_card_error(card, error); 779 return error; 780 } 781 782 if (ns_parse_mac(mac[i], card->atmdev->esi)) { 783 nicstar_read_eprom(card->membase, NICSTAR_EPROM_MAC_ADDR_OFFSET, 784 card->atmdev->esi, 6); 785 if (memcmp(card->atmdev->esi, "\x00\x00\x00\x00\x00\x00", 6) == 786 0) { 787 nicstar_read_eprom(card->membase, 788 NICSTAR_EPROM_MAC_ADDR_OFFSET_ALT, 789 card->atmdev->esi, 6); 790 } 791 } 792 793 printk("nicstar%d: MAC address %pM\n", i, card->atmdev->esi); 794 795 card->atmdev->dev_data = card; 796 card->atmdev->ci_range.vpi_bits = card->vpibits; 797 card->atmdev->ci_range.vci_bits = card->vcibits; 798 card->atmdev->link_rate = card->max_pcr; 799 card->atmdev->phy = NULL; 800 801#ifdef CONFIG_ATM_NICSTAR_USE_SUNI 802 if (card->max_pcr == ATM_OC3_PCR) 803 suni_init(card->atmdev); 804#endif /* CONFIG_ATM_NICSTAR_USE_SUNI */ 805 806#ifdef CONFIG_ATM_NICSTAR_USE_IDT77105 807 if (card->max_pcr == ATM_25_PCR) 808 idt77105_init(card->atmdev); 809#endif /* CONFIG_ATM_NICSTAR_USE_IDT77105 */ 810 811 if (card->atmdev->phy && card->atmdev->phy->start) 812 card->atmdev->phy->start(card->atmdev); 813 814 writel(NS_CFG_RXPATH | NS_CFG_SMBUFSIZE | NS_CFG_LGBUFSIZE | NS_CFG_EFBIE | NS_CFG_RSQSIZE | NS_CFG_VPIBITS | ns_cfg_rctsize | NS_CFG_RXINT_NODELAY | NS_CFG_RAWIE | /* Only enabled if RCQ_SUPPORT */ 815 NS_CFG_RSQAFIE | NS_CFG_TXEN | NS_CFG_TXIE | NS_CFG_TSQFIE_OPT | /* Only enabled if ENABLE_TSQFIE */ 816 NS_CFG_PHYIE, card->membase + CFG); 817 818 num_cards++; 819 820 return error; 821} 822 823static void __devinit ns_init_card_error(ns_dev * card, int error) 824{ 825 if (error >= 17) { 826 writel(0x00000000, card->membase + CFG); 827 } 828 if (error >= 16) { 829 struct sk_buff *iovb; 830 while ((iovb = skb_dequeue(&card->iovpool.queue)) != NULL) 831 dev_kfree_skb_any(iovb); 832 } 833 if (error >= 15) { 834 struct sk_buff *sb; 835 while ((sb = skb_dequeue(&card->sbpool.queue)) != NULL) 836 dev_kfree_skb_any(sb); 837 free_scq(card, card->scq0, NULL); 838 } 839 if (error >= 14) { 840 struct sk_buff *lb; 841 while ((lb = skb_dequeue(&card->lbpool.queue)) != NULL) 842 dev_kfree_skb_any(lb); 843 } 844 if (error >= 13) { 845 struct sk_buff *hb; 846 while ((hb = skb_dequeue(&card->hbpool.queue)) != NULL) 847 dev_kfree_skb_any(hb); 848 } 849 if (error >= 12) { 850 kfree(card->rsq.org); 851 } 852 if (error >= 11) { 853 kfree(card->tsq.org); 854 } 855 if (error >= 10) { 856 free_irq(card->pcidev->irq, card); 857 } 858 if (error >= 4) { 859 iounmap(card->membase); 860 } 861 if (error >= 3) { 862 pci_disable_device(card->pcidev); 863 kfree(card); 864 } 865} 866 867static scq_info *get_scq(ns_dev *card, int size, u32 scd) 868{ 869 scq_info *scq; 870 int i; 871 872 if (size != VBR_SCQSIZE && size != CBR_SCQSIZE) 873 return NULL; 874 875 scq = kmalloc(sizeof(scq_info), GFP_KERNEL); 876 if (!scq) 877 return NULL; 878 scq->org = pci_alloc_consistent(card->pcidev, 2 * size, &scq->dma); 879 if (!scq->org) { 880 kfree(scq); 881 return NULL; 882 } 883 scq->skb = kmalloc(sizeof(struct sk_buff *) * 884 (size / NS_SCQE_SIZE), GFP_KERNEL); 885 if (!scq->skb) { 886 kfree(scq->org); 887 kfree(scq); 888 return NULL; 889 } 890 scq->num_entries = size / NS_SCQE_SIZE; 891 scq->base = PTR_ALIGN(scq->org, size); 892 scq->next = scq->base; 893 scq->last = scq->base + (scq->num_entries - 1); 894 scq->tail = scq->last; 895 scq->scd = scd; 896 scq->num_entries = size / NS_SCQE_SIZE; 897 scq->tbd_count = 0; 898 init_waitqueue_head(&scq->scqfull_waitq); 899 scq->full = 0; 900 spin_lock_init(&scq->lock); 901 902 for (i = 0; i < scq->num_entries; i++) 903 scq->skb[i] = NULL; 904 905 return scq; 906} 907 908/* For variable rate SCQ vcc must be NULL */ 909static void free_scq(ns_dev *card, scq_info *scq, struct atm_vcc *vcc) 910{ 911 int i; 912 913 if (scq->num_entries == VBR_SCQ_NUM_ENTRIES) 914 for (i = 0; i < scq->num_entries; i++) { 915 if (scq->skb[i] != NULL) { 916 vcc = ATM_SKB(scq->skb[i])->vcc; 917 if (vcc->pop != NULL) 918 vcc->pop(vcc, scq->skb[i]); 919 else 920 dev_kfree_skb_any(scq->skb[i]); 921 } 922 } else { /* vcc must be != NULL */ 923 924 if (vcc == NULL) { 925 printk 926 ("nicstar: free_scq() called with vcc == NULL for fixed rate scq."); 927 for (i = 0; i < scq->num_entries; i++) 928 dev_kfree_skb_any(scq->skb[i]); 929 } else 930 for (i = 0; i < scq->num_entries; i++) { 931 if (scq->skb[i] != NULL) { 932 if (vcc->pop != NULL) 933 vcc->pop(vcc, scq->skb[i]); 934 else 935 dev_kfree_skb_any(scq->skb[i]); 936 } 937 } 938 } 939 kfree(scq->skb); 940 pci_free_consistent(card->pcidev, 941 2 * (scq->num_entries == VBR_SCQ_NUM_ENTRIES ? 942 VBR_SCQSIZE : CBR_SCQSIZE), 943 scq->org, scq->dma); 944 kfree(scq); 945} 946 947/* The handles passed must be pointers to the sk_buff containing the small 948 or large buffer(s) cast to u32. */ 949static void push_rxbufs(ns_dev * card, struct sk_buff *skb) 950{ 951 struct sk_buff *handle1, *handle2; 952 u32 id1 = 0, id2 = 0; 953 u32 addr1, addr2; 954 u32 stat; 955 unsigned long flags; 956 int err; 957 958 /* *BARF* */ 959 handle2 = NULL; 960 addr2 = 0; 961 handle1 = skb; 962 addr1 = pci_map_single(card->pcidev, 963 skb->data, 964 (NS_PRV_BUFTYPE(skb) == BUF_SM 965 ? NS_SMSKBSIZE : NS_LGSKBSIZE), 966 PCI_DMA_TODEVICE); 967 NS_PRV_DMA(skb) = addr1; /* save so we can unmap later */ 968 969#ifdef GENERAL_DEBUG 970 if (!addr1) 971 printk("nicstar%d: push_rxbufs called with addr1 = 0.\n", 972 card->index); 973#endif /* GENERAL_DEBUG */ 974 975 stat = readl(card->membase + STAT); 976 card->sbfqc = ns_stat_sfbqc_get(stat); 977 card->lbfqc = ns_stat_lfbqc_get(stat); 978 if (NS_PRV_BUFTYPE(skb) == BUF_SM) { 979 if (!addr2) { 980 if (card->sm_addr) { 981 addr2 = card->sm_addr; 982 handle2 = card->sm_handle; 983 card->sm_addr = 0x00000000; 984 card->sm_handle = 0x00000000; 985 } else { /* (!sm_addr) */ 986 987 card->sm_addr = addr1; 988 card->sm_handle = handle1; 989 } 990 } 991 } else { /* buf_type == BUF_LG */ 992 993 if (!addr2) { 994 if (card->lg_addr) { 995 addr2 = card->lg_addr; 996 handle2 = card->lg_handle; 997 card->lg_addr = 0x00000000; 998 card->lg_handle = 0x00000000; 999 } else { /* (!lg_addr) */ 1000 1001 card->lg_addr = addr1; 1002 card->lg_handle = handle1; 1003 } 1004 } 1005 } 1006 1007 if (addr2) { 1008 if (NS_PRV_BUFTYPE(skb) == BUF_SM) { 1009 if (card->sbfqc >= card->sbnr.max) { 1010 skb_unlink(handle1, &card->sbpool.queue); 1011 dev_kfree_skb_any(handle1); 1012 skb_unlink(handle2, &card->sbpool.queue); 1013 dev_kfree_skb_any(handle2); 1014 return; 1015 } else 1016 card->sbfqc += 2; 1017 } else { /* (buf_type == BUF_LG) */ 1018 1019 if (card->lbfqc >= card->lbnr.max) { 1020 skb_unlink(handle1, &card->lbpool.queue); 1021 dev_kfree_skb_any(handle1); 1022 skb_unlink(handle2, &card->lbpool.queue); 1023 dev_kfree_skb_any(handle2); 1024 return; 1025 } else 1026 card->lbfqc += 2; 1027 } 1028 1029 do { 1030 if (!idr_pre_get(&card->idr, GFP_ATOMIC)) { 1031 printk(KERN_ERR 1032 "nicstar%d: no free memory for idr\n", 1033 card->index); 1034 goto out; 1035 } 1036 1037 if (!id1) 1038 err = idr_get_new_above(&card->idr, handle1, 0, &id1); 1039 1040 if (!id2 && err == 0) 1041 err = idr_get_new_above(&card->idr, handle2, 0, &id2); 1042 1043 } while (err == -EAGAIN); 1044 1045 if (err) 1046 goto out; 1047 1048 spin_lock_irqsave(&card->res_lock, flags); 1049 while (CMD_BUSY(card)) ; 1050 writel(addr2, card->membase + DR3); 1051 writel(id2, card->membase + DR2); 1052 writel(addr1, card->membase + DR1); 1053 writel(id1, card->membase + DR0); 1054 writel(NS_CMD_WRITE_FREEBUFQ | NS_PRV_BUFTYPE(skb), 1055 card->membase + CMD); 1056 spin_unlock_irqrestore(&card->res_lock, flags); 1057 1058 XPRINTK("nicstar%d: Pushing %s buffers at 0x%x and 0x%x.\n", 1059 card->index, 1060 (NS_PRV_BUFTYPE(skb) == BUF_SM ? "small" : "large"), 1061 addr1, addr2); 1062 } 1063 1064 if (!card->efbie && card->sbfqc >= card->sbnr.min && 1065 card->lbfqc >= card->lbnr.min) { 1066 card->efbie = 1; 1067 writel((readl(card->membase + CFG) | NS_CFG_EFBIE), 1068 card->membase + CFG); 1069 } 1070 1071out: 1072 return; 1073} 1074 1075static irqreturn_t ns_irq_handler(int irq, void *dev_id) 1076{ 1077 u32 stat_r; 1078 ns_dev *card; 1079 struct atm_dev *dev; 1080 unsigned long flags; 1081 1082 card = (ns_dev *) dev_id; 1083 dev = card->atmdev; 1084 card->intcnt++; 1085 1086 PRINTK("nicstar%d: NICStAR generated an interrupt\n", card->index); 1087 1088 spin_lock_irqsave(&card->int_lock, flags); 1089 1090 stat_r = readl(card->membase + STAT); 1091 1092 /* Transmit Status Indicator has been written to T. S. Queue */ 1093 if (stat_r & NS_STAT_TSIF) { 1094 TXPRINTK("nicstar%d: TSI interrupt\n", card->index); 1095 process_tsq(card); 1096 writel(NS_STAT_TSIF, card->membase + STAT); 1097 } 1098 1099 /* Incomplete CS-PDU has been transmitted */ 1100 if (stat_r & NS_STAT_TXICP) { 1101 writel(NS_STAT_TXICP, card->membase + STAT); 1102 TXPRINTK("nicstar%d: Incomplete CS-PDU transmitted.\n", 1103 card->index); 1104 } 1105 1106 /* Transmit Status Queue 7/8 full */ 1107 if (stat_r & NS_STAT_TSQF) { 1108 writel(NS_STAT_TSQF, card->membase + STAT); 1109 PRINTK("nicstar%d: TSQ full.\n", card->index); 1110 process_tsq(card); 1111 } 1112 1113 /* Timer overflow */ 1114 if (stat_r & NS_STAT_TMROF) { 1115 writel(NS_STAT_TMROF, card->membase + STAT); 1116 PRINTK("nicstar%d: Timer overflow.\n", card->index); 1117 } 1118 1119 /* PHY device interrupt signal active */ 1120 if (stat_r & NS_STAT_PHYI) { 1121 writel(NS_STAT_PHYI, card->membase + STAT); 1122 PRINTK("nicstar%d: PHY interrupt.\n", card->index); 1123 if (dev->phy && dev->phy->interrupt) { 1124 dev->phy->interrupt(dev); 1125 } 1126 } 1127 1128 /* Small Buffer Queue is full */ 1129 if (stat_r & NS_STAT_SFBQF) { 1130 writel(NS_STAT_SFBQF, card->membase + STAT); 1131 printk("nicstar%d: Small free buffer queue is full.\n", 1132 card->index); 1133 } 1134 1135 /* Large Buffer Queue is full */ 1136 if (stat_r & NS_STAT_LFBQF) { 1137 writel(NS_STAT_LFBQF, card->membase + STAT); 1138 printk("nicstar%d: Large free buffer queue is full.\n", 1139 card->index); 1140 } 1141 1142 /* Receive Status Queue is full */ 1143 if (stat_r & NS_STAT_RSQF) { 1144 writel(NS_STAT_RSQF, card->membase + STAT); 1145 printk("nicstar%d: RSQ full.\n", card->index); 1146 process_rsq(card); 1147 } 1148 1149 /* Complete CS-PDU received */ 1150 if (stat_r & NS_STAT_EOPDU) { 1151 RXPRINTK("nicstar%d: End of CS-PDU received.\n", card->index); 1152 process_rsq(card); 1153 writel(NS_STAT_EOPDU, card->membase + STAT); 1154 } 1155 1156 /* Raw cell received */ 1157 if (stat_r & NS_STAT_RAWCF) { 1158 writel(NS_STAT_RAWCF, card->membase + STAT); 1159#ifndef RCQ_SUPPORT 1160 printk("nicstar%d: Raw cell received and no support yet...\n", 1161 card->index); 1162#endif /* RCQ_SUPPORT */ 1163 /* NOTE: the following procedure may keep a raw cell pending until the 1164 next interrupt. As this preliminary support is only meant to 1165 avoid buffer leakage, this is not an issue. */ 1166 while (readl(card->membase + RAWCT) != card->rawch) { 1167 1168 if (ns_rcqe_islast(card->rawcell)) { 1169 struct sk_buff *oldbuf; 1170 1171 oldbuf = card->rcbuf; 1172 card->rcbuf = idr_find(&card->idr, 1173 ns_rcqe_nextbufhandle(card->rawcell)); 1174 card->rawch = NS_PRV_DMA(card->rcbuf); 1175 card->rawcell = (struct ns_rcqe *) 1176 card->rcbuf->data; 1177 recycle_rx_buf(card, oldbuf); 1178 } else { 1179 card->rawch += NS_RCQE_SIZE; 1180 card->rawcell++; 1181 } 1182 } 1183 } 1184 1185 /* Small buffer queue is empty */ 1186 if (stat_r & NS_STAT_SFBQE) { 1187 int i; 1188 struct sk_buff *sb; 1189 1190 writel(NS_STAT_SFBQE, card->membase + STAT); 1191 printk("nicstar%d: Small free buffer queue empty.\n", 1192 card->index); 1193 for (i = 0; i < card->sbnr.min; i++) { 1194 sb = dev_alloc_skb(NS_SMSKBSIZE); 1195 if (sb == NULL) { 1196 writel(readl(card->membase + CFG) & 1197 ~NS_CFG_EFBIE, card->membase + CFG); 1198 card->efbie = 0; 1199 break; 1200 } 1201 NS_PRV_BUFTYPE(sb) = BUF_SM; 1202 skb_queue_tail(&card->sbpool.queue, sb); 1203 skb_reserve(sb, NS_AAL0_HEADER); 1204 push_rxbufs(card, sb); 1205 } 1206 card->sbfqc = i; 1207 process_rsq(card); 1208 } 1209 1210 /* Large buffer queue empty */ 1211 if (stat_r & NS_STAT_LFBQE) { 1212 int i; 1213 struct sk_buff *lb; 1214 1215 writel(NS_STAT_LFBQE, card->membase + STAT); 1216 printk("nicstar%d: Large free buffer queue empty.\n", 1217 card->index); 1218 for (i = 0; i < card->lbnr.min; i++) { 1219 lb = dev_alloc_skb(NS_LGSKBSIZE); 1220 if (lb == NULL) { 1221 writel(readl(card->membase + CFG) & 1222 ~NS_CFG_EFBIE, card->membase + CFG); 1223 card->efbie = 0; 1224 break; 1225 } 1226 NS_PRV_BUFTYPE(lb) = BUF_LG; 1227 skb_queue_tail(&card->lbpool.queue, lb); 1228 skb_reserve(lb, NS_SMBUFSIZE); 1229 push_rxbufs(card, lb); 1230 } 1231 card->lbfqc = i; 1232 process_rsq(card); 1233 } 1234 1235 /* Receive Status Queue is 7/8 full */ 1236 if (stat_r & NS_STAT_RSQAF) { 1237 writel(NS_STAT_RSQAF, card->membase + STAT); 1238 RXPRINTK("nicstar%d: RSQ almost full.\n", card->index); 1239 process_rsq(card); 1240 } 1241 1242 spin_unlock_irqrestore(&card->int_lock, flags); 1243 PRINTK("nicstar%d: end of interrupt service\n", card->index); 1244 return IRQ_HANDLED; 1245} 1246 1247static int ns_open(struct atm_vcc *vcc) 1248{ 1249 ns_dev *card; 1250 vc_map *vc; 1251 unsigned long tmpl, modl; 1252 int tcr, tcra; /* target cell rate, and absolute value */ 1253 int n = 0; /* Number of entries in the TST. Initialized to remove 1254 the compiler warning. */ 1255 u32 u32d[4]; 1256 int frscdi = 0; /* Index of the SCD. Initialized to remove the compiler 1257 warning. How I wish compilers were clever enough to 1258 tell which variables can truly be used 1259 uninitialized... */ 1260 int inuse; /* tx or rx vc already in use by another vcc */ 1261 short vpi = vcc->vpi; 1262 int vci = vcc->vci; 1263 1264 card = (ns_dev *) vcc->dev->dev_data; 1265 PRINTK("nicstar%d: opening vpi.vci %d.%d \n", card->index, (int)vpi, 1266 vci); 1267 if (vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0) { 1268 PRINTK("nicstar%d: unsupported AAL.\n", card->index); 1269 return -EINVAL; 1270 } 1271 1272 vc = &(card->vcmap[vpi << card->vcibits | vci]); 1273 vcc->dev_data = vc; 1274 1275 inuse = 0; 1276 if (vcc->qos.txtp.traffic_class != ATM_NONE && vc->tx) 1277 inuse = 1; 1278 if (vcc->qos.rxtp.traffic_class != ATM_NONE && vc->rx) 1279 inuse += 2; 1280 if (inuse) { 1281 printk("nicstar%d: %s vci already in use.\n", card->index, 1282 inuse == 1 ? "tx" : inuse == 2 ? "rx" : "tx and rx"); 1283 return -EINVAL; 1284 } 1285 1286 set_bit(ATM_VF_ADDR, &vcc->flags); 1287 1288 /* NOTE: You are not allowed to modify an open connection's QOS. To change 1289 that, remove the ATM_VF_PARTIAL flag checking. There may be other changes 1290 needed to do that. */ 1291 if (!test_bit(ATM_VF_PARTIAL, &vcc->flags)) { 1292 scq_info *scq; 1293 1294 set_bit(ATM_VF_PARTIAL, &vcc->flags); 1295 if (vcc->qos.txtp.traffic_class == ATM_CBR) { 1296 /* Check requested cell rate and availability of SCD */ 1297 if (vcc->qos.txtp.max_pcr == 0 && vcc->qos.txtp.pcr == 0 1298 && vcc->qos.txtp.min_pcr == 0) { 1299 PRINTK 1300 ("nicstar%d: trying to open a CBR vc with cell rate = 0 \n", 1301 card->index); 1302 clear_bit(ATM_VF_PARTIAL, &vcc->flags); 1303 clear_bit(ATM_VF_ADDR, &vcc->flags); 1304 return -EINVAL; 1305 } 1306 1307 tcr = atm_pcr_goal(&(vcc->qos.txtp)); 1308 tcra = tcr >= 0 ? tcr : -tcr; 1309 1310 PRINTK("nicstar%d: target cell rate = %d.\n", 1311 card->index, vcc->qos.txtp.max_pcr); 1312 1313 tmpl = 1314 (unsigned long)tcra *(unsigned long) 1315 NS_TST_NUM_ENTRIES; 1316 modl = tmpl % card->max_pcr; 1317 1318 n = (int)(tmpl / card->max_pcr); 1319 if (tcr > 0) { 1320 if (modl > 0) 1321 n++; 1322 } else if (tcr == 0) { 1323 if ((n = 1324 (card->tst_free_entries - 1325 NS_TST_RESERVED)) <= 0) { 1326 PRINTK 1327 ("nicstar%d: no CBR bandwidth free.\n", 1328 card->index); 1329 clear_bit(ATM_VF_PARTIAL, &vcc->flags); 1330 clear_bit(ATM_VF_ADDR, &vcc->flags); 1331 return -EINVAL; 1332 } 1333 } 1334 1335 if (n == 0) { 1336 printk 1337 ("nicstar%d: selected bandwidth < granularity.\n", 1338 card->index); 1339 clear_bit(ATM_VF_PARTIAL, &vcc->flags); 1340 clear_bit(ATM_VF_ADDR, &vcc->flags); 1341 return -EINVAL; 1342 } 1343 1344 if (n > (card->tst_free_entries - NS_TST_RESERVED)) { 1345 PRINTK 1346 ("nicstar%d: not enough free CBR bandwidth.\n", 1347 card->index); 1348 clear_bit(ATM_VF_PARTIAL, &vcc->flags); 1349 clear_bit(ATM_VF_ADDR, &vcc->flags); 1350 return -EINVAL; 1351 } else 1352 card->tst_free_entries -= n; 1353 1354 XPRINTK("nicstar%d: writing %d tst entries.\n", 1355 card->index, n); 1356 for (frscdi = 0; frscdi < NS_FRSCD_NUM; frscdi++) { 1357 if (card->scd2vc[frscdi] == NULL) { 1358 card->scd2vc[frscdi] = vc; 1359 break; 1360 } 1361 } 1362 if (frscdi == NS_FRSCD_NUM) { 1363 PRINTK 1364 ("nicstar%d: no SCD available for CBR channel.\n", 1365 card->index); 1366 card->tst_free_entries += n; 1367 clear_bit(ATM_VF_PARTIAL, &vcc->flags); 1368 clear_bit(ATM_VF_ADDR, &vcc->flags); 1369 return -EBUSY; 1370 } 1371 1372 vc->cbr_scd = NS_FRSCD + frscdi * NS_FRSCD_SIZE; 1373 1374 scq = get_scq(card, CBR_SCQSIZE, vc->cbr_scd); 1375 if (scq == NULL) { 1376 PRINTK("nicstar%d: can't get fixed rate SCQ.\n", 1377 card->index); 1378 card->scd2vc[frscdi] = NULL; 1379 card->tst_free_entries += n; 1380 clear_bit(ATM_VF_PARTIAL, &vcc->flags); 1381 clear_bit(ATM_VF_ADDR, &vcc->flags); 1382 return -ENOMEM; 1383 } 1384 vc->scq = scq; 1385 u32d[0] = scq_virt_to_bus(scq, scq->base); 1386 u32d[1] = (u32) 0x00000000; 1387 u32d[2] = (u32) 0xffffffff; 1388 u32d[3] = (u32) 0x00000000; 1389 ns_write_sram(card, vc->cbr_scd, u32d, 4); 1390 1391 fill_tst(card, n, vc); 1392 } else if (vcc->qos.txtp.traffic_class == ATM_UBR) { 1393 vc->cbr_scd = 0x00000000; 1394 vc->scq = card->scq0; 1395 } 1396 1397 if (vcc->qos.txtp.traffic_class != ATM_NONE) { 1398 vc->tx = 1; 1399 vc->tx_vcc = vcc; 1400 vc->tbd_count = 0; 1401 } 1402 if (vcc->qos.rxtp.traffic_class != ATM_NONE) { 1403 u32 status; 1404 1405 vc->rx = 1; 1406 vc->rx_vcc = vcc; 1407 vc->rx_iov = NULL; 1408 1409 /* Open the connection in hardware */ 1410 if (vcc->qos.aal == ATM_AAL5) 1411 status = NS_RCTE_AAL5 | NS_RCTE_CONNECTOPEN; 1412 else /* vcc->qos.aal == ATM_AAL0 */ 1413 status = NS_RCTE_AAL0 | NS_RCTE_CONNECTOPEN; 1414#ifdef RCQ_SUPPORT 1415 status |= NS_RCTE_RAWCELLINTEN; 1416#endif /* RCQ_SUPPORT */ 1417 ns_write_sram(card, 1418 NS_RCT + 1419 (vpi << card->vcibits | vci) * 1420 NS_RCT_ENTRY_SIZE, &status, 1); 1421 } 1422 1423 } 1424 1425 set_bit(ATM_VF_READY, &vcc->flags); 1426 return 0; 1427} 1428 1429static void ns_close(struct atm_vcc *vcc) 1430{ 1431 vc_map *vc; 1432 ns_dev *card; 1433 u32 data; 1434 int i; 1435 1436 vc = vcc->dev_data; 1437 card = vcc->dev->dev_data; 1438 PRINTK("nicstar%d: closing vpi.vci %d.%d \n", card->index, 1439 (int)vcc->vpi, vcc->vci); 1440 1441 clear_bit(ATM_VF_READY, &vcc->flags); 1442 1443 if (vcc->qos.rxtp.traffic_class != ATM_NONE) { 1444 u32 addr; 1445 unsigned long flags; 1446 1447 addr = 1448 NS_RCT + 1449 (vcc->vpi << card->vcibits | vcc->vci) * NS_RCT_ENTRY_SIZE; 1450 spin_lock_irqsave(&card->res_lock, flags); 1451 while (CMD_BUSY(card)) ; 1452 writel(NS_CMD_CLOSE_CONNECTION | addr << 2, 1453 card->membase + CMD); 1454 spin_unlock_irqrestore(&card->res_lock, flags); 1455 1456 vc->rx = 0; 1457 if (vc->rx_iov != NULL) { 1458 struct sk_buff *iovb; 1459 u32 stat; 1460 1461 stat = readl(card->membase + STAT); 1462 card->sbfqc = ns_stat_sfbqc_get(stat); 1463 card->lbfqc = ns_stat_lfbqc_get(stat); 1464 1465 PRINTK 1466 ("nicstar%d: closing a VC with pending rx buffers.\n", 1467 card->index); 1468 iovb = vc->rx_iov; 1469 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data, 1470 NS_PRV_IOVCNT(iovb)); 1471 NS_PRV_IOVCNT(iovb) = 0; 1472 spin_lock_irqsave(&card->int_lock, flags); 1473 recycle_iov_buf(card, iovb); 1474 spin_unlock_irqrestore(&card->int_lock, flags); 1475 vc->rx_iov = NULL; 1476 } 1477 } 1478 1479 if (vcc->qos.txtp.traffic_class != ATM_NONE) { 1480 vc->tx = 0; 1481 } 1482 1483 if (vcc->qos.txtp.traffic_class == ATM_CBR) { 1484 unsigned long flags; 1485 ns_scqe *scqep; 1486 scq_info *scq; 1487 1488 scq = vc->scq; 1489 1490 for (;;) { 1491 spin_lock_irqsave(&scq->lock, flags); 1492 scqep = scq->next; 1493 if (scqep == scq->base) 1494 scqep = scq->last; 1495 else 1496 scqep--; 1497 if (scqep == scq->tail) { 1498 spin_unlock_irqrestore(&scq->lock, flags); 1499 break; 1500 } 1501 /* If the last entry is not a TSR, place one in the SCQ in order to 1502 be able to completely drain it and then close. */ 1503 if (!ns_scqe_is_tsr(scqep) && scq->tail != scq->next) { 1504 ns_scqe tsr; 1505 u32 scdi, scqi; 1506 u32 data; 1507 int index; 1508 1509 tsr.word_1 = ns_tsr_mkword_1(NS_TSR_INTENABLE); 1510 scdi = (vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE; 1511 scqi = scq->next - scq->base; 1512 tsr.word_2 = ns_tsr_mkword_2(scdi, scqi); 1513 tsr.word_3 = 0x00000000; 1514 tsr.word_4 = 0x00000000; 1515 *scq->next = tsr; 1516 index = (int)scqi; 1517 scq->skb[index] = NULL; 1518 if (scq->next == scq->last) 1519 scq->next = scq->base; 1520 else 1521 scq->next++; 1522 data = scq_virt_to_bus(scq, scq->next); 1523 ns_write_sram(card, scq->scd, &data, 1); 1524 } 1525 spin_unlock_irqrestore(&scq->lock, flags); 1526 schedule(); 1527 } 1528 1529 /* Free all TST entries */ 1530 data = NS_TST_OPCODE_VARIABLE; 1531 for (i = 0; i < NS_TST_NUM_ENTRIES; i++) { 1532 if (card->tste2vc[i] == vc) { 1533 ns_write_sram(card, card->tst_addr + i, &data, 1534 1); 1535 card->tste2vc[i] = NULL; 1536 card->tst_free_entries++; 1537 } 1538 } 1539 1540 card->scd2vc[(vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE] = NULL; 1541 free_scq(card, vc->scq, vcc); 1542 } 1543 1544 /* remove all references to vcc before deleting it */ 1545 if (vcc->qos.txtp.traffic_class != ATM_NONE) { 1546 unsigned long flags; 1547 scq_info *scq = card->scq0; 1548 1549 spin_lock_irqsave(&scq->lock, flags); 1550 1551 for (i = 0; i < scq->num_entries; i++) { 1552 if (scq->skb[i] && ATM_SKB(scq->skb[i])->vcc == vcc) { 1553 ATM_SKB(scq->skb[i])->vcc = NULL; 1554 atm_return(vcc, scq->skb[i]->truesize); 1555 PRINTK 1556 ("nicstar: deleted pending vcc mapping\n"); 1557 } 1558 } 1559 1560 spin_unlock_irqrestore(&scq->lock, flags); 1561 } 1562 1563 vcc->dev_data = NULL; 1564 clear_bit(ATM_VF_PARTIAL, &vcc->flags); 1565 clear_bit(ATM_VF_ADDR, &vcc->flags); 1566 1567#ifdef RX_DEBUG 1568 { 1569 u32 stat, cfg; 1570 stat = readl(card->membase + STAT); 1571 cfg = readl(card->membase + CFG); 1572 printk("STAT = 0x%08X CFG = 0x%08X \n", stat, cfg); 1573 printk 1574 ("TSQ: base = 0x%p next = 0x%p last = 0x%p TSQT = 0x%08X \n", 1575 card->tsq.base, card->tsq.next, 1576 card->tsq.last, readl(card->membase + TSQT)); 1577 printk 1578 ("RSQ: base = 0x%p next = 0x%p last = 0x%p RSQT = 0x%08X \n", 1579 card->rsq.base, card->rsq.next, 1580 card->rsq.last, readl(card->membase + RSQT)); 1581 printk("Empty free buffer queue interrupt %s \n", 1582 card->efbie ? "enabled" : "disabled"); 1583 printk("SBCNT = %d count = %d LBCNT = %d count = %d \n", 1584 ns_stat_sfbqc_get(stat), card->sbpool.count, 1585 ns_stat_lfbqc_get(stat), card->lbpool.count); 1586 printk("hbpool.count = %d iovpool.count = %d \n", 1587 card->hbpool.count, card->iovpool.count); 1588 } 1589#endif /* RX_DEBUG */ 1590} 1591 1592static void fill_tst(ns_dev * card, int n, vc_map * vc) 1593{ 1594 u32 new_tst; 1595 unsigned long cl; 1596 int e, r; 1597 u32 data; 1598 1599 /* It would be very complicated to keep the two TSTs synchronized while 1600 assuring that writes are only made to the inactive TST. So, for now I 1601 will use only one TST. If problems occur, I will change this again */ 1602 1603 new_tst = card->tst_addr; 1604 1605 /* Fill procedure */ 1606 1607 for (e = 0; e < NS_TST_NUM_ENTRIES; e++) { 1608 if (card->tste2vc[e] == NULL) 1609 break; 1610 } 1611 if (e == NS_TST_NUM_ENTRIES) { 1612 printk("nicstar%d: No free TST entries found. \n", card->index); 1613 return; 1614 } 1615 1616 r = n; 1617 cl = NS_TST_NUM_ENTRIES; 1618 data = ns_tste_make(NS_TST_OPCODE_FIXED, vc->cbr_scd); 1619 1620 while (r > 0) { 1621 if (cl >= NS_TST_NUM_ENTRIES && card->tste2vc[e] == NULL) { 1622 card->tste2vc[e] = vc; 1623 ns_write_sram(card, new_tst + e, &data, 1); 1624 cl -= NS_TST_NUM_ENTRIES; 1625 r--; 1626 } 1627 1628 if (++e == NS_TST_NUM_ENTRIES) { 1629 e = 0; 1630 } 1631 cl += n; 1632 } 1633 1634 /* End of fill procedure */ 1635 1636 data = ns_tste_make(NS_TST_OPCODE_END, new_tst); 1637 ns_write_sram(card, new_tst + NS_TST_NUM_ENTRIES, &data, 1); 1638 ns_write_sram(card, card->tst_addr + NS_TST_NUM_ENTRIES, &data, 1); 1639 card->tst_addr = new_tst; 1640} 1641 1642static int ns_send(struct atm_vcc *vcc, struct sk_buff *skb) 1643{ 1644 ns_dev *card; 1645 vc_map *vc; 1646 scq_info *scq; 1647 unsigned long buflen; 1648 ns_scqe scqe; 1649 u32 flags; /* TBD flags, not CPU flags */ 1650 1651 card = vcc->dev->dev_data; 1652 TXPRINTK("nicstar%d: ns_send() called.\n", card->index); 1653 if ((vc = (vc_map *) vcc->dev_data) == NULL) { 1654 printk("nicstar%d: vcc->dev_data == NULL on ns_send().\n", 1655 card->index); 1656 atomic_inc(&vcc->stats->tx_err); 1657 dev_kfree_skb_any(skb); 1658 return -EINVAL; 1659 } 1660 1661 if (!vc->tx) { 1662 printk("nicstar%d: Trying to transmit on a non-tx VC.\n", 1663 card->index); 1664 atomic_inc(&vcc->stats->tx_err); 1665 dev_kfree_skb_any(skb); 1666 return -EINVAL; 1667 } 1668 1669 if (vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0) { 1670 printk("nicstar%d: Only AAL0 and AAL5 are supported.\n", 1671 card->index); 1672 atomic_inc(&vcc->stats->tx_err); 1673 dev_kfree_skb_any(skb); 1674 return -EINVAL; 1675 } 1676 1677 if (skb_shinfo(skb)->nr_frags != 0) { 1678 printk("nicstar%d: No scatter-gather yet.\n", card->index); 1679 atomic_inc(&vcc->stats->tx_err); 1680 dev_kfree_skb_any(skb); 1681 return -EINVAL; 1682 } 1683 1684 ATM_SKB(skb)->vcc = vcc; 1685 1686 NS_PRV_DMA(skb) = pci_map_single(card->pcidev, skb->data, 1687 skb->len, PCI_DMA_TODEVICE); 1688 1689 if (vcc->qos.aal == ATM_AAL5) { 1690 buflen = (skb->len + 47 + 8) / 48 * 48; /* Multiple of 48 */ 1691 flags = NS_TBD_AAL5; 1692 scqe.word_2 = cpu_to_le32(NS_PRV_DMA(skb)); 1693 scqe.word_3 = cpu_to_le32(skb->len); 1694 scqe.word_4 = 1695 ns_tbd_mkword_4(0, (u32) vcc->vpi, (u32) vcc->vci, 0, 1696 ATM_SKB(skb)-> 1697 atm_options & ATM_ATMOPT_CLP ? 1 : 0); 1698 flags |= NS_TBD_EOPDU; 1699 } else { /* (vcc->qos.aal == ATM_AAL0) */ 1700 1701 buflen = ATM_CELL_PAYLOAD; /* i.e., 48 bytes */ 1702 flags = NS_TBD_AAL0; 1703 scqe.word_2 = cpu_to_le32(NS_PRV_DMA(skb) + NS_AAL0_HEADER); 1704 scqe.word_3 = cpu_to_le32(0x00000000); 1705 if (*skb->data & 0x02) /* Payload type 1 - end of pdu */ 1706 flags |= NS_TBD_EOPDU; 1707 scqe.word_4 = 1708 cpu_to_le32(*((u32 *) skb->data) & ~NS_TBD_VC_MASK); 1709 /* Force the VPI/VCI to be the same as in VCC struct */ 1710 scqe.word_4 |= 1711 cpu_to_le32((((u32) vcc-> 1712 vpi) << NS_TBD_VPI_SHIFT | ((u32) vcc-> 1713 vci) << 1714 NS_TBD_VCI_SHIFT) & NS_TBD_VC_MASK); 1715 } 1716 1717 if (vcc->qos.txtp.traffic_class == ATM_CBR) { 1718 scqe.word_1 = ns_tbd_mkword_1_novbr(flags, (u32) buflen); 1719 scq = ((vc_map *) vcc->dev_data)->scq; 1720 } else { 1721 scqe.word_1 = 1722 ns_tbd_mkword_1(flags, (u32) 1, (u32) 1, (u32) buflen); 1723 scq = card->scq0; 1724 } 1725 1726 if (push_scqe(card, vc, scq, &scqe, skb) != 0) { 1727 atomic_inc(&vcc->stats->tx_err); 1728 dev_kfree_skb_any(skb); 1729 return -EIO; 1730 } 1731 atomic_inc(&vcc->stats->tx); 1732 1733 return 0; 1734} 1735 1736static int push_scqe(ns_dev * card, vc_map * vc, scq_info * scq, ns_scqe * tbd, 1737 struct sk_buff *skb) 1738{ 1739 unsigned long flags; 1740 ns_scqe tsr; 1741 u32 scdi, scqi; 1742 int scq_is_vbr; 1743 u32 data; 1744 int index; 1745 1746 spin_lock_irqsave(&scq->lock, flags); 1747 while (scq->tail == scq->next) { 1748 if (in_interrupt()) { 1749 spin_unlock_irqrestore(&scq->lock, flags); 1750 printk("nicstar%d: Error pushing TBD.\n", card->index); 1751 return 1; 1752 } 1753 1754 scq->full = 1; 1755 spin_unlock_irqrestore(&scq->lock, flags); 1756 interruptible_sleep_on_timeout(&scq->scqfull_waitq, 1757 SCQFULL_TIMEOUT); 1758 spin_lock_irqsave(&scq->lock, flags); 1759 1760 if (scq->full) { 1761 spin_unlock_irqrestore(&scq->lock, flags); 1762 printk("nicstar%d: Timeout pushing TBD.\n", 1763 card->index); 1764 return 1; 1765 } 1766 } 1767 *scq->next = *tbd; 1768 index = (int)(scq->next - scq->base); 1769 scq->skb[index] = skb; 1770 XPRINTK("nicstar%d: sending skb at 0x%p (pos %d).\n", 1771 card->index, skb, index); 1772 XPRINTK("nicstar%d: TBD written:\n0x%x\n0x%x\n0x%x\n0x%x\n at 0x%p.\n", 1773 card->index, le32_to_cpu(tbd->word_1), le32_to_cpu(tbd->word_2), 1774 le32_to_cpu(tbd->word_3), le32_to_cpu(tbd->word_4), 1775 scq->next); 1776 if (scq->next == scq->last) 1777 scq->next = scq->base; 1778 else 1779 scq->next++; 1780 1781 vc->tbd_count++; 1782 if (scq->num_entries == VBR_SCQ_NUM_ENTRIES) { 1783 scq->tbd_count++; 1784 scq_is_vbr = 1; 1785 } else 1786 scq_is_vbr = 0; 1787 1788 if (vc->tbd_count >= MAX_TBD_PER_VC 1789 || scq->tbd_count >= MAX_TBD_PER_SCQ) { 1790 int has_run = 0; 1791 1792 while (scq->tail == scq->next) { 1793 if (in_interrupt()) { 1794 data = scq_virt_to_bus(scq, scq->next); 1795 ns_write_sram(card, scq->scd, &data, 1); 1796 spin_unlock_irqrestore(&scq->lock, flags); 1797 printk("nicstar%d: Error pushing TSR.\n", 1798 card->index); 1799 return 0; 1800 } 1801 1802 scq->full = 1; 1803 if (has_run++) 1804 break; 1805 spin_unlock_irqrestore(&scq->lock, flags); 1806 interruptible_sleep_on_timeout(&scq->scqfull_waitq, 1807 SCQFULL_TIMEOUT); 1808 spin_lock_irqsave(&scq->lock, flags); 1809 } 1810 1811 if (!scq->full) { 1812 tsr.word_1 = ns_tsr_mkword_1(NS_TSR_INTENABLE); 1813 if (scq_is_vbr) 1814 scdi = NS_TSR_SCDISVBR; 1815 else 1816 scdi = (vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE; 1817 scqi = scq->next - scq->base; 1818 tsr.word_2 = ns_tsr_mkword_2(scdi, scqi); 1819 tsr.word_3 = 0x00000000; 1820 tsr.word_4 = 0x00000000; 1821 1822 *scq->next = tsr; 1823 index = (int)scqi; 1824 scq->skb[index] = NULL; 1825 XPRINTK 1826 ("nicstar%d: TSR written:\n0x%x\n0x%x\n0x%x\n0x%x\n at 0x%p.\n", 1827 card->index, le32_to_cpu(tsr.word_1), 1828 le32_to_cpu(tsr.word_2), le32_to_cpu(tsr.word_3), 1829 le32_to_cpu(tsr.word_4), scq->next); 1830 if (scq->next == scq->last) 1831 scq->next = scq->base; 1832 else 1833 scq->next++; 1834 vc->tbd_count = 0; 1835 scq->tbd_count = 0; 1836 } else 1837 PRINTK("nicstar%d: Timeout pushing TSR.\n", 1838 card->index); 1839 } 1840 data = scq_virt_to_bus(scq, scq->next); 1841 ns_write_sram(card, scq->scd, &data, 1); 1842 1843 spin_unlock_irqrestore(&scq->lock, flags); 1844 1845 return 0; 1846} 1847 1848static void process_tsq(ns_dev * card) 1849{ 1850 u32 scdi; 1851 scq_info *scq; 1852 ns_tsi *previous = NULL, *one_ahead, *two_ahead; 1853 int serviced_entries; /* flag indicating at least on entry was serviced */ 1854 1855 serviced_entries = 0; 1856 1857 if (card->tsq.next == card->tsq.last) 1858 one_ahead = card->tsq.base; 1859 else 1860 one_ahead = card->tsq.next + 1; 1861 1862 if (one_ahead == card->tsq.last) 1863 two_ahead = card->tsq.base; 1864 else 1865 two_ahead = one_ahead + 1; 1866 1867 while (!ns_tsi_isempty(card->tsq.next) || !ns_tsi_isempty(one_ahead) || 1868 !ns_tsi_isempty(two_ahead)) 1869 /* At most two empty, as stated in the 77201 errata */ 1870 { 1871 serviced_entries = 1; 1872 1873 /* Skip the one or two possible empty entries */ 1874 while (ns_tsi_isempty(card->tsq.next)) { 1875 if (card->tsq.next == card->tsq.last) 1876 card->tsq.next = card->tsq.base; 1877 else 1878 card->tsq.next++; 1879 } 1880 1881 if (!ns_tsi_tmrof(card->tsq.next)) { 1882 scdi = ns_tsi_getscdindex(card->tsq.next); 1883 if (scdi == NS_TSI_SCDISVBR) 1884 scq = card->scq0; 1885 else { 1886 if (card->scd2vc[scdi] == NULL) { 1887 printk 1888 ("nicstar%d: could not find VC from SCD index.\n", 1889 card->index); 1890 ns_tsi_init(card->tsq.next); 1891 return; 1892 } 1893 scq = card->scd2vc[scdi]->scq; 1894 } 1895 drain_scq(card, scq, ns_tsi_getscqpos(card->tsq.next)); 1896 scq->full = 0; 1897 wake_up_interruptible(&(scq->scqfull_waitq)); 1898 } 1899 1900 ns_tsi_init(card->tsq.next); 1901 previous = card->tsq.next; 1902 if (card->tsq.next == card->tsq.last) 1903 card->tsq.next = card->tsq.base; 1904 else 1905 card->tsq.next++; 1906 1907 if (card->tsq.next == card->tsq.last) 1908 one_ahead = card->tsq.base; 1909 else 1910 one_ahead = card->tsq.next + 1; 1911 1912 if (one_ahead == card->tsq.last) 1913 two_ahead = card->tsq.base; 1914 else 1915 two_ahead = one_ahead + 1; 1916 } 1917 1918 if (serviced_entries) 1919 writel(PTR_DIFF(previous, card->tsq.base), 1920 card->membase + TSQH); 1921} 1922 1923static void drain_scq(ns_dev * card, scq_info * scq, int pos) 1924{ 1925 struct atm_vcc *vcc; 1926 struct sk_buff *skb; 1927 int i; 1928 unsigned long flags; 1929 1930 XPRINTK("nicstar%d: drain_scq() called, scq at 0x%p, pos %d.\n", 1931 card->index, scq, pos); 1932 if (pos >= scq->num_entries) { 1933 printk("nicstar%d: Bad index on drain_scq().\n", card->index); 1934 return; 1935 } 1936 1937 spin_lock_irqsave(&scq->lock, flags); 1938 i = (int)(scq->tail - scq->base); 1939 if (++i == scq->num_entries) 1940 i = 0; 1941 while (i != pos) { 1942 skb = scq->skb[i]; 1943 XPRINTK("nicstar%d: freeing skb at 0x%p (index %d).\n", 1944 card->index, skb, i); 1945 if (skb != NULL) { 1946 pci_unmap_single(card->pcidev, 1947 NS_PRV_DMA(skb), 1948 skb->len, 1949 PCI_DMA_TODEVICE); 1950 vcc = ATM_SKB(skb)->vcc; 1951 if (vcc && vcc->pop != NULL) { 1952 vcc->pop(vcc, skb); 1953 } else { 1954 dev_kfree_skb_irq(skb); 1955 } 1956 scq->skb[i] = NULL; 1957 } 1958 if (++i == scq->num_entries) 1959 i = 0; 1960 } 1961 scq->tail = scq->base + pos; 1962 spin_unlock_irqrestore(&scq->lock, flags); 1963} 1964 1965static void process_rsq(ns_dev * card) 1966{ 1967 ns_rsqe *previous; 1968 1969 if (!ns_rsqe_valid(card->rsq.next)) 1970 return; 1971 do { 1972 dequeue_rx(card, card->rsq.next); 1973 ns_rsqe_init(card->rsq.next); 1974 previous = card->rsq.next; 1975 if (card->rsq.next == card->rsq.last) 1976 card->rsq.next = card->rsq.base; 1977 else 1978 card->rsq.next++; 1979 } while (ns_rsqe_valid(card->rsq.next)); 1980 writel(PTR_DIFF(previous, card->rsq.base), card->membase + RSQH); 1981} 1982 1983static void dequeue_rx(ns_dev * card, ns_rsqe * rsqe) 1984{ 1985 u32 vpi, vci; 1986 vc_map *vc; 1987 struct sk_buff *iovb; 1988 struct iovec *iov; 1989 struct atm_vcc *vcc; 1990 struct sk_buff *skb; 1991 unsigned short aal5_len; 1992 int len; 1993 u32 stat; 1994 u32 id; 1995 1996 stat = readl(card->membase + STAT); 1997 card->sbfqc = ns_stat_sfbqc_get(stat); 1998 card->lbfqc = ns_stat_lfbqc_get(stat); 1999 2000 id = le32_to_cpu(rsqe->buffer_handle); 2001 skb = idr_find(&card->idr, id); 2002 if (!skb) { 2003 RXPRINTK(KERN_ERR 2004 "nicstar%d: idr_find() failed!\n", card->index); 2005 return; 2006 } 2007 idr_remove(&card->idr, id); 2008 pci_dma_sync_single_for_cpu(card->pcidev, 2009 NS_PRV_DMA(skb), 2010 (NS_PRV_BUFTYPE(skb) == BUF_SM 2011 ? NS_SMSKBSIZE : NS_LGSKBSIZE), 2012 PCI_DMA_FROMDEVICE); 2013 pci_unmap_single(card->pcidev, 2014 NS_PRV_DMA(skb), 2015 (NS_PRV_BUFTYPE(skb) == BUF_SM 2016 ? NS_SMSKBSIZE : NS_LGSKBSIZE), 2017 PCI_DMA_FROMDEVICE); 2018 vpi = ns_rsqe_vpi(rsqe); 2019 vci = ns_rsqe_vci(rsqe); 2020 if (vpi >= 1UL << card->vpibits || vci >= 1UL << card->vcibits) { 2021 printk("nicstar%d: SDU received for out-of-range vc %d.%d.\n", 2022 card->index, vpi, vci); 2023 recycle_rx_buf(card, skb); 2024 return; 2025 } 2026 2027 vc = &(card->vcmap[vpi << card->vcibits | vci]); 2028 if (!vc->rx) { 2029 RXPRINTK("nicstar%d: SDU received on non-rx vc %d.%d.\n", 2030 card->index, vpi, vci); 2031 recycle_rx_buf(card, skb); 2032 return; 2033 } 2034 2035 vcc = vc->rx_vcc; 2036 2037 if (vcc->qos.aal == ATM_AAL0) { 2038 struct sk_buff *sb; 2039 unsigned char *cell; 2040 int i; 2041 2042 cell = skb->data; 2043 for (i = ns_rsqe_cellcount(rsqe); i; i--) { 2044 if ((sb = dev_alloc_skb(NS_SMSKBSIZE)) == NULL) { 2045 printk 2046 ("nicstar%d: Can't allocate buffers for aal0.\n", 2047 card->index); 2048 atomic_add(i, &vcc->stats->rx_drop); 2049 break; 2050 } 2051 if (!atm_charge(vcc, sb->truesize)) { 2052 RXPRINTK 2053 ("nicstar%d: atm_charge() dropped aal0 packets.\n", 2054 card->index); 2055 atomic_add(i - 1, &vcc->stats->rx_drop); /* already increased by 1 */ 2056 dev_kfree_skb_any(sb); 2057 break; 2058 } 2059 /* Rebuild the header */ 2060 *((u32 *) sb->data) = le32_to_cpu(rsqe->word_1) << 4 | 2061 (ns_rsqe_clp(rsqe) ? 0x00000001 : 0x00000000); 2062 if (i == 1 && ns_rsqe_eopdu(rsqe)) 2063 *((u32 *) sb->data) |= 0x00000002; 2064 skb_put(sb, NS_AAL0_HEADER); 2065 memcpy(skb_tail_pointer(sb), cell, ATM_CELL_PAYLOAD); 2066 skb_put(sb, ATM_CELL_PAYLOAD); 2067 ATM_SKB(sb)->vcc = vcc; 2068 __net_timestamp(sb); 2069 vcc->push(vcc, sb); 2070 atomic_inc(&vcc->stats->rx); 2071 cell += ATM_CELL_PAYLOAD; 2072 } 2073 2074 recycle_rx_buf(card, skb); 2075 return; 2076 } 2077 2078 /* To reach this point, the AAL layer can only be AAL5 */ 2079 2080 if ((iovb = vc->rx_iov) == NULL) { 2081 iovb = skb_dequeue(&(card->iovpool.queue)); 2082 if (iovb == NULL) { /* No buffers in the queue */ 2083 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_ATOMIC); 2084 if (iovb == NULL) { 2085 printk("nicstar%d: Out of iovec buffers.\n", 2086 card->index); 2087 atomic_inc(&vcc->stats->rx_drop); 2088 recycle_rx_buf(card, skb); 2089 return; 2090 } 2091 NS_PRV_BUFTYPE(iovb) = BUF_NONE; 2092 } else if (--card->iovpool.count < card->iovnr.min) { 2093 struct sk_buff *new_iovb; 2094 if ((new_iovb = 2095 alloc_skb(NS_IOVBUFSIZE, GFP_ATOMIC)) != NULL) { 2096 NS_PRV_BUFTYPE(iovb) = BUF_NONE; 2097 skb_queue_tail(&card->iovpool.queue, new_iovb); 2098 card->iovpool.count++; 2099 } 2100 } 2101 vc->rx_iov = iovb; 2102 NS_PRV_IOVCNT(iovb) = 0; 2103 iovb->len = 0; 2104 iovb->data = iovb->head; 2105 skb_reset_tail_pointer(iovb); 2106 /* IMPORTANT: a pointer to the sk_buff containing the small or large 2107 buffer is stored as iovec base, NOT a pointer to the 2108 small or large buffer itself. */ 2109 } else if (NS_PRV_IOVCNT(iovb) >= NS_MAX_IOVECS) { 2110 printk("nicstar%d: received too big AAL5 SDU.\n", card->index); 2111 atomic_inc(&vcc->stats->rx_err); 2112 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data, 2113 NS_MAX_IOVECS); 2114 NS_PRV_IOVCNT(iovb) = 0; 2115 iovb->len = 0; 2116 iovb->data = iovb->head; 2117 skb_reset_tail_pointer(iovb); 2118 } 2119 iov = &((struct iovec *)iovb->data)[NS_PRV_IOVCNT(iovb)++]; 2120 iov->iov_base = (void *)skb; 2121 iov->iov_len = ns_rsqe_cellcount(rsqe) * 48; 2122 iovb->len += iov->iov_len; 2123 2124#ifdef EXTRA_DEBUG 2125 if (NS_PRV_IOVCNT(iovb) == 1) { 2126 if (NS_PRV_BUFTYPE(skb) != BUF_SM) { 2127 printk 2128 ("nicstar%d: Expected a small buffer, and this is not one.\n", 2129 card->index); 2130 which_list(card, skb); 2131 atomic_inc(&vcc->stats->rx_err); 2132 recycle_rx_buf(card, skb); 2133 vc->rx_iov = NULL; 2134 recycle_iov_buf(card, iovb); 2135 return; 2136 } 2137 } else { /* NS_PRV_IOVCNT(iovb) >= 2 */ 2138 2139 if (NS_PRV_BUFTYPE(skb) != BUF_LG) { 2140 printk 2141 ("nicstar%d: Expected a large buffer, and this is not one.\n", 2142 card->index); 2143 which_list(card, skb); 2144 atomic_inc(&vcc->stats->rx_err); 2145 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data, 2146 NS_PRV_IOVCNT(iovb)); 2147 vc->rx_iov = NULL; 2148 recycle_iov_buf(card, iovb); 2149 return; 2150 } 2151 } 2152#endif /* EXTRA_DEBUG */ 2153 2154 if (ns_rsqe_eopdu(rsqe)) { 2155 /* This works correctly regardless of the endianness of the host */ 2156 unsigned char *L1L2 = (unsigned char *) 2157 (skb->data + iov->iov_len - 6); 2158 aal5_len = L1L2[0] << 8 | L1L2[1]; 2159 len = (aal5_len == 0x0000) ? 0x10000 : aal5_len; 2160 if (ns_rsqe_crcerr(rsqe) || 2161 len + 8 > iovb->len || len + (47 + 8) < iovb->len) { 2162 printk("nicstar%d: AAL5 CRC error", card->index); 2163 if (len + 8 > iovb->len || len + (47 + 8) < iovb->len) 2164 printk(" - PDU size mismatch.\n"); 2165 else 2166 printk(".\n"); 2167 atomic_inc(&vcc->stats->rx_err); 2168 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data, 2169 NS_PRV_IOVCNT(iovb)); 2170 vc->rx_iov = NULL; 2171 recycle_iov_buf(card, iovb); 2172 return; 2173 } 2174 2175 /* By this point we (hopefully) have a complete SDU without errors. */ 2176 2177 if (NS_PRV_IOVCNT(iovb) == 1) { /* Just a small buffer */ 2178 /* skb points to a small buffer */ 2179 if (!atm_charge(vcc, skb->truesize)) { 2180 push_rxbufs(card, skb); 2181 atomic_inc(&vcc->stats->rx_drop); 2182 } else { 2183 skb_put(skb, len); 2184 dequeue_sm_buf(card, skb); 2185#ifdef NS_USE_DESTRUCTORS 2186 skb->destructor = ns_sb_destructor; 2187#endif /* NS_USE_DESTRUCTORS */ 2188 ATM_SKB(skb)->vcc = vcc; 2189 __net_timestamp(skb); 2190 vcc->push(vcc, skb); 2191 atomic_inc(&vcc->stats->rx); 2192 } 2193 } else if (NS_PRV_IOVCNT(iovb) == 2) { /* One small plus one large buffer */ 2194 struct sk_buff *sb; 2195 2196 sb = (struct sk_buff *)(iov - 1)->iov_base; 2197 /* skb points to a large buffer */ 2198 2199 if (len <= NS_SMBUFSIZE) { 2200 if (!atm_charge(vcc, sb->truesize)) { 2201 push_rxbufs(card, sb); 2202 atomic_inc(&vcc->stats->rx_drop); 2203 } else { 2204 skb_put(sb, len); 2205 dequeue_sm_buf(card, sb); 2206#ifdef NS_USE_DESTRUCTORS 2207 sb->destructor = ns_sb_destructor; 2208#endif /* NS_USE_DESTRUCTORS */ 2209 ATM_SKB(sb)->vcc = vcc; 2210 __net_timestamp(sb); 2211 vcc->push(vcc, sb); 2212 atomic_inc(&vcc->stats->rx); 2213 } 2214 2215 push_rxbufs(card, skb); 2216 2217 } else { /* len > NS_SMBUFSIZE, the usual case */ 2218 2219 if (!atm_charge(vcc, skb->truesize)) { 2220 push_rxbufs(card, skb); 2221 atomic_inc(&vcc->stats->rx_drop); 2222 } else { 2223 dequeue_lg_buf(card, skb); 2224#ifdef NS_USE_DESTRUCTORS 2225 skb->destructor = ns_lb_destructor; 2226#endif /* NS_USE_DESTRUCTORS */ 2227 skb_push(skb, NS_SMBUFSIZE); 2228 skb_copy_from_linear_data(sb, skb->data, 2229 NS_SMBUFSIZE); 2230 skb_put(skb, len - NS_SMBUFSIZE); 2231 ATM_SKB(skb)->vcc = vcc; 2232 __net_timestamp(skb); 2233 vcc->push(vcc, skb); 2234 atomic_inc(&vcc->stats->rx); 2235 } 2236 2237 push_rxbufs(card, sb); 2238 2239 } 2240 2241 } else { /* Must push a huge buffer */ 2242 2243 struct sk_buff *hb, *sb, *lb; 2244 int remaining, tocopy; 2245 int j; 2246 2247 hb = skb_dequeue(&(card->hbpool.queue)); 2248 if (hb == NULL) { /* No buffers in the queue */ 2249 2250 hb = dev_alloc_skb(NS_HBUFSIZE); 2251 if (hb == NULL) { 2252 printk 2253 ("nicstar%d: Out of huge buffers.\n", 2254 card->index); 2255 atomic_inc(&vcc->stats->rx_drop); 2256 recycle_iovec_rx_bufs(card, 2257 (struct iovec *) 2258 iovb->data, 2259 NS_PRV_IOVCNT(iovb)); 2260 vc->rx_iov = NULL; 2261 recycle_iov_buf(card, iovb); 2262 return; 2263 } else if (card->hbpool.count < card->hbnr.min) { 2264 struct sk_buff *new_hb; 2265 if ((new_hb = 2266 dev_alloc_skb(NS_HBUFSIZE)) != 2267 NULL) { 2268 skb_queue_tail(&card->hbpool. 2269 queue, new_hb); 2270 card->hbpool.count++; 2271 } 2272 } 2273 NS_PRV_BUFTYPE(hb) = BUF_NONE; 2274 } else if (--card->hbpool.count < card->hbnr.min) { 2275 struct sk_buff *new_hb; 2276 if ((new_hb = 2277 dev_alloc_skb(NS_HBUFSIZE)) != NULL) { 2278 NS_PRV_BUFTYPE(new_hb) = BUF_NONE; 2279 skb_queue_tail(&card->hbpool.queue, 2280 new_hb); 2281 card->hbpool.count++; 2282 } 2283 if (card->hbpool.count < card->hbnr.min) { 2284 if ((new_hb = 2285 dev_alloc_skb(NS_HBUFSIZE)) != 2286 NULL) { 2287 NS_PRV_BUFTYPE(new_hb) = 2288 BUF_NONE; 2289 skb_queue_tail(&card->hbpool. 2290 queue, new_hb); 2291 card->hbpool.count++; 2292 } 2293 } 2294 } 2295 2296 iov = (struct iovec *)iovb->data; 2297 2298 if (!atm_charge(vcc, hb->truesize)) { 2299 recycle_iovec_rx_bufs(card, iov, 2300 NS_PRV_IOVCNT(iovb)); 2301 if (card->hbpool.count < card->hbnr.max) { 2302 skb_queue_tail(&card->hbpool.queue, hb); 2303 card->hbpool.count++; 2304 } else 2305 dev_kfree_skb_any(hb); 2306 atomic_inc(&vcc->stats->rx_drop); 2307 } else { 2308 /* Copy the small buffer to the huge buffer */ 2309 sb = (struct sk_buff *)iov->iov_base; 2310 skb_copy_from_linear_data(sb, hb->data, 2311 iov->iov_len); 2312 skb_put(hb, iov->iov_len); 2313 remaining = len - iov->iov_len; 2314 iov++; 2315 /* Free the small buffer */ 2316 push_rxbufs(card, sb); 2317 2318 /* Copy all large buffers to the huge buffer and free them */ 2319 for (j = 1; j < NS_PRV_IOVCNT(iovb); j++) { 2320 lb = (struct sk_buff *)iov->iov_base; 2321 tocopy = 2322 min_t(int, remaining, iov->iov_len); 2323 skb_copy_from_linear_data(lb, 2324 skb_tail_pointer 2325 (hb), tocopy); 2326 skb_put(hb, tocopy); 2327 iov++; 2328 remaining -= tocopy; 2329 push_rxbufs(card, lb); 2330 } 2331#ifdef EXTRA_DEBUG 2332 if (remaining != 0 || hb->len != len) 2333 printk 2334 ("nicstar%d: Huge buffer len mismatch.\n", 2335 card->index); 2336#endif /* EXTRA_DEBUG */ 2337 ATM_SKB(hb)->vcc = vcc; 2338#ifdef NS_USE_DESTRUCTORS 2339 hb->destructor = ns_hb_destructor; 2340#endif /* NS_USE_DESTRUCTORS */ 2341 __net_timestamp(hb); 2342 vcc->push(vcc, hb); 2343 atomic_inc(&vcc->stats->rx); 2344 } 2345 } 2346 2347 vc->rx_iov = NULL; 2348 recycle_iov_buf(card, iovb); 2349 } 2350 2351} 2352 2353#ifdef NS_USE_DESTRUCTORS 2354 2355static void ns_sb_destructor(struct sk_buff *sb) 2356{ 2357 ns_dev *card; 2358 u32 stat; 2359 2360 card = (ns_dev *) ATM_SKB(sb)->vcc->dev->dev_data; 2361 stat = readl(card->membase + STAT); 2362 card->sbfqc = ns_stat_sfbqc_get(stat); 2363 card->lbfqc = ns_stat_lfbqc_get(stat); 2364 2365 do { 2366 sb = __dev_alloc_skb(NS_SMSKBSIZE, GFP_KERNEL); 2367 if (sb == NULL) 2368 break; 2369 NS_PRV_BUFTYPE(sb) = BUF_SM; 2370 skb_queue_tail(&card->sbpool.queue, sb); 2371 skb_reserve(sb, NS_AAL0_HEADER); 2372 push_rxbufs(card, sb); 2373 } while (card->sbfqc < card->sbnr.min); 2374} 2375 2376static void ns_lb_destructor(struct sk_buff *lb) 2377{ 2378 ns_dev *card; 2379 u32 stat; 2380 2381 card = (ns_dev *) ATM_SKB(lb)->vcc->dev->dev_data; 2382 stat = readl(card->membase + STAT); 2383 card->sbfqc = ns_stat_sfbqc_get(stat); 2384 card->lbfqc = ns_stat_lfbqc_get(stat); 2385 2386 do { 2387 lb = __dev_alloc_skb(NS_LGSKBSIZE, GFP_KERNEL); 2388 if (lb == NULL) 2389 break; 2390 NS_PRV_BUFTYPE(lb) = BUF_LG; 2391 skb_queue_tail(&card->lbpool.queue, lb); 2392 skb_reserve(lb, NS_SMBUFSIZE); 2393 push_rxbufs(card, lb); 2394 } while (card->lbfqc < card->lbnr.min); 2395} 2396 2397static void ns_hb_destructor(struct sk_buff *hb) 2398{ 2399 ns_dev *card; 2400 2401 card = (ns_dev *) ATM_SKB(hb)->vcc->dev->dev_data; 2402 2403 while (card->hbpool.count < card->hbnr.init) { 2404 hb = __dev_alloc_skb(NS_HBUFSIZE, GFP_KERNEL); 2405 if (hb == NULL) 2406 break; 2407 NS_PRV_BUFTYPE(hb) = BUF_NONE; 2408 skb_queue_tail(&card->hbpool.queue, hb); 2409 card->hbpool.count++; 2410 } 2411} 2412 2413#endif /* NS_USE_DESTRUCTORS */ 2414 2415static void recycle_rx_buf(ns_dev * card, struct sk_buff *skb) 2416{ 2417 if (unlikely(NS_PRV_BUFTYPE(skb) == BUF_NONE)) { 2418 printk("nicstar%d: What kind of rx buffer is this?\n", 2419 card->index); 2420 dev_kfree_skb_any(skb); 2421 } else 2422 push_rxbufs(card, skb); 2423} 2424 2425static void recycle_iovec_rx_bufs(ns_dev * card, struct iovec *iov, int count) 2426{ 2427 while (count-- > 0) 2428 recycle_rx_buf(card, (struct sk_buff *)(iov++)->iov_base); 2429} 2430 2431static void recycle_iov_buf(ns_dev * card, struct sk_buff *iovb) 2432{ 2433 if (card->iovpool.count < card->iovnr.max) { 2434 skb_queue_tail(&card->iovpool.queue, iovb); 2435 card->iovpool.count++; 2436 } else 2437 dev_kfree_skb_any(iovb); 2438} 2439 2440static void dequeue_sm_buf(ns_dev * card, struct sk_buff *sb) 2441{ 2442 skb_unlink(sb, &card->sbpool.queue); 2443#ifdef NS_USE_DESTRUCTORS 2444 if (card->sbfqc < card->sbnr.min) 2445#else 2446 if (card->sbfqc < card->sbnr.init) { 2447 struct sk_buff *new_sb; 2448 if ((new_sb = dev_alloc_skb(NS_SMSKBSIZE)) != NULL) { 2449 NS_PRV_BUFTYPE(new_sb) = BUF_SM; 2450 skb_queue_tail(&card->sbpool.queue, new_sb); 2451 skb_reserve(new_sb, NS_AAL0_HEADER); 2452 push_rxbufs(card, new_sb); 2453 } 2454 } 2455 if (card->sbfqc < card->sbnr.init) 2456#endif /* NS_USE_DESTRUCTORS */ 2457 { 2458 struct sk_buff *new_sb; 2459 if ((new_sb = dev_alloc_skb(NS_SMSKBSIZE)) != NULL) { 2460 NS_PRV_BUFTYPE(new_sb) = BUF_SM; 2461 skb_queue_tail(&card->sbpool.queue, new_sb); 2462 skb_reserve(new_sb, NS_AAL0_HEADER); 2463 push_rxbufs(card, new_sb); 2464 } 2465 } 2466} 2467 2468static void dequeue_lg_buf(ns_dev * card, struct sk_buff *lb) 2469{ 2470 skb_unlink(lb, &card->lbpool.queue); 2471#ifdef NS_USE_DESTRUCTORS 2472 if (card->lbfqc < card->lbnr.min) 2473#else 2474 if (card->lbfqc < card->lbnr.init) { 2475 struct sk_buff *new_lb; 2476 if ((new_lb = dev_alloc_skb(NS_LGSKBSIZE)) != NULL) { 2477 NS_PRV_BUFTYPE(new_lb) = BUF_LG; 2478 skb_queue_tail(&card->lbpool.queue, new_lb); 2479 skb_reserve(new_lb, NS_SMBUFSIZE); 2480 push_rxbufs(card, new_lb); 2481 } 2482 } 2483 if (card->lbfqc < card->lbnr.init) 2484#endif /* NS_USE_DESTRUCTORS */ 2485 { 2486 struct sk_buff *new_lb; 2487 if ((new_lb = dev_alloc_skb(NS_LGSKBSIZE)) != NULL) { 2488 NS_PRV_BUFTYPE(new_lb) = BUF_LG; 2489 skb_queue_tail(&card->lbpool.queue, new_lb); 2490 skb_reserve(new_lb, NS_SMBUFSIZE); 2491 push_rxbufs(card, new_lb); 2492 } 2493 } 2494} 2495 2496static int ns_proc_read(struct atm_dev *dev, loff_t * pos, char *page) 2497{ 2498 u32 stat; 2499 ns_dev *card; 2500 int left; 2501 2502 left = (int)*pos; 2503 card = (ns_dev *) dev->dev_data; 2504 stat = readl(card->membase + STAT); 2505 if (!left--) 2506 return sprintf(page, "Pool count min init max \n"); 2507 if (!left--) 2508 return sprintf(page, "Small %5d %5d %5d %5d \n", 2509 ns_stat_sfbqc_get(stat), card->sbnr.min, 2510 card->sbnr.init, card->sbnr.max); 2511 if (!left--) 2512 return sprintf(page, "Large %5d %5d %5d %5d \n", 2513 ns_stat_lfbqc_get(stat), card->lbnr.min, 2514 card->lbnr.init, card->lbnr.max); 2515 if (!left--) 2516 return sprintf(page, "Huge %5d %5d %5d %5d \n", 2517 card->hbpool.count, card->hbnr.min, 2518 card->hbnr.init, card->hbnr.max); 2519 if (!left--) 2520 return sprintf(page, "Iovec %5d %5d %5d %5d \n", 2521 card->iovpool.count, card->iovnr.min, 2522 card->iovnr.init, card->iovnr.max); 2523 if (!left--) { 2524 int retval; 2525 retval = 2526 sprintf(page, "Interrupt counter: %u \n", card->intcnt); 2527 card->intcnt = 0; 2528 return retval; 2529 } 2530 return 0; 2531} 2532 2533static int ns_ioctl(struct atm_dev *dev, unsigned int cmd, void __user * arg) 2534{ 2535 ns_dev *card; 2536 pool_levels pl; 2537 long btype; 2538 unsigned long flags; 2539 2540 card = dev->dev_data; 2541 switch (cmd) { 2542 case NS_GETPSTAT: 2543 if (get_user 2544 (pl.buftype, &((pool_levels __user *) arg)->buftype)) 2545 return -EFAULT; 2546 switch (pl.buftype) { 2547 case NS_BUFTYPE_SMALL: 2548 pl.count = 2549 ns_stat_sfbqc_get(readl(card->membase + STAT)); 2550 pl.level.min = card->sbnr.min; 2551 pl.level.init = card->sbnr.init; 2552 pl.level.max = card->sbnr.max; 2553 break; 2554 2555 case NS_BUFTYPE_LARGE: 2556 pl.count = 2557 ns_stat_lfbqc_get(readl(card->membase + STAT)); 2558 pl.level.min = card->lbnr.min; 2559 pl.level.init = card->lbnr.init; 2560 pl.level.max = card->lbnr.max; 2561 break; 2562 2563 case NS_BUFTYPE_HUGE: 2564 pl.count = card->hbpool.count; 2565 pl.level.min = card->hbnr.min; 2566 pl.level.init = card->hbnr.init; 2567 pl.level.max = card->hbnr.max; 2568 break; 2569 2570 case NS_BUFTYPE_IOVEC: 2571 pl.count = card->iovpool.count; 2572 pl.level.min = card->iovnr.min; 2573 pl.level.init = card->iovnr.init; 2574 pl.level.max = card->iovnr.max; 2575 break; 2576 2577 default: 2578 return -ENOIOCTLCMD; 2579 2580 } 2581 if (!copy_to_user((pool_levels __user *) arg, &pl, sizeof(pl))) 2582 return (sizeof(pl)); 2583 else 2584 return -EFAULT; 2585 2586 case NS_SETBUFLEV: 2587 if (!capable(CAP_NET_ADMIN)) 2588 return -EPERM; 2589 if (copy_from_user(&pl, (pool_levels __user *) arg, sizeof(pl))) 2590 return -EFAULT; 2591 if (pl.level.min >= pl.level.init 2592 || pl.level.init >= pl.level.max) 2593 return -EINVAL; 2594 if (pl.level.min == 0) 2595 return -EINVAL; 2596 switch (pl.buftype) { 2597 case NS_BUFTYPE_SMALL: 2598 if (pl.level.max > TOP_SB) 2599 return -EINVAL; 2600 card->sbnr.min = pl.level.min; 2601 card->sbnr.init = pl.level.init; 2602 card->sbnr.max = pl.level.max; 2603 break; 2604 2605 case NS_BUFTYPE_LARGE: 2606 if (pl.level.max > TOP_LB) 2607 return -EINVAL; 2608 card->lbnr.min = pl.level.min; 2609 card->lbnr.init = pl.level.init; 2610 card->lbnr.max = pl.level.max; 2611 break; 2612 2613 case NS_BUFTYPE_HUGE: 2614 if (pl.level.max > TOP_HB) 2615 return -EINVAL; 2616 card->hbnr.min = pl.level.min; 2617 card->hbnr.init = pl.level.init; 2618 card->hbnr.max = pl.level.max; 2619 break; 2620 2621 case NS_BUFTYPE_IOVEC: 2622 if (pl.level.max > TOP_IOVB) 2623 return -EINVAL; 2624 card->iovnr.min = pl.level.min; 2625 card->iovnr.init = pl.level.init; 2626 card->iovnr.max = pl.level.max; 2627 break; 2628 2629 default: 2630 return -EINVAL; 2631 2632 } 2633 return 0; 2634 2635 case NS_ADJBUFLEV: 2636 if (!capable(CAP_NET_ADMIN)) 2637 return -EPERM; 2638 btype = (long)arg; /* a long is the same size as a pointer or bigger */ 2639 switch (btype) { 2640 case NS_BUFTYPE_SMALL: 2641 while (card->sbfqc < card->sbnr.init) { 2642 struct sk_buff *sb; 2643 2644 sb = __dev_alloc_skb(NS_SMSKBSIZE, GFP_KERNEL); 2645 if (sb == NULL) 2646 return -ENOMEM; 2647 NS_PRV_BUFTYPE(sb) = BUF_SM; 2648 skb_queue_tail(&card->sbpool.queue, sb); 2649 skb_reserve(sb, NS_AAL0_HEADER); 2650 push_rxbufs(card, sb); 2651 } 2652 break; 2653 2654 case NS_BUFTYPE_LARGE: 2655 while (card->lbfqc < card->lbnr.init) { 2656 struct sk_buff *lb; 2657 2658 lb = __dev_alloc_skb(NS_LGSKBSIZE, GFP_KERNEL); 2659 if (lb == NULL) 2660 return -ENOMEM; 2661 NS_PRV_BUFTYPE(lb) = BUF_LG; 2662 skb_queue_tail(&card->lbpool.queue, lb); 2663 skb_reserve(lb, NS_SMBUFSIZE); 2664 push_rxbufs(card, lb); 2665 } 2666 break; 2667 2668 case NS_BUFTYPE_HUGE: 2669 while (card->hbpool.count > card->hbnr.init) { 2670 struct sk_buff *hb; 2671 2672 spin_lock_irqsave(&card->int_lock, flags); 2673 hb = skb_dequeue(&card->hbpool.queue); 2674 card->hbpool.count--; 2675 spin_unlock_irqrestore(&card->int_lock, flags); 2676 if (hb == NULL) 2677 printk 2678 ("nicstar%d: huge buffer count inconsistent.\n", 2679 card->index); 2680 else 2681 dev_kfree_skb_any(hb); 2682 2683 } 2684 while (card->hbpool.count < card->hbnr.init) { 2685 struct sk_buff *hb; 2686 2687 hb = __dev_alloc_skb(NS_HBUFSIZE, GFP_KERNEL); 2688 if (hb == NULL) 2689 return -ENOMEM; 2690 NS_PRV_BUFTYPE(hb) = BUF_NONE; 2691 spin_lock_irqsave(&card->int_lock, flags); 2692 skb_queue_tail(&card->hbpool.queue, hb); 2693 card->hbpool.count++; 2694 spin_unlock_irqrestore(&card->int_lock, flags); 2695 } 2696 break; 2697 2698 case NS_BUFTYPE_IOVEC: 2699 while (card->iovpool.count > card->iovnr.init) { 2700 struct sk_buff *iovb; 2701 2702 spin_lock_irqsave(&card->int_lock, flags); 2703 iovb = skb_dequeue(&card->iovpool.queue); 2704 card->iovpool.count--; 2705 spin_unlock_irqrestore(&card->int_lock, flags); 2706 if (iovb == NULL) 2707 printk 2708 ("nicstar%d: iovec buffer count inconsistent.\n", 2709 card->index); 2710 else 2711 dev_kfree_skb_any(iovb); 2712 2713 } 2714 while (card->iovpool.count < card->iovnr.init) { 2715 struct sk_buff *iovb; 2716 2717 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_KERNEL); 2718 if (iovb == NULL) 2719 return -ENOMEM; 2720 NS_PRV_BUFTYPE(iovb) = BUF_NONE; 2721 spin_lock_irqsave(&card->int_lock, flags); 2722 skb_queue_tail(&card->iovpool.queue, iovb); 2723 card->iovpool.count++; 2724 spin_unlock_irqrestore(&card->int_lock, flags); 2725 } 2726 break; 2727 2728 default: 2729 return -EINVAL; 2730 2731 } 2732 return 0; 2733 2734 default: 2735 if (dev->phy && dev->phy->ioctl) { 2736 return dev->phy->ioctl(dev, cmd, arg); 2737 } else { 2738 printk("nicstar%d: %s == NULL \n", card->index, 2739 dev->phy ? "dev->phy->ioctl" : "dev->phy"); 2740 return -ENOIOCTLCMD; 2741 } 2742 } 2743} 2744 2745#ifdef EXTRA_DEBUG 2746static void which_list(ns_dev * card, struct sk_buff *skb) 2747{ 2748 printk("skb buf_type: 0x%08x\n", NS_PRV_BUFTYPE(skb)); 2749} 2750#endif /* EXTRA_DEBUG */ 2751 2752static void ns_poll(unsigned long arg) 2753{ 2754 int i; 2755 ns_dev *card; 2756 unsigned long flags; 2757 u32 stat_r, stat_w; 2758 2759 PRINTK("nicstar: Entering ns_poll().\n"); 2760 for (i = 0; i < num_cards; i++) { 2761 card = cards[i]; 2762 if (spin_is_locked(&card->int_lock)) { 2763 /* Probably it isn't worth spinning */ 2764 continue; 2765 } 2766 spin_lock_irqsave(&card->int_lock, flags); 2767 2768 stat_w = 0; 2769 stat_r = readl(card->membase + STAT); 2770 if (stat_r & NS_STAT_TSIF) 2771 stat_w |= NS_STAT_TSIF; 2772 if (stat_r & NS_STAT_EOPDU) 2773 stat_w |= NS_STAT_EOPDU; 2774 2775 process_tsq(card); 2776 process_rsq(card); 2777 2778 writel(stat_w, card->membase + STAT); 2779 spin_unlock_irqrestore(&card->int_lock, flags); 2780 } 2781 mod_timer(&ns_timer, jiffies + NS_POLL_PERIOD); 2782 PRINTK("nicstar: Leaving ns_poll().\n"); 2783} 2784 2785static int ns_parse_mac(char *mac, unsigned char *esi) 2786{ 2787 int i, j; 2788 short byte1, byte0; 2789 2790 if (mac == NULL || esi == NULL) 2791 return -1; 2792 j = 0; 2793 for (i = 0; i < 6; i++) { 2794 if ((byte1 = hex_to_bin(mac[j++])) < 0) 2795 return -1; 2796 if ((byte0 = hex_to_bin(mac[j++])) < 0) 2797 return -1; 2798 esi[i] = (unsigned char)(byte1 * 16 + byte0); 2799 if (i < 5) { 2800 if (mac[j++] != ':') 2801 return -1; 2802 } 2803 } 2804 return 0; 2805} 2806 2807 2808static void ns_phy_put(struct atm_dev *dev, unsigned char value, 2809 unsigned long addr) 2810{ 2811 ns_dev *card; 2812 unsigned long flags; 2813 2814 card = dev->dev_data; 2815 spin_lock_irqsave(&card->res_lock, flags); 2816 while (CMD_BUSY(card)) ; 2817 writel((u32) value, card->membase + DR0); 2818 writel(NS_CMD_WRITE_UTILITY | 0x00000200 | (addr & 0x000000FF), 2819 card->membase + CMD); 2820 spin_unlock_irqrestore(&card->res_lock, flags); 2821} 2822 2823static unsigned char ns_phy_get(struct atm_dev *dev, unsigned long addr) 2824{ 2825 ns_dev *card; 2826 unsigned long flags; 2827 u32 data; 2828 2829 card = dev->dev_data; 2830 spin_lock_irqsave(&card->res_lock, flags); 2831 while (CMD_BUSY(card)) ; 2832 writel(NS_CMD_READ_UTILITY | 0x00000200 | (addr & 0x000000FF), 2833 card->membase + CMD); 2834 while (CMD_BUSY(card)) ; 2835 data = readl(card->membase + DR0) & 0x000000FF; 2836 spin_unlock_irqrestore(&card->res_lock, flags); 2837 return (unsigned char)data; 2838} 2839 2840module_init(nicstar_init); 2841module_exit(nicstar_cleanup); 2842