1/* 2 * ata_piix.c - Intel PATA/SATA controllers 3 * 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com> 5 * Please ALWAYS copy linux-ide@vger.kernel.org 6 * on emails. 7 * 8 * 9 * Copyright 2003-2005 Red Hat Inc 10 * Copyright 2003-2005 Jeff Garzik 11 * 12 * 13 * Copyright header from piix.c: 14 * 15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer 16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> 17 * Copyright (C) 2003 Red Hat Inc 18 * 19 * 20 * This program is free software; you can redistribute it and/or modify 21 * it under the terms of the GNU General Public License as published by 22 * the Free Software Foundation; either version 2, or (at your option) 23 * any later version. 24 * 25 * This program is distributed in the hope that it will be useful, 26 * but WITHOUT ANY WARRANTY; without even the implied warranty of 27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 28 * GNU General Public License for more details. 29 * 30 * You should have received a copy of the GNU General Public License 31 * along with this program; see the file COPYING. If not, write to 32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 33 * 34 * 35 * libata documentation is available via 'make {ps|pdf}docs', 36 * as Documentation/DocBook/libata.* 37 * 38 * Hardware documentation available at http://developer.intel.com/ 39 * 40 * Documentation 41 * Publically available from Intel web site. Errata documentation 42 * is also publically available. As an aide to anyone hacking on this 43 * driver the list of errata that are relevant is below, going back to 44 * PIIX4. Older device documentation is now a bit tricky to find. 45 * 46 * The chipsets all follow very much the same design. The original Triton 47 * series chipsets do _not_ support independant device timings, but this 48 * is fixed in Triton II. With the odd mobile exception the chips then 49 * change little except in gaining more modes until SATA arrives. This 50 * driver supports only the chips with independant timing (that is those 51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix 52 * for the early chip drivers. 53 * 54 * Errata of note: 55 * 56 * Unfixable 57 * PIIX4 errata #9 - Only on ultra obscure hw 58 * ICH3 errata #13 - Not observed to affect real hw 59 * by Intel 60 * 61 * Things we must deal with 62 * PIIX4 errata #10 - BM IDE hang with non UDMA 63 * (must stop/start dma to recover) 64 * 440MX errata #15 - As PIIX4 errata #10 65 * PIIX4 errata #15 - Must not read control registers 66 * during a PIO transfer 67 * 440MX errata #13 - As PIIX4 errata #15 68 * ICH2 errata #21 - DMA mode 0 doesn't work right 69 * ICH0/1 errata #55 - As ICH2 errata #21 70 * ICH2 spec c #9 - Extra operations needed to handle 71 * drive hotswap [NOT YET SUPPORTED] 72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary 73 * and must be dword aligned 74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3 75 * ICH7 errata #16 - MWDMA1 timings are incorrect 76 * 77 * Should have been BIOS fixed: 78 * 450NX: errata #19 - DMA hangs on old 450NX 79 * 450NX: errata #20 - DMA hangs on old 450NX 80 * 450NX: errata #25 - Corruption with DMA on old 450NX 81 * ICH3 errata #15 - IDE deadlock under high load 82 * (BIOS must set dev 31 fn 0 bit 23) 83 * ICH3 errata #18 - Don't use native mode 84 */ 85 86#include <linux/kernel.h> 87#include <linux/module.h> 88#include <linux/pci.h> 89#include <linux/init.h> 90#include <linux/blkdev.h> 91#include <linux/delay.h> 92#include <linux/device.h> 93#include <linux/gfp.h> 94#include <scsi/scsi_host.h> 95#include <linux/libata.h> 96#include <linux/dmi.h> 97 98#define DRV_NAME "ata_piix" 99#define DRV_VERSION "2.13" 100 101enum { 102 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */ 103 ICH5_PMR = 0x90, /* port mapping register */ 104 ICH5_PCS = 0x92, /* port control and status */ 105 PIIX_SIDPR_BAR = 5, 106 PIIX_SIDPR_LEN = 16, 107 PIIX_SIDPR_IDX = 0, 108 PIIX_SIDPR_DATA = 4, 109 110 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */ 111 PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */ 112 113 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS, 114 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR, 115 116 PIIX_80C_PRI = (1 << 5) | (1 << 4), 117 PIIX_80C_SEC = (1 << 7) | (1 << 6), 118 119 /* constants for mapping table */ 120 P0 = 0, /* port 0 */ 121 P1 = 1, /* port 1 */ 122 P2 = 2, /* port 2 */ 123 P3 = 3, /* port 3 */ 124 IDE = -1, /* IDE */ 125 NA = -2, /* not avaliable */ 126 RV = -3, /* reserved */ 127 128 PIIX_AHCI_DEVICE = 6, 129 130 /* host->flags bits */ 131 PIIX_HOST_BROKEN_SUSPEND = (1 << 24), 132}; 133 134enum piix_controller_ids { 135 /* controller IDs */ 136 piix_pata_mwdma, /* PIIX3 MWDMA only */ 137 piix_pata_33, /* PIIX4 at 33Mhz */ 138 ich_pata_33, /* ICH up to UDMA 33 only */ 139 ich_pata_66, /* ICH up to 66 Mhz */ 140 ich_pata_100, /* ICH up to UDMA 100 */ 141 ich_pata_100_nomwdma1, /* ICH up to UDMA 100 but with no MWDMA1*/ 142 ich5_sata, 143 ich6_sata, 144 ich6m_sata, 145 ich8_sata, 146 ich8_2port_sata, 147 ich8m_apple_sata, /* locks up on second port enable */ 148 tolapai_sata, 149 piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */ 150}; 151 152struct piix_map_db { 153 const u32 mask; 154 const u16 port_enable; 155 const int map[][4]; 156}; 157 158struct piix_host_priv { 159 const int *map; 160 u32 saved_iocfg; 161 spinlock_t sidpr_lock; 162 void __iomem *sidpr; 163}; 164 165static int piix_init_one(struct pci_dev *pdev, 166 const struct pci_device_id *ent); 167static void piix_remove_one(struct pci_dev *pdev); 168static int piix_pata_prereset(struct ata_link *link, unsigned long deadline); 169static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev); 170static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev); 171static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev); 172static int ich_pata_cable_detect(struct ata_port *ap); 173static u8 piix_vmw_bmdma_status(struct ata_port *ap); 174static int piix_sidpr_scr_read(struct ata_link *link, 175 unsigned int reg, u32 *val); 176static int piix_sidpr_scr_write(struct ata_link *link, 177 unsigned int reg, u32 val); 178static bool piix_irq_check(struct ata_port *ap); 179#ifdef CONFIG_PM 180static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); 181static int piix_pci_device_resume(struct pci_dev *pdev); 182#endif 183 184static unsigned int in_module_init = 1; 185 186static const struct pci_device_id piix_pci_tbl[] = { 187 /* Intel PIIX3 for the 430HX etc */ 188 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma }, 189 /* VMware ICH4 */ 190 { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw }, 191 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */ 192 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */ 193 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 194 /* Intel PIIX4 */ 195 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 196 /* Intel PIIX4 */ 197 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 198 /* Intel PIIX */ 199 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 200 /* Intel ICH (i810, i815, i840) UDMA 66*/ 201 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 }, 202 /* Intel ICH0 : UDMA 33*/ 203 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 }, 204 /* Intel ICH2M */ 205 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 206 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */ 207 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 208 /* Intel ICH3M */ 209 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 210 /* Intel ICH3 (E7500/1) UDMA 100 */ 211 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 212 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */ 213 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 214 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 215 /* Intel ICH5 */ 216 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 217 /* C-ICH (i810E2) */ 218 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 219 /* ESB (855GME/875P + 6300ESB) UDMA 100 */ 220 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 221 /* ICH6 (and 6) (i915) UDMA 100 */ 222 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 223 /* ICH7/7-R (i945, i975) UDMA 100*/ 224 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 }, 225 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 }, 226 /* ICH8 Mobile PATA Controller */ 227 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 228 229 /* SATA ports */ 230 231 /* 82801EB (ICH5) */ 232 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 233 /* 82801EB (ICH5) */ 234 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 235 /* 6300ESB (ICH5 variant with broken PCS present bits) */ 236 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 237 /* 6300ESB pretending RAID */ 238 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 239 /* 82801FB/FW (ICH6/ICH6W) */ 240 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, 241 /* 82801FR/FRW (ICH6R/ICH6RW) */ 242 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, 243 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented). 244 * Attach iff the controller is in IDE mode. */ 245 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 246 PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata }, 247 /* 82801GB/GR/GH (ICH7, identical to ICH6) */ 248 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, 249 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */ 250 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata }, 251 /* Enterprise Southbridge 2 (631xESB/632xESB) */ 252 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, 253 /* SATA Controller 1 IDE (ICH8) */ 254 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 255 /* SATA Controller 2 IDE (ICH8) */ 256 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 257 /* Mobile SATA Controller IDE (ICH8M), Apple */ 258 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata }, 259 { 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata }, 260 { 0x8086, 0x2828, 0x106b, 0x00a3, 0, 0, ich8m_apple_sata }, 261 /* Mobile SATA Controller IDE (ICH8M) */ 262 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 263 /* SATA Controller IDE (ICH9) */ 264 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 265 /* SATA Controller IDE (ICH9) */ 266 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 267 /* SATA Controller IDE (ICH9) */ 268 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 269 /* SATA Controller IDE (ICH9M) */ 270 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 271 /* SATA Controller IDE (ICH9M) */ 272 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 273 /* SATA Controller IDE (ICH9M) */ 274 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 275 /* SATA Controller IDE (Tolapai) */ 276 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata }, 277 /* SATA Controller IDE (ICH10) */ 278 { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 279 /* SATA Controller IDE (ICH10) */ 280 { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 281 /* SATA Controller IDE (ICH10) */ 282 { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 283 /* SATA Controller IDE (ICH10) */ 284 { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 285 /* SATA Controller IDE (PCH) */ 286 { 0x8086, 0x3b20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 287 /* SATA Controller IDE (PCH) */ 288 { 0x8086, 0x3b21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 289 /* SATA Controller IDE (PCH) */ 290 { 0x8086, 0x3b26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 291 /* SATA Controller IDE (PCH) */ 292 { 0x8086, 0x3b28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 293 /* SATA Controller IDE (PCH) */ 294 { 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 295 /* SATA Controller IDE (PCH) */ 296 { 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 297 /* SATA Controller IDE (CPT) */ 298 { 0x8086, 0x1c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 299 /* SATA Controller IDE (CPT) */ 300 { 0x8086, 0x1c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 301 /* SATA Controller IDE (CPT) */ 302 { 0x8086, 0x1c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 303 /* SATA Controller IDE (CPT) */ 304 { 0x8086, 0x1c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 305 /* SATA Controller IDE (PBG) */ 306 { 0x8086, 0x1d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 307 /* SATA Controller IDE (PBG) */ 308 { 0x8086, 0x1d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 309 { } /* terminate list */ 310}; 311 312static struct pci_driver piix_pci_driver = { 313 .name = DRV_NAME, 314 .id_table = piix_pci_tbl, 315 .probe = piix_init_one, 316 .remove = piix_remove_one, 317#ifdef CONFIG_PM 318 .suspend = piix_pci_device_suspend, 319 .resume = piix_pci_device_resume, 320#endif 321}; 322 323static struct scsi_host_template piix_sht = { 324 ATA_BMDMA_SHT(DRV_NAME), 325}; 326 327static struct ata_port_operations piix_sata_ops = { 328 .inherits = &ata_bmdma32_port_ops, 329 .sff_irq_check = piix_irq_check, 330}; 331 332static struct ata_port_operations piix_pata_ops = { 333 .inherits = &piix_sata_ops, 334 .cable_detect = ata_cable_40wire, 335 .set_piomode = piix_set_piomode, 336 .set_dmamode = piix_set_dmamode, 337 .prereset = piix_pata_prereset, 338}; 339 340static struct ata_port_operations piix_vmw_ops = { 341 .inherits = &piix_pata_ops, 342 .bmdma_status = piix_vmw_bmdma_status, 343}; 344 345static struct ata_port_operations ich_pata_ops = { 346 .inherits = &piix_pata_ops, 347 .cable_detect = ich_pata_cable_detect, 348 .set_dmamode = ich_set_dmamode, 349}; 350 351static struct ata_port_operations piix_sidpr_sata_ops = { 352 .inherits = &piix_sata_ops, 353 .hardreset = sata_std_hardreset, 354 .scr_read = piix_sidpr_scr_read, 355 .scr_write = piix_sidpr_scr_write, 356}; 357 358static const struct piix_map_db ich5_map_db = { 359 .mask = 0x7, 360 .port_enable = 0x3, 361 .map = { 362 /* PM PS SM SS MAP */ 363 { P0, NA, P1, NA }, /* 000b */ 364 { P1, NA, P0, NA }, /* 001b */ 365 { RV, RV, RV, RV }, 366 { RV, RV, RV, RV }, 367 { P0, P1, IDE, IDE }, /* 100b */ 368 { P1, P0, IDE, IDE }, /* 101b */ 369 { IDE, IDE, P0, P1 }, /* 110b */ 370 { IDE, IDE, P1, P0 }, /* 111b */ 371 }, 372}; 373 374static const struct piix_map_db ich6_map_db = { 375 .mask = 0x3, 376 .port_enable = 0xf, 377 .map = { 378 /* PM PS SM SS MAP */ 379 { P0, P2, P1, P3 }, /* 00b */ 380 { IDE, IDE, P1, P3 }, /* 01b */ 381 { P0, P2, IDE, IDE }, /* 10b */ 382 { RV, RV, RV, RV }, 383 }, 384}; 385 386static const struct piix_map_db ich6m_map_db = { 387 .mask = 0x3, 388 .port_enable = 0x5, 389 390 /* Map 01b isn't specified in the doc but some notebooks use 391 * it anyway. MAP 01b have been spotted on both ICH6M and 392 * ICH7M. 393 */ 394 .map = { 395 /* PM PS SM SS MAP */ 396 { P0, P2, NA, NA }, /* 00b */ 397 { IDE, IDE, P1, P3 }, /* 01b */ 398 { P0, P2, IDE, IDE }, /* 10b */ 399 { RV, RV, RV, RV }, 400 }, 401}; 402 403static const struct piix_map_db ich8_map_db = { 404 .mask = 0x3, 405 .port_enable = 0xf, 406 .map = { 407 /* PM PS SM SS MAP */ 408 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */ 409 { RV, RV, RV, RV }, 410 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */ 411 { RV, RV, RV, RV }, 412 }, 413}; 414 415static const struct piix_map_db ich8_2port_map_db = { 416 .mask = 0x3, 417 .port_enable = 0x3, 418 .map = { 419 /* PM PS SM SS MAP */ 420 { P0, NA, P1, NA }, /* 00b */ 421 { RV, RV, RV, RV }, /* 01b */ 422 { RV, RV, RV, RV }, /* 10b */ 423 { RV, RV, RV, RV }, 424 }, 425}; 426 427static const struct piix_map_db ich8m_apple_map_db = { 428 .mask = 0x3, 429 .port_enable = 0x1, 430 .map = { 431 /* PM PS SM SS MAP */ 432 { P0, NA, NA, NA }, /* 00b */ 433 { RV, RV, RV, RV }, 434 { P0, P2, IDE, IDE }, /* 10b */ 435 { RV, RV, RV, RV }, 436 }, 437}; 438 439static const struct piix_map_db tolapai_map_db = { 440 .mask = 0x3, 441 .port_enable = 0x3, 442 .map = { 443 /* PM PS SM SS MAP */ 444 { P0, NA, P1, NA }, /* 00b */ 445 { RV, RV, RV, RV }, /* 01b */ 446 { RV, RV, RV, RV }, /* 10b */ 447 { RV, RV, RV, RV }, 448 }, 449}; 450 451static const struct piix_map_db *piix_map_db_table[] = { 452 [ich5_sata] = &ich5_map_db, 453 [ich6_sata] = &ich6_map_db, 454 [ich6m_sata] = &ich6m_map_db, 455 [ich8_sata] = &ich8_map_db, 456 [ich8_2port_sata] = &ich8_2port_map_db, 457 [ich8m_apple_sata] = &ich8m_apple_map_db, 458 [tolapai_sata] = &tolapai_map_db, 459}; 460 461static struct ata_port_info piix_port_info[] = { 462 [piix_pata_mwdma] = /* PIIX3 MWDMA only */ 463 { 464 .flags = PIIX_PATA_FLAGS, 465 .pio_mask = ATA_PIO4, 466 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ 467 .port_ops = &piix_pata_ops, 468 }, 469 470 [piix_pata_33] = /* PIIX4 at 33MHz */ 471 { 472 .flags = PIIX_PATA_FLAGS, 473 .pio_mask = ATA_PIO4, 474 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ 475 .udma_mask = ATA_UDMA2, 476 .port_ops = &piix_pata_ops, 477 }, 478 479 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/ 480 { 481 .flags = PIIX_PATA_FLAGS, 482 .pio_mask = ATA_PIO4, 483 .mwdma_mask = ATA_MWDMA12_ONLY, /* Check: maybe MWDMA0 is ok */ 484 .udma_mask = ATA_UDMA2, 485 .port_ops = &ich_pata_ops, 486 }, 487 488 [ich_pata_66] = /* ICH controllers up to 66MHz */ 489 { 490 .flags = PIIX_PATA_FLAGS, 491 .pio_mask = ATA_PIO4, 492 .mwdma_mask = ATA_MWDMA12_ONLY, /* MWDMA0 is broken on chip */ 493 .udma_mask = ATA_UDMA4, 494 .port_ops = &ich_pata_ops, 495 }, 496 497 [ich_pata_100] = 498 { 499 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR, 500 .pio_mask = ATA_PIO4, 501 .mwdma_mask = ATA_MWDMA12_ONLY, 502 .udma_mask = ATA_UDMA5, 503 .port_ops = &ich_pata_ops, 504 }, 505 506 [ich_pata_100_nomwdma1] = 507 { 508 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR, 509 .pio_mask = ATA_PIO4, 510 .mwdma_mask = ATA_MWDMA2_ONLY, 511 .udma_mask = ATA_UDMA5, 512 .port_ops = &ich_pata_ops, 513 }, 514 515 [ich5_sata] = 516 { 517 .flags = PIIX_SATA_FLAGS, 518 .pio_mask = ATA_PIO4, 519 .mwdma_mask = ATA_MWDMA2, 520 .udma_mask = ATA_UDMA6, 521 .port_ops = &piix_sata_ops, 522 }, 523 524 [ich6_sata] = 525 { 526 .flags = PIIX_SATA_FLAGS, 527 .pio_mask = ATA_PIO4, 528 .mwdma_mask = ATA_MWDMA2, 529 .udma_mask = ATA_UDMA6, 530 .port_ops = &piix_sata_ops, 531 }, 532 533 [ich6m_sata] = 534 { 535 .flags = PIIX_SATA_FLAGS, 536 .pio_mask = ATA_PIO4, 537 .mwdma_mask = ATA_MWDMA2, 538 .udma_mask = ATA_UDMA6, 539 .port_ops = &piix_sata_ops, 540 }, 541 542 [ich8_sata] = 543 { 544 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR, 545 .pio_mask = ATA_PIO4, 546 .mwdma_mask = ATA_MWDMA2, 547 .udma_mask = ATA_UDMA6, 548 .port_ops = &piix_sata_ops, 549 }, 550 551 [ich8_2port_sata] = 552 { 553 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR, 554 .pio_mask = ATA_PIO4, 555 .mwdma_mask = ATA_MWDMA2, 556 .udma_mask = ATA_UDMA6, 557 .port_ops = &piix_sata_ops, 558 }, 559 560 [tolapai_sata] = 561 { 562 .flags = PIIX_SATA_FLAGS, 563 .pio_mask = ATA_PIO4, 564 .mwdma_mask = ATA_MWDMA2, 565 .udma_mask = ATA_UDMA6, 566 .port_ops = &piix_sata_ops, 567 }, 568 569 [ich8m_apple_sata] = 570 { 571 .flags = PIIX_SATA_FLAGS, 572 .pio_mask = ATA_PIO4, 573 .mwdma_mask = ATA_MWDMA2, 574 .udma_mask = ATA_UDMA6, 575 .port_ops = &piix_sata_ops, 576 }, 577 578 [piix_pata_vmw] = 579 { 580 .flags = PIIX_PATA_FLAGS, 581 .pio_mask = ATA_PIO4, 582 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ 583 .udma_mask = ATA_UDMA2, 584 .port_ops = &piix_vmw_ops, 585 }, 586 587}; 588 589static struct pci_bits piix_enable_bits[] = { 590 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */ 591 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */ 592}; 593 594MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik"); 595MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers"); 596MODULE_LICENSE("GPL"); 597MODULE_DEVICE_TABLE(pci, piix_pci_tbl); 598MODULE_VERSION(DRV_VERSION); 599 600struct ich_laptop { 601 u16 device; 602 u16 subvendor; 603 u16 subdevice; 604}; 605 606/* 607 * List of laptops that use short cables rather than 80 wire 608 */ 609 610static const struct ich_laptop ich_laptop[] = { 611 /* devid, subvendor, subdev */ 612 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */ 613 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */ 614 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */ 615 { 0x27DF, 0x1028, 0x02b0 }, /* ICH7 on unknown Dell */ 616 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */ 617 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */ 618 { 0x27DF, 0x103C, 0x361a }, /* ICH7 on unknown HP */ 619 { 0x27DF, 0x1071, 0xD221 }, /* ICH7 on Hercules EC-900 */ 620 { 0x27DF, 0x152D, 0x0778 }, /* ICH7 on unknown Intel */ 621 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */ 622 { 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */ 623 { 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */ 624 { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */ 625 { 0x27df, 0x104d, 0x900e }, /* ICH7 on Sony TZ-90 */ 626 /* end marker */ 627 { 0, } 628}; 629 630/** 631 * ich_pata_cable_detect - Probe host controller cable detect info 632 * @ap: Port for which cable detect info is desired 633 * 634 * Read 80c cable indicator from ATA PCI device's PCI config 635 * register. This register is normally set by firmware (BIOS). 636 * 637 * LOCKING: 638 * None (inherited from caller). 639 */ 640 641static int ich_pata_cable_detect(struct ata_port *ap) 642{ 643 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 644 struct piix_host_priv *hpriv = ap->host->private_data; 645 const struct ich_laptop *lap = &ich_laptop[0]; 646 u8 mask; 647 648 /* Check for specials - Acer Aspire 5602WLMi */ 649 while (lap->device) { 650 if (lap->device == pdev->device && 651 lap->subvendor == pdev->subsystem_vendor && 652 lap->subdevice == pdev->subsystem_device) 653 return ATA_CBL_PATA40_SHORT; 654 655 lap++; 656 } 657 658 /* check BIOS cable detect results */ 659 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC; 660 if ((hpriv->saved_iocfg & mask) == 0) 661 return ATA_CBL_PATA40; 662 return ATA_CBL_PATA80; 663} 664 665/** 666 * piix_pata_prereset - prereset for PATA host controller 667 * @link: Target link 668 * @deadline: deadline jiffies for the operation 669 * 670 * LOCKING: 671 * None (inherited from caller). 672 */ 673static int piix_pata_prereset(struct ata_link *link, unsigned long deadline) 674{ 675 struct ata_port *ap = link->ap; 676 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 677 678 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no])) 679 return -ENOENT; 680 return ata_sff_prereset(link, deadline); 681} 682 683static DEFINE_SPINLOCK(piix_lock); 684 685/** 686 * piix_set_piomode - Initialize host controller PATA PIO timings 687 * @ap: Port whose timings we are configuring 688 * @adev: um 689 * 690 * Set PIO mode for device, in host controller PCI config space. 691 * 692 * LOCKING: 693 * None (inherited from caller). 694 */ 695 696static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev) 697{ 698 struct pci_dev *dev = to_pci_dev(ap->host->dev); 699 unsigned long flags; 700 unsigned int pio = adev->pio_mode - XFER_PIO_0; 701 unsigned int is_slave = (adev->devno != 0); 702 unsigned int master_port= ap->port_no ? 0x42 : 0x40; 703 unsigned int slave_port = 0x44; 704 u16 master_data; 705 u8 slave_data; 706 u8 udma_enable; 707 int control = 0; 708 709 /* 710 * See Intel Document 298600-004 for the timing programing rules 711 * for ICH controllers. 712 */ 713 714 static const /* ISP RTC */ 715 u8 timings[][2] = { { 0, 0 }, 716 { 0, 0 }, 717 { 1, 0 }, 718 { 2, 1 }, 719 { 2, 3 }, }; 720 721 if (pio >= 2) 722 control |= 1; /* TIME1 enable */ 723 if (ata_pio_need_iordy(adev)) 724 control |= 2; /* IE enable */ 725 726 /* Intel specifies that the PPE functionality is for disk only */ 727 if (adev->class == ATA_DEV_ATA) 728 control |= 4; /* PPE enable */ 729 730 spin_lock_irqsave(&piix_lock, flags); 731 732 /* PIO configuration clears DTE unconditionally. It will be 733 * programmed in set_dmamode which is guaranteed to be called 734 * after set_piomode if any DMA mode is available. 735 */ 736 pci_read_config_word(dev, master_port, &master_data); 737 if (is_slave) { 738 /* clear TIME1|IE1|PPE1|DTE1 */ 739 master_data &= 0xff0f; 740 /* Enable SITRE (separate slave timing register) */ 741 master_data |= 0x4000; 742 /* enable PPE1, IE1 and TIME1 as needed */ 743 master_data |= (control << 4); 744 pci_read_config_byte(dev, slave_port, &slave_data); 745 slave_data &= (ap->port_no ? 0x0f : 0xf0); 746 /* Load the timing nibble for this slave */ 747 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) 748 << (ap->port_no ? 4 : 0); 749 } else { 750 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */ 751 master_data &= 0xccf0; 752 /* Enable PPE, IE and TIME as appropriate */ 753 master_data |= control; 754 /* load ISP and RCT */ 755 master_data |= 756 (timings[pio][0] << 12) | 757 (timings[pio][1] << 8); 758 } 759 pci_write_config_word(dev, master_port, master_data); 760 if (is_slave) 761 pci_write_config_byte(dev, slave_port, slave_data); 762 763 /* Ensure the UDMA bit is off - it will be turned back on if 764 UDMA is selected */ 765 766 if (ap->udma_mask) { 767 pci_read_config_byte(dev, 0x48, &udma_enable); 768 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno)); 769 pci_write_config_byte(dev, 0x48, udma_enable); 770 } 771 772 spin_unlock_irqrestore(&piix_lock, flags); 773} 774 775/** 776 * do_pata_set_dmamode - Initialize host controller PATA PIO timings 777 * @ap: Port whose timings we are configuring 778 * @adev: Drive in question 779 * @isich: set if the chip is an ICH device 780 * 781 * Set UDMA mode for device, in host controller PCI config space. 782 * 783 * LOCKING: 784 * None (inherited from caller). 785 */ 786 787static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich) 788{ 789 struct pci_dev *dev = to_pci_dev(ap->host->dev); 790 unsigned long flags; 791 u8 master_port = ap->port_no ? 0x42 : 0x40; 792 u16 master_data; 793 u8 speed = adev->dma_mode; 794 int devid = adev->devno + 2 * ap->port_no; 795 u8 udma_enable = 0; 796 797 static const /* ISP RTC */ 798 u8 timings[][2] = { { 0, 0 }, 799 { 0, 0 }, 800 { 1, 0 }, 801 { 2, 1 }, 802 { 2, 3 }, }; 803 804 spin_lock_irqsave(&piix_lock, flags); 805 806 pci_read_config_word(dev, master_port, &master_data); 807 if (ap->udma_mask) 808 pci_read_config_byte(dev, 0x48, &udma_enable); 809 810 if (speed >= XFER_UDMA_0) { 811 unsigned int udma = adev->dma_mode - XFER_UDMA_0; 812 u16 udma_timing; 813 u16 ideconf; 814 int u_clock, u_speed; 815 816 /* 817 * UDMA is handled by a combination of clock switching and 818 * selection of dividers 819 * 820 * Handy rule: Odd modes are UDMATIMx 01, even are 02 821 * except UDMA0 which is 00 822 */ 823 u_speed = min(2 - (udma & 1), udma); 824 if (udma == 5) 825 u_clock = 0x1000; /* 100Mhz */ 826 else if (udma > 2) 827 u_clock = 1; /* 66Mhz */ 828 else 829 u_clock = 0; /* 33Mhz */ 830 831 udma_enable |= (1 << devid); 832 833 /* Load the CT/RP selection */ 834 pci_read_config_word(dev, 0x4A, &udma_timing); 835 udma_timing &= ~(3 << (4 * devid)); 836 udma_timing |= u_speed << (4 * devid); 837 pci_write_config_word(dev, 0x4A, udma_timing); 838 839 if (isich) { 840 /* Select a 33/66/100Mhz clock */ 841 pci_read_config_word(dev, 0x54, &ideconf); 842 ideconf &= ~(0x1001 << devid); 843 ideconf |= u_clock << devid; 844 /* For ICH or later we should set bit 10 for better 845 performance (WR_PingPong_En) */ 846 pci_write_config_word(dev, 0x54, ideconf); 847 } 848 } else { 849 /* 850 * MWDMA is driven by the PIO timings. We must also enable 851 * IORDY unconditionally along with TIME1. PPE has already 852 * been set when the PIO timing was set. 853 */ 854 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0; 855 unsigned int control; 856 u8 slave_data; 857 const unsigned int needed_pio[3] = { 858 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 859 }; 860 int pio = needed_pio[mwdma] - XFER_PIO_0; 861 862 control = 3; /* IORDY|TIME1 */ 863 864 /* If the drive MWDMA is faster than it can do PIO then 865 we must force PIO into PIO0 */ 866 867 if (adev->pio_mode < needed_pio[mwdma]) 868 /* Enable DMA timing only */ 869 control |= 8; /* PIO cycles in PIO0 */ 870 871 if (adev->devno) { /* Slave */ 872 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */ 873 master_data |= control << 4; 874 pci_read_config_byte(dev, 0x44, &slave_data); 875 slave_data &= (ap->port_no ? 0x0f : 0xf0); 876 /* Load the matching timing */ 877 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0); 878 pci_write_config_byte(dev, 0x44, slave_data); 879 } else { /* Master */ 880 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY 881 and master timing bits */ 882 master_data |= control; 883 master_data |= 884 (timings[pio][0] << 12) | 885 (timings[pio][1] << 8); 886 } 887 888 if (ap->udma_mask) 889 udma_enable &= ~(1 << devid); 890 891 pci_write_config_word(dev, master_port, master_data); 892 } 893 /* Don't scribble on 0x48 if the controller does not support UDMA */ 894 if (ap->udma_mask) 895 pci_write_config_byte(dev, 0x48, udma_enable); 896 897 spin_unlock_irqrestore(&piix_lock, flags); 898} 899 900/** 901 * piix_set_dmamode - Initialize host controller PATA DMA timings 902 * @ap: Port whose timings we are configuring 903 * @adev: um 904 * 905 * Set MW/UDMA mode for device, in host controller PCI config space. 906 * 907 * LOCKING: 908 * None (inherited from caller). 909 */ 910 911static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev) 912{ 913 do_pata_set_dmamode(ap, adev, 0); 914} 915 916/** 917 * ich_set_dmamode - Initialize host controller PATA DMA timings 918 * @ap: Port whose timings we are configuring 919 * @adev: um 920 * 921 * Set MW/UDMA mode for device, in host controller PCI config space. 922 * 923 * LOCKING: 924 * None (inherited from caller). 925 */ 926 927static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev) 928{ 929 do_pata_set_dmamode(ap, adev, 1); 930} 931 932/* 933 * Serial ATA Index/Data Pair Superset Registers access 934 * 935 * Beginning from ICH8, there's a sane way to access SCRs using index 936 * and data register pair located at BAR5 which means that we have 937 * separate SCRs for master and slave. This is handled using libata 938 * slave_link facility. 939 */ 940static const int piix_sidx_map[] = { 941 [SCR_STATUS] = 0, 942 [SCR_ERROR] = 2, 943 [SCR_CONTROL] = 1, 944}; 945 946static void piix_sidpr_sel(struct ata_link *link, unsigned int reg) 947{ 948 struct ata_port *ap = link->ap; 949 struct piix_host_priv *hpriv = ap->host->private_data; 950 951 iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg], 952 hpriv->sidpr + PIIX_SIDPR_IDX); 953} 954 955static int piix_sidpr_scr_read(struct ata_link *link, 956 unsigned int reg, u32 *val) 957{ 958 struct piix_host_priv *hpriv = link->ap->host->private_data; 959 unsigned long flags; 960 961 if (reg >= ARRAY_SIZE(piix_sidx_map)) 962 return -EINVAL; 963 964 spin_lock_irqsave(&hpriv->sidpr_lock, flags); 965 piix_sidpr_sel(link, reg); 966 *val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA); 967 spin_unlock_irqrestore(&hpriv->sidpr_lock, flags); 968 return 0; 969} 970 971static int piix_sidpr_scr_write(struct ata_link *link, 972 unsigned int reg, u32 val) 973{ 974 struct piix_host_priv *hpriv = link->ap->host->private_data; 975 unsigned long flags; 976 977 if (reg >= ARRAY_SIZE(piix_sidx_map)) 978 return -EINVAL; 979 980 spin_lock_irqsave(&hpriv->sidpr_lock, flags); 981 piix_sidpr_sel(link, reg); 982 iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA); 983 spin_unlock_irqrestore(&hpriv->sidpr_lock, flags); 984 return 0; 985} 986 987static bool piix_irq_check(struct ata_port *ap) 988{ 989 if (unlikely(!ap->ioaddr.bmdma_addr)) 990 return false; 991 992 return ap->ops->bmdma_status(ap) & ATA_DMA_INTR; 993} 994 995#ifdef CONFIG_PM 996static int piix_broken_suspend(void) 997{ 998 static const struct dmi_system_id sysids[] = { 999 { 1000 .ident = "TECRA M3", 1001 .matches = { 1002 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1003 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"), 1004 }, 1005 }, 1006 { 1007 .ident = "TECRA M3", 1008 .matches = { 1009 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1010 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"), 1011 }, 1012 }, 1013 { 1014 .ident = "TECRA M4", 1015 .matches = { 1016 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1017 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"), 1018 }, 1019 }, 1020 { 1021 .ident = "TECRA M4", 1022 .matches = { 1023 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1024 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"), 1025 }, 1026 }, 1027 { 1028 .ident = "TECRA M5", 1029 .matches = { 1030 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1031 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"), 1032 }, 1033 }, 1034 { 1035 .ident = "TECRA M6", 1036 .matches = { 1037 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1038 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"), 1039 }, 1040 }, 1041 { 1042 .ident = "TECRA M7", 1043 .matches = { 1044 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1045 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"), 1046 }, 1047 }, 1048 { 1049 .ident = "TECRA A8", 1050 .matches = { 1051 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1052 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"), 1053 }, 1054 }, 1055 { 1056 .ident = "Satellite R20", 1057 .matches = { 1058 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1059 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"), 1060 }, 1061 }, 1062 { 1063 .ident = "Satellite R25", 1064 .matches = { 1065 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1066 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"), 1067 }, 1068 }, 1069 { 1070 .ident = "Satellite U200", 1071 .matches = { 1072 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1073 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"), 1074 }, 1075 }, 1076 { 1077 .ident = "Satellite U200", 1078 .matches = { 1079 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1080 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"), 1081 }, 1082 }, 1083 { 1084 .ident = "Satellite Pro U200", 1085 .matches = { 1086 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1087 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"), 1088 }, 1089 }, 1090 { 1091 .ident = "Satellite U205", 1092 .matches = { 1093 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1094 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"), 1095 }, 1096 }, 1097 { 1098 .ident = "SATELLITE U205", 1099 .matches = { 1100 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1101 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"), 1102 }, 1103 }, 1104 { 1105 .ident = "Portege M500", 1106 .matches = { 1107 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1108 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"), 1109 }, 1110 }, 1111 { 1112 .ident = "VGN-BX297XP", 1113 .matches = { 1114 DMI_MATCH(DMI_SYS_VENDOR, "Sony Corporation"), 1115 DMI_MATCH(DMI_PRODUCT_NAME, "VGN-BX297XP"), 1116 }, 1117 }, 1118 1119 { } /* terminate list */ 1120 }; 1121 static const char *oemstrs[] = { 1122 "Tecra M3,", 1123 }; 1124 int i; 1125 1126 if (dmi_check_system(sysids)) 1127 return 1; 1128 1129 for (i = 0; i < ARRAY_SIZE(oemstrs); i++) 1130 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL)) 1131 return 1; 1132 1133 /* TECRA M4 sometimes forgets its identify and reports bogus 1134 * DMI information. As the bogus information is a bit 1135 * generic, match as many entries as possible. This manual 1136 * matching is necessary because dmi_system_id.matches is 1137 * limited to four entries. 1138 */ 1139 if (dmi_match(DMI_SYS_VENDOR, "TOSHIBA") && 1140 dmi_match(DMI_PRODUCT_NAME, "000000") && 1141 dmi_match(DMI_PRODUCT_VERSION, "000000") && 1142 dmi_match(DMI_PRODUCT_SERIAL, "000000") && 1143 dmi_match(DMI_BOARD_VENDOR, "TOSHIBA") && 1144 dmi_match(DMI_BOARD_NAME, "Portable PC") && 1145 dmi_match(DMI_BOARD_VERSION, "Version A0")) 1146 return 1; 1147 1148 return 0; 1149} 1150 1151static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) 1152{ 1153 struct ata_host *host = dev_get_drvdata(&pdev->dev); 1154 unsigned long flags; 1155 int rc = 0; 1156 1157 rc = ata_host_suspend(host, mesg); 1158 if (rc) 1159 return rc; 1160 1161 /* Some braindamaged ACPI suspend implementations expect the 1162 * controller to be awake on entry; otherwise, it burns cpu 1163 * cycles and power trying to do something to the sleeping 1164 * beauty. 1165 */ 1166 if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) { 1167 pci_save_state(pdev); 1168 1169 /* mark its power state as "unknown", since we don't 1170 * know if e.g. the BIOS will change its device state 1171 * when we suspend. 1172 */ 1173 if (pdev->current_state == PCI_D0) 1174 pdev->current_state = PCI_UNKNOWN; 1175 1176 /* tell resume that it's waking up from broken suspend */ 1177 spin_lock_irqsave(&host->lock, flags); 1178 host->flags |= PIIX_HOST_BROKEN_SUSPEND; 1179 spin_unlock_irqrestore(&host->lock, flags); 1180 } else 1181 ata_pci_device_do_suspend(pdev, mesg); 1182 1183 return 0; 1184} 1185 1186static int piix_pci_device_resume(struct pci_dev *pdev) 1187{ 1188 struct ata_host *host = dev_get_drvdata(&pdev->dev); 1189 unsigned long flags; 1190 int rc; 1191 1192 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) { 1193 spin_lock_irqsave(&host->lock, flags); 1194 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND; 1195 spin_unlock_irqrestore(&host->lock, flags); 1196 1197 pci_set_power_state(pdev, PCI_D0); 1198 pci_restore_state(pdev); 1199 1200 /* PCI device wasn't disabled during suspend. Use 1201 * pci_reenable_device() to avoid affecting the enable 1202 * count. 1203 */ 1204 rc = pci_reenable_device(pdev); 1205 if (rc) 1206 dev_printk(KERN_ERR, &pdev->dev, "failed to enable " 1207 "device after resume (%d)\n", rc); 1208 } else 1209 rc = ata_pci_device_do_resume(pdev); 1210 1211 if (rc == 0) 1212 ata_host_resume(host); 1213 1214 return rc; 1215} 1216#endif 1217 1218static u8 piix_vmw_bmdma_status(struct ata_port *ap) 1219{ 1220 return ata_bmdma_status(ap) & ~ATA_DMA_ERR; 1221} 1222 1223#define AHCI_PCI_BAR 5 1224#define AHCI_GLOBAL_CTL 0x04 1225#define AHCI_ENABLE (1 << 31) 1226static int piix_disable_ahci(struct pci_dev *pdev) 1227{ 1228 void __iomem *mmio; 1229 u32 tmp; 1230 int rc = 0; 1231 1232 /* BUG: pci_enable_device has not yet been called. This 1233 * works because this device is usually set up by BIOS. 1234 */ 1235 1236 if (!pci_resource_start(pdev, AHCI_PCI_BAR) || 1237 !pci_resource_len(pdev, AHCI_PCI_BAR)) 1238 return 0; 1239 1240 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64); 1241 if (!mmio) 1242 return -ENOMEM; 1243 1244 tmp = ioread32(mmio + AHCI_GLOBAL_CTL); 1245 if (tmp & AHCI_ENABLE) { 1246 tmp &= ~AHCI_ENABLE; 1247 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL); 1248 1249 tmp = ioread32(mmio + AHCI_GLOBAL_CTL); 1250 if (tmp & AHCI_ENABLE) 1251 rc = -EIO; 1252 } 1253 1254 pci_iounmap(pdev, mmio); 1255 return rc; 1256} 1257 1258/** 1259 * piix_check_450nx_errata - Check for problem 450NX setup 1260 * @ata_dev: the PCI device to check 1261 * 1262 * Check for the present of 450NX errata #19 and errata #25. If 1263 * they are found return an error code so we can turn off DMA 1264 */ 1265 1266static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev) 1267{ 1268 struct pci_dev *pdev = NULL; 1269 u16 cfg; 1270 int no_piix_dma = 0; 1271 1272 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) { 1273 /* Look for 450NX PXB. Check for problem configurations 1274 A PCI quirk checks bit 6 already */ 1275 pci_read_config_word(pdev, 0x41, &cfg); 1276 /* Only on the original revision: IDE DMA can hang */ 1277 if (pdev->revision == 0x00) 1278 no_piix_dma = 1; 1279 /* On all revisions below 5 PXB bus lock must be disabled for IDE */ 1280 else if (cfg & (1<<14) && pdev->revision < 5) 1281 no_piix_dma = 2; 1282 } 1283 if (no_piix_dma) 1284 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n"); 1285 if (no_piix_dma == 2) 1286 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n"); 1287 return no_piix_dma; 1288} 1289 1290static void __devinit piix_init_pcs(struct ata_host *host, 1291 const struct piix_map_db *map_db) 1292{ 1293 struct pci_dev *pdev = to_pci_dev(host->dev); 1294 u16 pcs, new_pcs; 1295 1296 pci_read_config_word(pdev, ICH5_PCS, &pcs); 1297 1298 new_pcs = pcs | map_db->port_enable; 1299 1300 if (new_pcs != pcs) { 1301 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs); 1302 pci_write_config_word(pdev, ICH5_PCS, new_pcs); 1303 msleep(150); 1304 } 1305} 1306 1307static const int *__devinit piix_init_sata_map(struct pci_dev *pdev, 1308 struct ata_port_info *pinfo, 1309 const struct piix_map_db *map_db) 1310{ 1311 const int *map; 1312 int i, invalid_map = 0; 1313 u8 map_value; 1314 1315 pci_read_config_byte(pdev, ICH5_PMR, &map_value); 1316 1317 map = map_db->map[map_value & map_db->mask]; 1318 1319 dev_printk(KERN_INFO, &pdev->dev, "MAP ["); 1320 for (i = 0; i < 4; i++) { 1321 switch (map[i]) { 1322 case RV: 1323 invalid_map = 1; 1324 printk(" XX"); 1325 break; 1326 1327 case NA: 1328 printk(" --"); 1329 break; 1330 1331 case IDE: 1332 WARN_ON((i & 1) || map[i + 1] != IDE); 1333 pinfo[i / 2] = piix_port_info[ich_pata_100]; 1334 i++; 1335 printk(" IDE IDE"); 1336 break; 1337 1338 default: 1339 printk(" P%d", map[i]); 1340 if (i & 1) 1341 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS; 1342 break; 1343 } 1344 } 1345 printk(" ]\n"); 1346 1347 if (invalid_map) 1348 dev_printk(KERN_ERR, &pdev->dev, 1349 "invalid MAP value %u\n", map_value); 1350 1351 return map; 1352} 1353 1354static bool piix_no_sidpr(struct ata_host *host) 1355{ 1356 struct pci_dev *pdev = to_pci_dev(host->dev); 1357 1358 /* 1359 * Samsung DB-P70 only has three ATA ports exposed and 1360 * curiously the unconnected first port reports link online 1361 * while not responding to SRST protocol causing excessive 1362 * detection delay. 1363 * 1364 * Unfortunately, the system doesn't carry enough DMI 1365 * information to identify the machine but does have subsystem 1366 * vendor and device set. As it's unclear whether the 1367 * subsystem vendor/device is used only for this specific 1368 * board, the port can't be disabled solely with the 1369 * information; however, turning off SIDPR access works around 1370 * the problem. Turn it off. 1371 * 1372 * This problem is reported in bnc#441240. 1373 * 1374 * https://bugzilla.novell.com/show_bug.cgi?id=441420 1375 */ 1376 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2920 && 1377 pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG && 1378 pdev->subsystem_device == 0xb049) { 1379 dev_printk(KERN_WARNING, host->dev, 1380 "Samsung DB-P70 detected, disabling SIDPR\n"); 1381 return true; 1382 } 1383 1384 return false; 1385} 1386 1387static int __devinit piix_init_sidpr(struct ata_host *host) 1388{ 1389 struct pci_dev *pdev = to_pci_dev(host->dev); 1390 struct piix_host_priv *hpriv = host->private_data; 1391 struct ata_link *link0 = &host->ports[0]->link; 1392 u32 scontrol; 1393 int i, rc; 1394 1395 /* check for availability */ 1396 for (i = 0; i < 4; i++) 1397 if (hpriv->map[i] == IDE) 1398 return 0; 1399 1400 /* is it blacklisted? */ 1401 if (piix_no_sidpr(host)) 1402 return 0; 1403 1404 if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR)) 1405 return 0; 1406 1407 if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 || 1408 pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN) 1409 return 0; 1410 1411 if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME)) 1412 return 0; 1413 1414 hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR]; 1415 1416 /* SCR access via SIDPR doesn't work on some configurations. 1417 * Give it a test drive by inhibiting power save modes which 1418 * we'll do anyway. 1419 */ 1420 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol); 1421 1422 /* if IPM is already 3, SCR access is probably working. Don't 1423 * un-inhibit power save modes as BIOS might have inhibited 1424 * them for a reason. 1425 */ 1426 if ((scontrol & 0xf00) != 0x300) { 1427 scontrol |= 0x300; 1428 piix_sidpr_scr_write(link0, SCR_CONTROL, scontrol); 1429 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol); 1430 1431 if ((scontrol & 0xf00) != 0x300) { 1432 dev_printk(KERN_INFO, host->dev, "SCR access via " 1433 "SIDPR is available but doesn't work\n"); 1434 return 0; 1435 } 1436 } 1437 1438 /* okay, SCRs available, set ops and ask libata for slave_link */ 1439 for (i = 0; i < 2; i++) { 1440 struct ata_port *ap = host->ports[i]; 1441 1442 ap->ops = &piix_sidpr_sata_ops; 1443 1444 if (ap->flags & ATA_FLAG_SLAVE_POSS) { 1445 rc = ata_slave_link_init(ap); 1446 if (rc) 1447 return rc; 1448 } 1449 } 1450 1451 return 0; 1452} 1453 1454static void piix_iocfg_bit18_quirk(struct ata_host *host) 1455{ 1456 static const struct dmi_system_id sysids[] = { 1457 { 1458 /* Clevo M570U sets IOCFG bit 18 if the cdrom 1459 * isn't used to boot the system which 1460 * disables the channel. 1461 */ 1462 .ident = "M570U", 1463 .matches = { 1464 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."), 1465 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"), 1466 }, 1467 }, 1468 1469 { } /* terminate list */ 1470 }; 1471 struct pci_dev *pdev = to_pci_dev(host->dev); 1472 struct piix_host_priv *hpriv = host->private_data; 1473 1474 if (!dmi_check_system(sysids)) 1475 return; 1476 1477 /* The datasheet says that bit 18 is NOOP but certain systems 1478 * seem to use it to disable a channel. Clear the bit on the 1479 * affected systems. 1480 */ 1481 if (hpriv->saved_iocfg & (1 << 18)) { 1482 dev_printk(KERN_INFO, &pdev->dev, 1483 "applying IOCFG bit18 quirk\n"); 1484 pci_write_config_dword(pdev, PIIX_IOCFG, 1485 hpriv->saved_iocfg & ~(1 << 18)); 1486 } 1487} 1488 1489static bool piix_broken_system_poweroff(struct pci_dev *pdev) 1490{ 1491 static const struct dmi_system_id broken_systems[] = { 1492 { 1493 .ident = "HP Compaq 2510p", 1494 .matches = { 1495 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1496 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 2510p"), 1497 }, 1498 /* PCI slot number of the controller */ 1499 .driver_data = (void *)0x1FUL, 1500 }, 1501 { 1502 .ident = "HP Compaq nc6000", 1503 .matches = { 1504 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1505 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nc6000"), 1506 }, 1507 /* PCI slot number of the controller */ 1508 .driver_data = (void *)0x1FUL, 1509 }, 1510 1511 { } /* terminate list */ 1512 }; 1513 const struct dmi_system_id *dmi = dmi_first_match(broken_systems); 1514 1515 if (dmi) { 1516 unsigned long slot = (unsigned long)dmi->driver_data; 1517 /* apply the quirk only to on-board controllers */ 1518 return slot == PCI_SLOT(pdev->devfn); 1519 } 1520 1521 return false; 1522} 1523 1524/** 1525 * piix_init_one - Register PIIX ATA PCI device with kernel services 1526 * @pdev: PCI device to register 1527 * @ent: Entry in piix_pci_tbl matching with @pdev 1528 * 1529 * Called from kernel PCI layer. We probe for combined mode (sigh), 1530 * and then hand over control to libata, for it to do the rest. 1531 * 1532 * LOCKING: 1533 * Inherited from PCI layer (may sleep). 1534 * 1535 * RETURNS: 1536 * Zero on success, or -ERRNO value. 1537 */ 1538 1539static int __devinit piix_init_one(struct pci_dev *pdev, 1540 const struct pci_device_id *ent) 1541{ 1542 static int printed_version; 1543 struct device *dev = &pdev->dev; 1544 struct ata_port_info port_info[2]; 1545 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] }; 1546 unsigned long port_flags; 1547 struct ata_host *host; 1548 struct piix_host_priv *hpriv; 1549 int rc; 1550 1551 if (!printed_version++) 1552 dev_printk(KERN_DEBUG, &pdev->dev, 1553 "version " DRV_VERSION "\n"); 1554 1555 if (!in_module_init && ent->driver_data >= ich5_sata) 1556 return -ENODEV; 1557 1558 if (piix_broken_system_poweroff(pdev)) { 1559 piix_port_info[ent->driver_data].flags |= 1560 ATA_FLAG_NO_POWEROFF_SPINDOWN | 1561 ATA_FLAG_NO_HIBERNATE_SPINDOWN; 1562 dev_info(&pdev->dev, "quirky BIOS, skipping spindown " 1563 "on poweroff and hibernation\n"); 1564 } 1565 1566 port_info[0] = piix_port_info[ent->driver_data]; 1567 port_info[1] = piix_port_info[ent->driver_data]; 1568 1569 port_flags = port_info[0].flags; 1570 1571 /* enable device and prepare host */ 1572 rc = pcim_enable_device(pdev); 1573 if (rc) 1574 return rc; 1575 1576 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); 1577 if (!hpriv) 1578 return -ENOMEM; 1579 spin_lock_init(&hpriv->sidpr_lock); 1580 1581 /* Save IOCFG, this will be used for cable detection, quirk 1582 * detection and restoration on detach. This is necessary 1583 * because some ACPI implementations mess up cable related 1584 * bits on _STM. Reported on kernel bz#11879. 1585 */ 1586 pci_read_config_dword(pdev, PIIX_IOCFG, &hpriv->saved_iocfg); 1587 1588 /* ICH6R may be driven by either ata_piix or ahci driver 1589 * regardless of BIOS configuration. Make sure AHCI mode is 1590 * off. 1591 */ 1592 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) { 1593 rc = piix_disable_ahci(pdev); 1594 if (rc) 1595 return rc; 1596 } 1597 1598 /* SATA map init can change port_info, do it before prepping host */ 1599 if (port_flags & ATA_FLAG_SATA) 1600 hpriv->map = piix_init_sata_map(pdev, port_info, 1601 piix_map_db_table[ent->driver_data]); 1602 1603 rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host); 1604 if (rc) 1605 return rc; 1606 host->private_data = hpriv; 1607 1608 /* initialize controller */ 1609 if (port_flags & ATA_FLAG_SATA) { 1610 piix_init_pcs(host, piix_map_db_table[ent->driver_data]); 1611 rc = piix_init_sidpr(host); 1612 if (rc) 1613 return rc; 1614 } 1615 1616 /* apply IOCFG bit18 quirk */ 1617 piix_iocfg_bit18_quirk(host); 1618 1619 /* On ICH5, some BIOSen disable the interrupt using the 1620 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3. 1621 * On ICH6, this bit has the same effect, but only when 1622 * MSI is disabled (and it is disabled, as we don't use 1623 * message-signalled interrupts currently). 1624 */ 1625 if (port_flags & PIIX_FLAG_CHECKINTR) 1626 pci_intx(pdev, 1); 1627 1628 if (piix_check_450nx_errata(pdev)) { 1629 /* This writes into the master table but it does not 1630 really matter for this errata as we will apply it to 1631 all the PIIX devices on the board */ 1632 host->ports[0]->mwdma_mask = 0; 1633 host->ports[0]->udma_mask = 0; 1634 host->ports[1]->mwdma_mask = 0; 1635 host->ports[1]->udma_mask = 0; 1636 } 1637 host->flags |= ATA_HOST_PARALLEL_SCAN; 1638 1639 pci_set_master(pdev); 1640 return ata_pci_sff_activate_host(host, ata_bmdma_interrupt, &piix_sht); 1641} 1642 1643static void piix_remove_one(struct pci_dev *pdev) 1644{ 1645 struct ata_host *host = dev_get_drvdata(&pdev->dev); 1646 struct piix_host_priv *hpriv = host->private_data; 1647 1648 pci_write_config_dword(pdev, PIIX_IOCFG, hpriv->saved_iocfg); 1649 1650 ata_pci_remove_one(pdev); 1651} 1652 1653static int __init piix_init(void) 1654{ 1655 int rc; 1656 1657 DPRINTK("pci_register_driver\n"); 1658 rc = pci_register_driver(&piix_pci_driver); 1659 if (rc) 1660 return rc; 1661 1662 in_module_init = 0; 1663 1664 DPRINTK("done\n"); 1665 return 0; 1666} 1667 1668static void __exit piix_exit(void) 1669{ 1670 pci_unregister_driver(&piix_pci_driver); 1671} 1672 1673module_init(piix_init); 1674module_exit(piix_exit); 1675