1/* 2 * Moorestown PCI support 3 * Copyright (c) 2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Moorestown has an interesting PCI implementation: 7 * - configuration space is memory mapped (as defined by MCFG) 8 * - Lincroft devices also have a real, type 1 configuration space 9 * - Early Lincroft silicon has a type 1 access bug that will cause 10 * a hang if non-existent devices are accessed 11 * - some devices have the "fixed BAR" capability, which means 12 * they can't be relocated or modified; check for that during 13 * BAR sizing 14 * 15 * So, we use the MCFG space for all reads and writes, but also send 16 * Lincroft writes to type 1 space. But only read/write if the device 17 * actually exists, otherwise return all 1s for reads and bit bucket 18 * the writes. 19 */ 20 21#include <linux/sched.h> 22#include <linux/pci.h> 23#include <linux/ioport.h> 24#include <linux/init.h> 25#include <linux/dmi.h> 26 27#include <asm/acpi.h> 28#include <asm/segment.h> 29#include <asm/io.h> 30#include <asm/smp.h> 31#include <asm/pci_x86.h> 32#include <asm/hw_irq.h> 33#include <asm/io_apic.h> 34 35#define PCIE_CAP_OFFSET 0x100 36 37/* Fixed BAR fields */ 38#define PCIE_VNDR_CAP_ID_FIXED_BAR 0x00 /* Fixed BAR (TBD) */ 39#define PCI_FIXED_BAR_0_SIZE 0x04 40#define PCI_FIXED_BAR_1_SIZE 0x08 41#define PCI_FIXED_BAR_2_SIZE 0x0c 42#define PCI_FIXED_BAR_3_SIZE 0x10 43#define PCI_FIXED_BAR_4_SIZE 0x14 44#define PCI_FIXED_BAR_5_SIZE 0x1c 45 46/** 47 * fixed_bar_cap - return the offset of the fixed BAR cap if found 48 * @bus: PCI bus 49 * @devfn: device in question 50 * 51 * Look for the fixed BAR cap on @bus and @devfn, returning its offset 52 * if found or 0 otherwise. 53 */ 54static int fixed_bar_cap(struct pci_bus *bus, unsigned int devfn) 55{ 56 int pos; 57 u32 pcie_cap = 0, cap_data; 58 59 pos = PCIE_CAP_OFFSET; 60 61 if (!raw_pci_ext_ops) 62 return 0; 63 64 while (pos) { 65 if (raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number, 66 devfn, pos, 4, &pcie_cap)) 67 return 0; 68 69 if (PCI_EXT_CAP_ID(pcie_cap) == 0x0000 || 70 PCI_EXT_CAP_ID(pcie_cap) == 0xffff) 71 break; 72 73 if (PCI_EXT_CAP_ID(pcie_cap) == PCI_EXT_CAP_ID_VNDR) { 74 raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number, 75 devfn, pos + 4, 4, &cap_data); 76 if ((cap_data & 0xffff) == PCIE_VNDR_CAP_ID_FIXED_BAR) 77 return pos; 78 } 79 80 pos = PCI_EXT_CAP_NEXT(pcie_cap); 81 } 82 83 return 0; 84} 85 86static int pci_device_update_fixed(struct pci_bus *bus, unsigned int devfn, 87 int reg, int len, u32 val, int offset) 88{ 89 u32 size; 90 unsigned int domain, busnum; 91 int bar = (reg - PCI_BASE_ADDRESS_0) >> 2; 92 93 domain = pci_domain_nr(bus); 94 busnum = bus->number; 95 96 if (val == ~0 && len == 4) { 97 unsigned long decode; 98 99 raw_pci_ext_ops->read(domain, busnum, devfn, 100 offset + 8 + (bar * 4), 4, &size); 101 102 /* Turn the size into a decode pattern for the sizing code */ 103 if (size) { 104 decode = size - 1; 105 decode |= decode >> 1; 106 decode |= decode >> 2; 107 decode |= decode >> 4; 108 decode |= decode >> 8; 109 decode |= decode >> 16; 110 decode++; 111 decode = ~(decode - 1); 112 } else { 113 decode = 0; 114 } 115 116 /* 117 * If val is all ones, the core code is trying to size the reg, 118 * so update the mmconfig space with the real size. 119 * 120 * Note: this assumes the fixed size we got is a power of two. 121 */ 122 return raw_pci_ext_ops->write(domain, busnum, devfn, reg, 4, 123 decode); 124 } 125 126 /* This is some other kind of BAR write, so just do it. */ 127 return raw_pci_ext_ops->write(domain, busnum, devfn, reg, len, val); 128} 129 130/** 131 * type1_access_ok - check whether to use type 1 132 * @bus: bus number 133 * @devfn: device & function in question 134 * 135 * If the bus is on a Lincroft chip and it exists, or is not on a Lincroft at 136 * all, the we can go ahead with any reads & writes. If it's on a Lincroft, 137 * but doesn't exist, avoid the access altogether to keep the chip from 138 * hanging. 139 */ 140static bool type1_access_ok(unsigned int bus, unsigned int devfn, int reg) 141{ 142 if (reg >= 0x100 || reg == PCI_STATUS || reg == PCI_HEADER_TYPE) 143 return 0; 144 if (bus == 0 && (devfn == PCI_DEVFN(2, 0) || devfn == PCI_DEVFN(0, 0))) 145 return 1; 146 return 0; /* langwell on others */ 147} 148 149static int pci_read(struct pci_bus *bus, unsigned int devfn, int where, 150 int size, u32 *value) 151{ 152 if (type1_access_ok(bus->number, devfn, where)) 153 return pci_direct_conf1.read(pci_domain_nr(bus), bus->number, 154 devfn, where, size, value); 155 return raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number, 156 devfn, where, size, value); 157} 158 159static int pci_write(struct pci_bus *bus, unsigned int devfn, int where, 160 int size, u32 value) 161{ 162 int offset; 163 164 /* On MRST, there is no PCI ROM BAR, this will cause a subsequent read 165 * to ROM BAR return 0 then being ignored. 166 */ 167 if (where == PCI_ROM_ADDRESS) 168 return 0; 169 170 /* 171 * Devices with fixed BARs need special handling: 172 * - BAR sizing code will save, write ~0, read size, restore 173 * - so writes to fixed BARs need special handling 174 * - other writes to fixed BAR devices should go through mmconfig 175 */ 176 offset = fixed_bar_cap(bus, devfn); 177 if (offset && 178 (where >= PCI_BASE_ADDRESS_0 && where <= PCI_BASE_ADDRESS_5)) { 179 return pci_device_update_fixed(bus, devfn, where, size, value, 180 offset); 181 } 182 183 /* 184 * On Moorestown update both real & mmconfig space 185 * Note: early Lincroft silicon can't handle type 1 accesses to 186 * non-existent devices, so just eat the write in that case. 187 */ 188 if (type1_access_ok(bus->number, devfn, where)) 189 return pci_direct_conf1.write(pci_domain_nr(bus), bus->number, 190 devfn, where, size, value); 191 return raw_pci_ext_ops->write(pci_domain_nr(bus), bus->number, devfn, 192 where, size, value); 193} 194 195static int mrst_pci_irq_enable(struct pci_dev *dev) 196{ 197 u8 pin; 198 struct io_apic_irq_attr irq_attr; 199 200 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 201 202 /* MRST only have IOAPIC, the PCI irq lines are 1:1 mapped to 203 * IOAPIC RTE entries, so we just enable RTE for the device. 204 */ 205 irq_attr.ioapic = mp_find_ioapic(dev->irq); 206 irq_attr.ioapic_pin = dev->irq; 207 irq_attr.trigger = 1; /* level */ 208 irq_attr.polarity = 1; /* active low */ 209 io_apic_set_pci_routing(&dev->dev, dev->irq, &irq_attr); 210 211 return 0; 212} 213 214struct pci_ops pci_mrst_ops = { 215 .read = pci_read, 216 .write = pci_write, 217}; 218 219/** 220 * pci_mrst_init - installs pci_mrst_ops 221 * 222 * Moorestown has an interesting PCI implementation (see above). 223 * Called when the early platform detection installs it. 224 */ 225int __init pci_mrst_init(void) 226{ 227 printk(KERN_INFO "Moorestown platform detected, using MRST PCI ops\n"); 228 pci_mmcfg_late_init(); 229 pcibios_enable_irq = mrst_pci_irq_enable; 230 pci_root_ops = pci_mrst_ops; 231 /* Continue with standard init */ 232 return 1; 233} 234 235/* 236 * Langwell devices reside at fixed offsets, don't try to move them. 237 */ 238static void __devinit pci_fixed_bar_fixup(struct pci_dev *dev) 239{ 240 unsigned long offset; 241 u32 size; 242 int i; 243 244 /* Must have extended configuration space */ 245 if (dev->cfg_size < PCIE_CAP_OFFSET + 4) 246 return; 247 248 /* Fixup the BAR sizes for fixed BAR devices and make them unmoveable */ 249 offset = fixed_bar_cap(dev->bus, dev->devfn); 250 if (!offset || PCI_DEVFN(2, 0) == dev->devfn || 251 PCI_DEVFN(2, 2) == dev->devfn) 252 return; 253 254 for (i = 0; i < PCI_ROM_RESOURCE; i++) { 255 pci_read_config_dword(dev, offset + 8 + (i * 4), &size); 256 dev->resource[i].end = dev->resource[i].start + size - 1; 257 dev->resource[i].flags |= IORESOURCE_PCI_FIXED; 258 } 259} 260DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_fixed_bar_fixup); 261