1/* 2 * Exceptions for specific devices. Usually work-arounds for fatal design flaws. 3 */ 4 5#include <linux/delay.h> 6#include <linux/dmi.h> 7#include <linux/pci.h> 8#include <linux/init.h> 9#include <asm/pci_x86.h> 10 11static void __devinit pci_fixup_i450nx(struct pci_dev *d) 12{ 13 /* 14 * i450NX -- Find and scan all secondary buses on all PXB's. 15 */ 16 int pxb, reg; 17 u8 busno, suba, subb; 18 19 dev_warn(&d->dev, "Searching for i450NX host bridges\n"); 20 reg = 0xd0; 21 for(pxb = 0; pxb < 2; pxb++) { 22 pci_read_config_byte(d, reg++, &busno); 23 pci_read_config_byte(d, reg++, &suba); 24 pci_read_config_byte(d, reg++, &subb); 25 dev_dbg(&d->dev, "i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno, 26 suba, subb); 27 if (busno) 28 pci_scan_bus_with_sysdata(busno); /* Bus A */ 29 if (suba < subb) 30 pci_scan_bus_with_sysdata(suba+1); /* Bus B */ 31 } 32 pcibios_last_bus = -1; 33} 34DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx); 35 36static void __devinit pci_fixup_i450gx(struct pci_dev *d) 37{ 38 /* 39 * i450GX and i450KX -- Find and scan all secondary buses. 40 * (called separately for each PCI bridge found) 41 */ 42 u8 busno; 43 pci_read_config_byte(d, 0x4a, &busno); 44 dev_info(&d->dev, "i440KX/GX host bridge; secondary bus %02x\n", busno); 45 pci_scan_bus_with_sysdata(busno); 46 pcibios_last_bus = -1; 47} 48DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454GX, pci_fixup_i450gx); 49 50static void __devinit pci_fixup_umc_ide(struct pci_dev *d) 51{ 52 /* 53 * UM8886BF IDE controller sets region type bits incorrectly, 54 * therefore they look like memory despite of them being I/O. 55 */ 56 int i; 57 58 dev_warn(&d->dev, "Fixing base address flags\n"); 59 for(i = 0; i < 4; i++) 60 d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO; 61} 62DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, pci_fixup_umc_ide); 63 64static void __devinit pci_fixup_ncr53c810(struct pci_dev *d) 65{ 66 /* 67 * NCR 53C810 returns class code 0 (at least on some systems). 68 * Fix class to be PCI_CLASS_STORAGE_SCSI 69 */ 70 if (!d->class) { 71 dev_warn(&d->dev, "Fixing NCR 53C810 class code\n"); 72 d->class = PCI_CLASS_STORAGE_SCSI << 8; 73 } 74} 75DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, pci_fixup_ncr53c810); 76 77static void __devinit pci_fixup_latency(struct pci_dev *d) 78{ 79 /* 80 * SiS 5597 and 5598 chipsets require latency timer set to 81 * at most 32 to avoid lockups. 82 */ 83 dev_dbg(&d->dev, "Setting max latency to 32\n"); 84 pcibios_max_latency = 32; 85} 86DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, pci_fixup_latency); 87DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5598, pci_fixup_latency); 88 89static void __devinit pci_fixup_piix4_acpi(struct pci_dev *d) 90{ 91 /* 92 * PIIX4 ACPI device: hardwired IRQ9 93 */ 94 d->irq = 9; 95} 96DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, pci_fixup_piix4_acpi); 97 98/* 99 * Addresses issues with problems in the memory write queue timer in 100 * certain VIA Northbridges. This bugfix is per VIA's specifications, 101 * except for the KL133/KM133: clearing bit 5 on those Northbridges seems 102 * to trigger a bug in its integrated ProSavage video card, which 103 * causes screen corruption. We only clear bits 6 and 7 for that chipset, 104 * until VIA can provide us with definitive information on why screen 105 * corruption occurs, and what exactly those bits do. 106 * 107 * VIA 8363,8622,8361 Northbridges: 108 * - bits 5, 6, 7 at offset 0x55 need to be turned off 109 * VIA 8367 (KT266x) Northbridges: 110 * - bits 5, 6, 7 at offset 0x95 need to be turned off 111 * VIA 8363 rev 0x81/0x84 (KL133/KM133) Northbridges: 112 * - bits 6, 7 at offset 0x55 need to be turned off 113 */ 114 115#define VIA_8363_KL133_REVISION_ID 0x81 116#define VIA_8363_KM133_REVISION_ID 0x84 117 118static void pci_fixup_via_northbridge_bug(struct pci_dev *d) 119{ 120 u8 v; 121 int where = 0x55; 122 int mask = 0x1f; /* clear bits 5, 6, 7 by default */ 123 124 if (d->device == PCI_DEVICE_ID_VIA_8367_0) { 125 /* fix pci bus latency issues resulted by NB bios error 126 it appears on bug free^Wreduced kt266x's bios forces 127 NB latency to zero */ 128 pci_write_config_byte(d, PCI_LATENCY_TIMER, 0); 129 130 where = 0x95; /* the memory write queue timer register is 131 different for the KT266x's: 0x95 not 0x55 */ 132 } else if (d->device == PCI_DEVICE_ID_VIA_8363_0 && 133 (d->revision == VIA_8363_KL133_REVISION_ID || 134 d->revision == VIA_8363_KM133_REVISION_ID)) { 135 mask = 0x3f; /* clear only bits 6 and 7; clearing bit 5 136 causes screen corruption on the KL133/KM133 */ 137 } 138 139 pci_read_config_byte(d, where, &v); 140 if (v & ~mask) { 141 dev_warn(&d->dev, "Disabling VIA memory write queue (PCI ID %04x, rev %02x): [%02x] %02x & %02x -> %02x\n", \ 142 d->device, d->revision, where, v, mask, v & mask); 143 v &= mask; 144 pci_write_config_byte(d, where, v); 145 } 146} 147DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug); 148DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug); 149DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug); 150DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug); 151DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug); 152DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug); 153DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug); 154DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug); 155 156/* 157 * For some reasons Intel decided that certain parts of their 158 * 815, 845 and some other chipsets must look like PCI-to-PCI bridges 159 * while they are obviously not. The 82801 family (AA, AB, BAM/CAM, 160 * BA/CA/DB and E) PCI bridges are actually HUB-to-PCI ones, according 161 * to Intel terminology. These devices do forward all addresses from 162 * system to PCI bus no matter what are their window settings, so they are 163 * "transparent" (or subtractive decoding) from programmers point of view. 164 */ 165static void __devinit pci_fixup_transparent_bridge(struct pci_dev *dev) 166{ 167 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI && 168 (dev->device & 0xff00) == 0x2400) 169 dev->transparent = 1; 170} 171DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_fixup_transparent_bridge); 172 173static void pci_fixup_nforce2(struct pci_dev *dev) 174{ 175 u32 val; 176 177 /* 178 * Chip Old value New value 179 * C17 0x1F0FFF01 0x1F01FF01 180 * C18D 0x9F0FFF01 0x9F01FF01 181 * 182 * Northbridge chip version may be determined by 183 * reading the PCI revision ID (0xC1 or greater is C18D). 184 */ 185 pci_read_config_dword(dev, 0x6c, &val); 186 187 /* 188 * Apply fixup if needed, but don't touch disconnect state 189 */ 190 if ((val & 0x00FF0000) != 0x00010000) { 191 dev_warn(&dev->dev, "nForce2 C1 Halt Disconnect fixup\n"); 192 pci_write_config_dword(dev, 0x6c, (val & 0xFF00FFFF) | 0x00010000); 193 } 194} 195DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2); 196DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2); 197 198/* Max PCI Express root ports */ 199#define MAX_PCIEROOT 6 200static int quirk_aspm_offset[MAX_PCIEROOT << 3]; 201 202#define GET_INDEX(a, b) ((((a) - PCI_DEVICE_ID_INTEL_MCH_PA) << 3) + ((b) & 7)) 203 204static int quirk_pcie_aspm_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value) 205{ 206 return raw_pci_read(pci_domain_nr(bus), bus->number, 207 devfn, where, size, value); 208} 209 210/* 211 * Replace the original pci bus ops for write with a new one that will filter 212 * the request to insure ASPM cannot be enabled. 213 */ 214static int quirk_pcie_aspm_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value) 215{ 216 u8 offset; 217 218 offset = quirk_aspm_offset[GET_INDEX(bus->self->device, devfn)]; 219 220 if ((offset) && (where == offset)) 221 value = value & 0xfffffffc; 222 223 return raw_pci_write(pci_domain_nr(bus), bus->number, 224 devfn, where, size, value); 225} 226 227static struct pci_ops quirk_pcie_aspm_ops = { 228 .read = quirk_pcie_aspm_read, 229 .write = quirk_pcie_aspm_write, 230}; 231 232/* 233 * Prevents PCI Express ASPM (Active State Power Management) being enabled. 234 * 235 * Save the register offset, where the ASPM control bits are located, 236 * for each PCI Express device that is in the device list of 237 * the root port in an array for fast indexing. Replace the bus ops 238 * with the modified one. 239 */ 240static void pcie_rootport_aspm_quirk(struct pci_dev *pdev) 241{ 242 int cap_base, i; 243 struct pci_bus *pbus; 244 struct pci_dev *dev; 245 246 if ((pbus = pdev->subordinate) == NULL) 247 return; 248 249 /* 250 * Check if the DID of pdev matches one of the six root ports. This 251 * check is needed in the case this function is called directly by the 252 * hot-plug driver. 253 */ 254 if ((pdev->device < PCI_DEVICE_ID_INTEL_MCH_PA) || 255 (pdev->device > PCI_DEVICE_ID_INTEL_MCH_PC1)) 256 return; 257 258 if (list_empty(&pbus->devices)) { 259 /* 260 * If no device is attached to the root port at power-up or 261 * after hot-remove, the pbus->devices is empty and this code 262 * will set the offsets to zero and the bus ops to parent's bus 263 * ops, which is unmodified. 264 */ 265 for (i = GET_INDEX(pdev->device, 0); i <= GET_INDEX(pdev->device, 7); ++i) 266 quirk_aspm_offset[i] = 0; 267 268 pbus->ops = pbus->parent->ops; 269 } else { 270 /* 271 * If devices are attached to the root port at power-up or 272 * after hot-add, the code loops through the device list of 273 * each root port to save the register offsets and replace the 274 * bus ops. 275 */ 276 list_for_each_entry(dev, &pbus->devices, bus_list) { 277 /* There are 0 to 8 devices attached to this bus */ 278 cap_base = pci_find_capability(dev, PCI_CAP_ID_EXP); 279 quirk_aspm_offset[GET_INDEX(pdev->device, dev->devfn)] = cap_base + 0x10; 280 } 281 pbus->ops = &quirk_pcie_aspm_ops; 282 } 283} 284DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PA, pcie_rootport_aspm_quirk); 285DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PA1, pcie_rootport_aspm_quirk); 286DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PB, pcie_rootport_aspm_quirk); 287DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PB1, pcie_rootport_aspm_quirk); 288DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PC, pcie_rootport_aspm_quirk); 289DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PC1, pcie_rootport_aspm_quirk); 290 291/* 292 * Fixup to mark boot BIOS video selected by BIOS before it changes 293 * 294 * From information provided by "Jon Smirl" <jonsmirl@gmail.com> 295 * 296 * The standard boot ROM sequence for an x86 machine uses the BIOS 297 * to select an initial video card for boot display. This boot video 298 * card will have it's BIOS copied to C0000 in system RAM. 299 * IORESOURCE_ROM_SHADOW is used to associate the boot video 300 * card with this copy. On laptops this copy has to be used since 301 * the main ROM may be compressed or combined with another image. 302 * See pci_map_rom() for use of this flag. IORESOURCE_ROM_SHADOW 303 * is marked here since the boot video device will be the only enabled 304 * video device at this point. 305 */ 306 307static void __devinit pci_fixup_video(struct pci_dev *pdev) 308{ 309 struct pci_dev *bridge; 310 struct pci_bus *bus; 311 u16 config; 312 313 if ((pdev->class >> 8) != PCI_CLASS_DISPLAY_VGA) 314 return; 315 316 /* Is VGA routed to us? */ 317 bus = pdev->bus; 318 while (bus) { 319 bridge = bus->self; 320 321 /* 322 * From information provided by 323 * "David Miller" <davem@davemloft.net> 324 * The bridge control register is valid for PCI header 325 * type BRIDGE, or CARDBUS. Host to PCI controllers use 326 * PCI header type NORMAL. 327 */ 328 if (bridge 329 && ((bridge->hdr_type == PCI_HEADER_TYPE_BRIDGE) 330 || (bridge->hdr_type == PCI_HEADER_TYPE_CARDBUS))) { 331 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, 332 &config); 333 if (!(config & PCI_BRIDGE_CTL_VGA)) 334 return; 335 } 336 bus = bus->parent; 337 } 338 pci_read_config_word(pdev, PCI_COMMAND, &config); 339 if (config & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) { 340 pdev->resource[PCI_ROM_RESOURCE].flags |= IORESOURCE_ROM_SHADOW; 341 dev_printk(KERN_DEBUG, &pdev->dev, "Boot video device\n"); 342 } 343} 344DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_video); 345 346 347static const struct dmi_system_id __devinitconst msi_k8t_dmi_table[] = { 348 { 349 .ident = "MSI-K8T-Neo2Fir", 350 .matches = { 351 DMI_MATCH(DMI_SYS_VENDOR, "MSI"), 352 DMI_MATCH(DMI_PRODUCT_NAME, "MS-6702E"), 353 }, 354 }, 355 {} 356}; 357 358/* 359 * The AMD-Athlon64 board MSI "K8T Neo2-FIR" disables the onboard sound 360 * card if a PCI-soundcard is added. 361 * 362 * The BIOS only gives options "DISABLED" and "AUTO". This code sets 363 * the corresponding register-value to enable the soundcard. 364 * 365 * The soundcard is only enabled, if the mainborad is identified 366 * via DMI-tables and the soundcard is detected to be off. 367 */ 368static void __devinit pci_fixup_msi_k8t_onboard_sound(struct pci_dev *dev) 369{ 370 unsigned char val; 371 if (!dmi_check_system(msi_k8t_dmi_table)) 372 return; /* only applies to MSI K8T Neo2-FIR */ 373 374 pci_read_config_byte(dev, 0x50, &val); 375 if (val & 0x40) { 376 pci_write_config_byte(dev, 0x50, val & (~0x40)); 377 378 /* verify the change for status output */ 379 pci_read_config_byte(dev, 0x50, &val); 380 if (val & 0x40) 381 dev_info(&dev->dev, "Detected MSI K8T Neo2-FIR; " 382 "can't enable onboard soundcard!\n"); 383 else 384 dev_info(&dev->dev, "Detected MSI K8T Neo2-FIR; " 385 "enabled onboard soundcard\n"); 386 } 387} 388DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, 389 pci_fixup_msi_k8t_onboard_sound); 390DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, 391 pci_fixup_msi_k8t_onboard_sound); 392 393/* 394 * Some Toshiba laptops need extra code to enable their TI TSB43AB22/A. 395 * 396 * We pretend to bring them out of full D3 state, and restore the proper 397 * IRQ, PCI cache line size, and BARs, otherwise the device won't function 398 * properly. In some cases, the device will generate an interrupt on 399 * the wrong IRQ line, causing any devices sharing the line it's 400 * *supposed* to use to be disabled by the kernel's IRQ debug code. 401 */ 402static u16 toshiba_line_size; 403 404static const struct dmi_system_id __devinitconst toshiba_ohci1394_dmi_table[] = { 405 { 406 .ident = "Toshiba PS5 based laptop", 407 .matches = { 408 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 409 DMI_MATCH(DMI_PRODUCT_VERSION, "PS5"), 410 }, 411 }, 412 { 413 .ident = "Toshiba PSM4 based laptop", 414 .matches = { 415 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 416 DMI_MATCH(DMI_PRODUCT_VERSION, "PSM4"), 417 }, 418 }, 419 { 420 .ident = "Toshiba A40 based laptop", 421 .matches = { 422 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 423 DMI_MATCH(DMI_PRODUCT_VERSION, "PSA40U"), 424 }, 425 }, 426 { } 427}; 428 429static void __devinit pci_pre_fixup_toshiba_ohci1394(struct pci_dev *dev) 430{ 431 if (!dmi_check_system(toshiba_ohci1394_dmi_table)) 432 return; /* only applies to certain Toshibas (so far) */ 433 434 dev->current_state = PCI_D3cold; 435 pci_read_config_word(dev, PCI_CACHE_LINE_SIZE, &toshiba_line_size); 436} 437DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0x8032, 438 pci_pre_fixup_toshiba_ohci1394); 439 440static void __devinit pci_post_fixup_toshiba_ohci1394(struct pci_dev *dev) 441{ 442 if (!dmi_check_system(toshiba_ohci1394_dmi_table)) 443 return; /* only applies to certain Toshibas (so far) */ 444 445 /* Restore config space on Toshiba laptops */ 446 pci_write_config_word(dev, PCI_CACHE_LINE_SIZE, toshiba_line_size); 447 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, (u8 *)&dev->irq); 448 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 449 pci_resource_start(dev, 0)); 450 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 451 pci_resource_start(dev, 1)); 452} 453DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_TI, 0x8032, 454 pci_post_fixup_toshiba_ohci1394); 455 456 457/* 458 * Prevent the BIOS trapping accesses to the Cyrix CS5530A video device 459 * configuration space. 460 */ 461static void pci_early_fixup_cyrix_5530(struct pci_dev *dev) 462{ 463 u8 r; 464 /* clear 'F4 Video Configuration Trap' bit */ 465 pci_read_config_byte(dev, 0x42, &r); 466 r &= 0xfd; 467 pci_write_config_byte(dev, 0x42, r); 468} 469DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY, 470 pci_early_fixup_cyrix_5530); 471DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY, 472 pci_early_fixup_cyrix_5530); 473 474/* 475 * Siemens Nixdorf AG FSC Multiprocessor Interrupt Controller: 476 * prevent update of the BAR0, which doesn't look like a normal BAR. 477 */ 478static void __devinit pci_siemens_interrupt_controller(struct pci_dev *dev) 479{ 480 dev->resource[0].flags |= IORESOURCE_PCI_FIXED; 481} 482DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SIEMENS, 0x0015, 483 pci_siemens_interrupt_controller); 484 485/* 486 * SB600: Disable BAR1 on device 14.0 to avoid HPET resources from 487 * confusing the PCI engine: 488 */ 489static void sb600_disable_hpet_bar(struct pci_dev *dev) 490{ 491 u8 val; 492 493 /* 494 * The SB600 and SB700 both share the same device 495 * ID, but the PM register 0x55 does something different 496 * for the SB700, so make sure we are dealing with the 497 * SB600 before touching the bit: 498 */ 499 500 pci_read_config_byte(dev, 0x08, &val); 501 502 if (val < 0x2F) { 503 outb(0x55, 0xCD6); 504 val = inb(0xCD7); 505 506 /* Set bit 7 in PM register 0x55 */ 507 outb(0x55, 0xCD6); 508 outb(val | 0x80, 0xCD7); 509 } 510} 511DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x4385, sb600_disable_hpet_bar); 512