1/* 2 * P5 specific Machine Check Exception Reporting 3 * (C) Copyright 2002 Alan Cox <alan@lxorguk.ukuu.org.uk> 4 */ 5#include <linux/interrupt.h> 6#include <linux/kernel.h> 7#include <linux/types.h> 8#include <linux/init.h> 9#include <linux/smp.h> 10 11#include <asm/processor.h> 12#include <asm/system.h> 13#include <asm/mce.h> 14#include <asm/msr.h> 15 16/* By default disabled */ 17int mce_p5_enabled __read_mostly; 18 19/* Machine check handler for Pentium class Intel CPUs: */ 20static void pentium_machine_check(struct pt_regs *regs, long error_code) 21{ 22 u32 loaddr, hi, lotype; 23 24 rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi); 25 rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi); 26 27 printk(KERN_EMERG 28 "CPU#%d: Machine Check Exception: 0x%8X (type 0x%8X).\n", 29 smp_processor_id(), loaddr, lotype); 30 31 if (lotype & (1<<5)) { 32 printk(KERN_EMERG 33 "CPU#%d: Possible thermal failure (CPU on fire ?).\n", 34 smp_processor_id()); 35 } 36 37 add_taint(TAINT_MACHINE_CHECK); 38} 39 40/* Set up machine check reporting for processors with Intel style MCE: */ 41void intel_p5_mcheck_init(struct cpuinfo_x86 *c) 42{ 43 u32 l, h; 44 45 /* Default P5 to off as its often misconnected: */ 46 if (!mce_p5_enabled) 47 return; 48 49 /* Check for MCE support: */ 50 if (!cpu_has(c, X86_FEATURE_MCE)) 51 return; 52 53 machine_check_vector = pentium_machine_check; 54 /* Make sure the vector pointer is visible before we enable MCEs: */ 55 wmb(); 56 57 /* Read registers before enabling: */ 58 rdmsr(MSR_IA32_P5_MC_ADDR, l, h); 59 rdmsr(MSR_IA32_P5_MC_TYPE, l, h); 60 printk(KERN_INFO 61 "Intel old style machine check architecture supported.\n"); 62 63 /* Enable MCE: */ 64 set_in_cr4(X86_CR4_MCE); 65 printk(KERN_INFO 66 "Intel old style machine check reporting enabled on CPU#%d.\n", 67 smp_processor_id()); 68} 69