1#ifndef __SVM_H 2#define __SVM_H 3 4enum { 5 INTERCEPT_INTR, 6 INTERCEPT_NMI, 7 INTERCEPT_SMI, 8 INTERCEPT_INIT, 9 INTERCEPT_VINTR, 10 INTERCEPT_SELECTIVE_CR0, 11 INTERCEPT_STORE_IDTR, 12 INTERCEPT_STORE_GDTR, 13 INTERCEPT_STORE_LDTR, 14 INTERCEPT_STORE_TR, 15 INTERCEPT_LOAD_IDTR, 16 INTERCEPT_LOAD_GDTR, 17 INTERCEPT_LOAD_LDTR, 18 INTERCEPT_LOAD_TR, 19 INTERCEPT_RDTSC, 20 INTERCEPT_RDPMC, 21 INTERCEPT_PUSHF, 22 INTERCEPT_POPF, 23 INTERCEPT_CPUID, 24 INTERCEPT_RSM, 25 INTERCEPT_IRET, 26 INTERCEPT_INTn, 27 INTERCEPT_INVD, 28 INTERCEPT_PAUSE, 29 INTERCEPT_HLT, 30 INTERCEPT_INVLPG, 31 INTERCEPT_INVLPGA, 32 INTERCEPT_IOIO_PROT, 33 INTERCEPT_MSR_PROT, 34 INTERCEPT_TASK_SWITCH, 35 INTERCEPT_FERR_FREEZE, 36 INTERCEPT_SHUTDOWN, 37 INTERCEPT_VMRUN, 38 INTERCEPT_VMMCALL, 39 INTERCEPT_VMLOAD, 40 INTERCEPT_VMSAVE, 41 INTERCEPT_STGI, 42 INTERCEPT_CLGI, 43 INTERCEPT_SKINIT, 44 INTERCEPT_RDTSCP, 45 INTERCEPT_ICEBP, 46 INTERCEPT_WBINVD, 47 INTERCEPT_MONITOR, 48 INTERCEPT_MWAIT, 49 INTERCEPT_MWAIT_COND, 50}; 51 52 53struct __attribute__ ((__packed__)) vmcb_control_area { 54 u16 intercept_cr_read; 55 u16 intercept_cr_write; 56 u16 intercept_dr_read; 57 u16 intercept_dr_write; 58 u32 intercept_exceptions; 59 u64 intercept; 60 u8 reserved_1[42]; 61 u16 pause_filter_count; 62 u64 iopm_base_pa; 63 u64 msrpm_base_pa; 64 u64 tsc_offset; 65 u32 asid; 66 u8 tlb_ctl; 67 u8 reserved_2[3]; 68 u32 int_ctl; 69 u32 int_vector; 70 u32 int_state; 71 u8 reserved_3[4]; 72 u32 exit_code; 73 u32 exit_code_hi; 74 u64 exit_info_1; 75 u64 exit_info_2; 76 u32 exit_int_info; 77 u32 exit_int_info_err; 78 u64 nested_ctl; 79 u8 reserved_4[16]; 80 u32 event_inj; 81 u32 event_inj_err; 82 u64 nested_cr3; 83 u64 lbr_ctl; 84 u64 reserved_5; 85 u64 next_rip; 86 u8 reserved_6[816]; 87}; 88 89 90#define TLB_CONTROL_DO_NOTHING 0 91#define TLB_CONTROL_FLUSH_ALL_ASID 1 92 93#define V_TPR_MASK 0x0f 94 95#define V_IRQ_SHIFT 8 96#define V_IRQ_MASK (1 << V_IRQ_SHIFT) 97 98#define V_INTR_PRIO_SHIFT 16 99#define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT) 100 101#define V_IGN_TPR_SHIFT 20 102#define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT) 103 104#define V_INTR_MASKING_SHIFT 24 105#define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT) 106 107#define SVM_INTERRUPT_SHADOW_MASK 1 108 109#define SVM_IOIO_STR_SHIFT 2 110#define SVM_IOIO_REP_SHIFT 3 111#define SVM_IOIO_SIZE_SHIFT 4 112#define SVM_IOIO_ASIZE_SHIFT 7 113 114#define SVM_IOIO_TYPE_MASK 1 115#define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT) 116#define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT) 117#define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT) 118#define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT) 119 120#define SVM_VM_CR_VALID_MASK 0x001fULL 121#define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL 122#define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL 123 124struct __attribute__ ((__packed__)) vmcb_seg { 125 u16 selector; 126 u16 attrib; 127 u32 limit; 128 u64 base; 129}; 130 131struct __attribute__ ((__packed__)) vmcb_save_area { 132 struct vmcb_seg es; 133 struct vmcb_seg cs; 134 struct vmcb_seg ss; 135 struct vmcb_seg ds; 136 struct vmcb_seg fs; 137 struct vmcb_seg gs; 138 struct vmcb_seg gdtr; 139 struct vmcb_seg ldtr; 140 struct vmcb_seg idtr; 141 struct vmcb_seg tr; 142 u8 reserved_1[43]; 143 u8 cpl; 144 u8 reserved_2[4]; 145 u64 efer; 146 u8 reserved_3[112]; 147 u64 cr4; 148 u64 cr3; 149 u64 cr0; 150 u64 dr7; 151 u64 dr6; 152 u64 rflags; 153 u64 rip; 154 u8 reserved_4[88]; 155 u64 rsp; 156 u8 reserved_5[24]; 157 u64 rax; 158 u64 star; 159 u64 lstar; 160 u64 cstar; 161 u64 sfmask; 162 u64 kernel_gs_base; 163 u64 sysenter_cs; 164 u64 sysenter_esp; 165 u64 sysenter_eip; 166 u64 cr2; 167 u8 reserved_6[32]; 168 u64 g_pat; 169 u64 dbgctl; 170 u64 br_from; 171 u64 br_to; 172 u64 last_excp_from; 173 u64 last_excp_to; 174}; 175 176struct __attribute__ ((__packed__)) vmcb { 177 struct vmcb_control_area control; 178 struct vmcb_save_area save; 179}; 180 181#define SVM_CPUID_FEATURE_SHIFT 2 182#define SVM_CPUID_FUNC 0x8000000a 183 184#define SVM_VM_CR_SVM_DISABLE 4 185 186#define SVM_SELECTOR_S_SHIFT 4 187#define SVM_SELECTOR_DPL_SHIFT 5 188#define SVM_SELECTOR_P_SHIFT 7 189#define SVM_SELECTOR_AVL_SHIFT 8 190#define SVM_SELECTOR_L_SHIFT 9 191#define SVM_SELECTOR_DB_SHIFT 10 192#define SVM_SELECTOR_G_SHIFT 11 193 194#define SVM_SELECTOR_TYPE_MASK (0xf) 195#define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT) 196#define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT) 197#define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT) 198#define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT) 199#define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT) 200#define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT) 201#define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT) 202 203#define SVM_SELECTOR_WRITE_MASK (1 << 1) 204#define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK 205#define SVM_SELECTOR_CODE_MASK (1 << 3) 206 207#define INTERCEPT_CR0_MASK 1 208#define INTERCEPT_CR3_MASK (1 << 3) 209#define INTERCEPT_CR4_MASK (1 << 4) 210#define INTERCEPT_CR8_MASK (1 << 8) 211 212#define INTERCEPT_DR0_MASK 1 213#define INTERCEPT_DR1_MASK (1 << 1) 214#define INTERCEPT_DR2_MASK (1 << 2) 215#define INTERCEPT_DR3_MASK (1 << 3) 216#define INTERCEPT_DR4_MASK (1 << 4) 217#define INTERCEPT_DR5_MASK (1 << 5) 218#define INTERCEPT_DR6_MASK (1 << 6) 219#define INTERCEPT_DR7_MASK (1 << 7) 220 221#define SVM_EVTINJ_VEC_MASK 0xff 222 223#define SVM_EVTINJ_TYPE_SHIFT 8 224#define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT) 225 226#define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT) 227#define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT) 228#define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT) 229#define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT) 230 231#define SVM_EVTINJ_VALID (1 << 31) 232#define SVM_EVTINJ_VALID_ERR (1 << 11) 233 234#define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK 235#define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK 236 237#define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR 238#define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI 239#define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT 240#define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT 241 242#define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID 243#define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR 244 245#define SVM_EXITINFOSHIFT_TS_REASON_IRET 36 246#define SVM_EXITINFOSHIFT_TS_REASON_JMP 38 247#define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44 248 249#define SVM_EXIT_READ_CR0 0x000 250#define SVM_EXIT_READ_CR3 0x003 251#define SVM_EXIT_READ_CR4 0x004 252#define SVM_EXIT_READ_CR8 0x008 253#define SVM_EXIT_WRITE_CR0 0x010 254#define SVM_EXIT_WRITE_CR3 0x013 255#define SVM_EXIT_WRITE_CR4 0x014 256#define SVM_EXIT_WRITE_CR8 0x018 257#define SVM_EXIT_READ_DR0 0x020 258#define SVM_EXIT_READ_DR1 0x021 259#define SVM_EXIT_READ_DR2 0x022 260#define SVM_EXIT_READ_DR3 0x023 261#define SVM_EXIT_READ_DR4 0x024 262#define SVM_EXIT_READ_DR5 0x025 263#define SVM_EXIT_READ_DR6 0x026 264#define SVM_EXIT_READ_DR7 0x027 265#define SVM_EXIT_WRITE_DR0 0x030 266#define SVM_EXIT_WRITE_DR1 0x031 267#define SVM_EXIT_WRITE_DR2 0x032 268#define SVM_EXIT_WRITE_DR3 0x033 269#define SVM_EXIT_WRITE_DR4 0x034 270#define SVM_EXIT_WRITE_DR5 0x035 271#define SVM_EXIT_WRITE_DR6 0x036 272#define SVM_EXIT_WRITE_DR7 0x037 273#define SVM_EXIT_EXCP_BASE 0x040 274#define SVM_EXIT_INTR 0x060 275#define SVM_EXIT_NMI 0x061 276#define SVM_EXIT_SMI 0x062 277#define SVM_EXIT_INIT 0x063 278#define SVM_EXIT_VINTR 0x064 279#define SVM_EXIT_CR0_SEL_WRITE 0x065 280#define SVM_EXIT_IDTR_READ 0x066 281#define SVM_EXIT_GDTR_READ 0x067 282#define SVM_EXIT_LDTR_READ 0x068 283#define SVM_EXIT_TR_READ 0x069 284#define SVM_EXIT_IDTR_WRITE 0x06a 285#define SVM_EXIT_GDTR_WRITE 0x06b 286#define SVM_EXIT_LDTR_WRITE 0x06c 287#define SVM_EXIT_TR_WRITE 0x06d 288#define SVM_EXIT_RDTSC 0x06e 289#define SVM_EXIT_RDPMC 0x06f 290#define SVM_EXIT_PUSHF 0x070 291#define SVM_EXIT_POPF 0x071 292#define SVM_EXIT_CPUID 0x072 293#define SVM_EXIT_RSM 0x073 294#define SVM_EXIT_IRET 0x074 295#define SVM_EXIT_SWINT 0x075 296#define SVM_EXIT_INVD 0x076 297#define SVM_EXIT_PAUSE 0x077 298#define SVM_EXIT_HLT 0x078 299#define SVM_EXIT_INVLPG 0x079 300#define SVM_EXIT_INVLPGA 0x07a 301#define SVM_EXIT_IOIO 0x07b 302#define SVM_EXIT_MSR 0x07c 303#define SVM_EXIT_TASK_SWITCH 0x07d 304#define SVM_EXIT_FERR_FREEZE 0x07e 305#define SVM_EXIT_SHUTDOWN 0x07f 306#define SVM_EXIT_VMRUN 0x080 307#define SVM_EXIT_VMMCALL 0x081 308#define SVM_EXIT_VMLOAD 0x082 309#define SVM_EXIT_VMSAVE 0x083 310#define SVM_EXIT_STGI 0x084 311#define SVM_EXIT_CLGI 0x085 312#define SVM_EXIT_SKINIT 0x086 313#define SVM_EXIT_RDTSCP 0x087 314#define SVM_EXIT_ICEBP 0x088 315#define SVM_EXIT_WBINVD 0x089 316#define SVM_EXIT_MONITOR 0x08a 317#define SVM_EXIT_MWAIT 0x08b 318#define SVM_EXIT_MWAIT_COND 0x08c 319#define SVM_EXIT_NPF 0x400 320 321#define SVM_EXIT_ERR -1 322 323#define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP) 324 325#define SVM_VMLOAD ".byte 0x0f, 0x01, 0xda" 326#define SVM_VMRUN ".byte 0x0f, 0x01, 0xd8" 327#define SVM_VMSAVE ".byte 0x0f, 0x01, 0xdb" 328#define SVM_CLGI ".byte 0x0f, 0x01, 0xdd" 329#define SVM_STGI ".byte 0x0f, 0x01, 0xdc" 330#define SVM_INVLPGA ".byte 0x0f, 0x01, 0xdf" 331 332#endif 333