1#ifndef _ASM_X86_APIC_H 2#define _ASM_X86_APIC_H 3 4#include <linux/cpumask.h> 5#include <linux/delay.h> 6#include <linux/pm.h> 7 8#include <asm/alternative.h> 9#include <asm/cpufeature.h> 10#include <asm/processor.h> 11#include <asm/apicdef.h> 12#include <asm/atomic.h> 13#include <asm/fixmap.h> 14#include <asm/mpspec.h> 15#include <asm/system.h> 16#include <asm/msr.h> 17 18#define ARCH_APICTIMER_STOPS_ON_C3 1 19 20/* 21 * Debugging macros 22 */ 23#define APIC_QUIET 0 24#define APIC_VERBOSE 1 25#define APIC_DEBUG 2 26 27/* 28 * Define the default level of output to be very little 29 * This can be turned up by using apic=verbose for more 30 * information and apic=debug for _lots_ of information. 31 * apic_verbosity is defined in apic.c 32 */ 33#define apic_printk(v, s, a...) do { \ 34 if ((v) <= apic_verbosity) \ 35 printk(s, ##a); \ 36 } while (0) 37 38 39#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 40extern void generic_apic_probe(void); 41#else 42static inline void generic_apic_probe(void) 43{ 44} 45#endif 46 47#ifdef CONFIG_X86_LOCAL_APIC 48 49extern unsigned int apic_verbosity; 50extern int local_apic_timer_c2_ok; 51 52extern int disable_apic; 53 54#ifdef CONFIG_SMP 55extern void __inquire_remote_apic(int apicid); 56#else /* CONFIG_SMP */ 57static inline void __inquire_remote_apic(int apicid) 58{ 59} 60#endif /* CONFIG_SMP */ 61 62static inline void default_inquire_remote_apic(int apicid) 63{ 64 if (apic_verbosity >= APIC_DEBUG) 65 __inquire_remote_apic(apicid); 66} 67 68/* 69 * With 82489DX we can't rely on apic feature bit 70 * retrieved via cpuid but still have to deal with 71 * such an apic chip so we assume that SMP configuration 72 * is found from MP table (64bit case uses ACPI mostly 73 * which set smp presence flag as well so we are safe 74 * to use this helper too). 75 */ 76static inline bool apic_from_smp_config(void) 77{ 78 return smp_found_config && !disable_apic; 79} 80 81/* 82 * Basic functions accessing APICs. 83 */ 84#ifdef CONFIG_PARAVIRT 85#include <asm/paravirt.h> 86#endif 87 88#ifdef CONFIG_X86_64 89extern int is_vsmp_box(void); 90#else 91static inline int is_vsmp_box(void) 92{ 93 return 0; 94} 95#endif 96extern void xapic_wait_icr_idle(void); 97extern u32 safe_xapic_wait_icr_idle(void); 98extern void xapic_icr_write(u32, u32); 99extern int setup_profiling_timer(unsigned int); 100 101static inline void native_apic_mem_write(u32 reg, u32 v) 102{ 103 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 104 105 alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP, 106 ASM_OUTPUT2("=r" (v), "=m" (*addr)), 107 ASM_OUTPUT2("0" (v), "m" (*addr))); 108} 109 110static inline u32 native_apic_mem_read(u32 reg) 111{ 112 return *((volatile u32 *)(APIC_BASE + reg)); 113} 114 115extern void native_apic_wait_icr_idle(void); 116extern u32 native_safe_apic_wait_icr_idle(void); 117extern void native_apic_icr_write(u32 low, u32 id); 118extern u64 native_apic_icr_read(void); 119 120extern int x2apic_mode; 121 122#ifdef CONFIG_X86_X2APIC 123/* 124 * Make previous memory operations globally visible before 125 * sending the IPI through x2apic wrmsr. We need a serializing instruction or 126 * mfence for this. 127 */ 128static inline void x2apic_wrmsr_fence(void) 129{ 130 asm volatile("mfence" : : : "memory"); 131} 132 133static inline void native_apic_msr_write(u32 reg, u32 v) 134{ 135 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 136 reg == APIC_LVR) 137 return; 138 139 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 140} 141 142static inline u32 native_apic_msr_read(u32 reg) 143{ 144 u32 low, high; 145 146 if (reg == APIC_DFR) 147 return -1; 148 149 rdmsr(APIC_BASE_MSR + (reg >> 4), low, high); 150 return low; 151} 152 153static inline void native_x2apic_wait_icr_idle(void) 154{ 155 /* no need to wait for icr idle in x2apic */ 156 return; 157} 158 159static inline u32 native_safe_x2apic_wait_icr_idle(void) 160{ 161 /* no need to wait for icr idle in x2apic */ 162 return 0; 163} 164 165static inline void native_x2apic_icr_write(u32 low, u32 id) 166{ 167 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 168} 169 170static inline u64 native_x2apic_icr_read(void) 171{ 172 unsigned long val; 173 174 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 175 return val; 176} 177 178extern int x2apic_phys; 179extern void check_x2apic(void); 180extern void enable_x2apic(void); 181extern void x2apic_icr_write(u32 low, u32 id); 182static inline int x2apic_enabled(void) 183{ 184 int msr, msr2; 185 186 if (!cpu_has_x2apic) 187 return 0; 188 189 rdmsr(MSR_IA32_APICBASE, msr, msr2); 190 if (msr & X2APIC_ENABLE) 191 return 1; 192 return 0; 193} 194 195#define x2apic_supported() (cpu_has_x2apic) 196static inline void x2apic_force_phys(void) 197{ 198 x2apic_phys = 1; 199} 200#else 201static inline void check_x2apic(void) 202{ 203} 204static inline void enable_x2apic(void) 205{ 206} 207static inline int x2apic_enabled(void) 208{ 209 return 0; 210} 211static inline void x2apic_force_phys(void) 212{ 213} 214 215#define x2apic_preenabled 0 216#define x2apic_supported() 0 217#endif 218 219extern void enable_IR_x2apic(void); 220 221extern int get_physical_broadcast(void); 222 223extern void apic_disable(void); 224extern int lapic_get_maxlvt(void); 225extern void clear_local_APIC(void); 226extern void connect_bsp_APIC(void); 227extern void disconnect_bsp_APIC(int virt_wire_setup); 228extern void disable_local_APIC(void); 229extern void lapic_shutdown(void); 230extern int verify_local_APIC(void); 231extern void cache_APIC_registers(void); 232extern void sync_Arb_IDs(void); 233extern void init_bsp_APIC(void); 234extern void setup_local_APIC(void); 235extern void end_local_APIC_setup(void); 236extern void init_apic_mappings(void); 237extern void setup_boot_APIC_clock(void); 238extern void setup_secondary_APIC_clock(void); 239extern int APIC_init_uniprocessor(void); 240extern void enable_NMI_through_LVT0(void); 241 242#ifdef CONFIG_X86_64 243extern void early_init_lapic_mapping(void); 244extern int apic_is_clustered_box(void); 245#else 246static inline int apic_is_clustered_box(void) 247{ 248 return 0; 249} 250#endif 251 252extern u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask); 253extern u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask); 254 255 256#else /* !CONFIG_X86_LOCAL_APIC */ 257static inline void lapic_shutdown(void) { } 258#define local_apic_timer_c2_ok 1 259static inline void init_apic_mappings(void) { } 260static inline void disable_local_APIC(void) { } 261static inline void apic_disable(void) { } 262# define setup_boot_APIC_clock x86_init_noop 263# define setup_secondary_APIC_clock x86_init_noop 264#endif /* !CONFIG_X86_LOCAL_APIC */ 265 266#ifdef CONFIG_X86_64 267#define SET_APIC_ID(x) (apic->set_apic_id(x)) 268#else 269 270#endif 271 272/* 273 * Copyright 2004 James Cleverdon, IBM. 274 * Subject to the GNU Public License, v.2 275 * 276 * Generic APIC sub-arch data struct. 277 * 278 * Hacked for x86-64 by James Cleverdon from i386 architecture code by 279 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 280 * James Cleverdon. 281 */ 282struct apic { 283 char *name; 284 285 int (*probe)(void); 286 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 287 int (*apic_id_registered)(void); 288 289 u32 irq_delivery_mode; 290 u32 irq_dest_mode; 291 292 const struct cpumask *(*target_cpus)(void); 293 294 int disable_esr; 295 296 int dest_logical; 297 unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid); 298 unsigned long (*check_apicid_present)(int apicid); 299 300 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask); 301 void (*init_apic_ldr)(void); 302 303 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); 304 305 void (*setup_apic_routing)(void); 306 int (*multi_timer_check)(int apic, int irq); 307 int (*apicid_to_node)(int logical_apicid); 308 int (*cpu_to_logical_apicid)(int cpu); 309 int (*cpu_present_to_apicid)(int mps_cpu); 310 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap); 311 void (*setup_portio_remap)(void); 312 int (*check_phys_apicid_present)(int phys_apicid); 313 void (*enable_apic_mode)(void); 314 int (*phys_pkg_id)(int cpuid_apic, int index_msb); 315 316 /* 317 * When one of the next two hooks returns 1 the apic 318 * is switched to this. Essentially they are additional 319 * probe functions: 320 */ 321 int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid); 322 323 unsigned int (*get_apic_id)(unsigned long x); 324 unsigned long (*set_apic_id)(unsigned int id); 325 unsigned long apic_id_mask; 326 327 unsigned int (*cpu_mask_to_apicid)(const struct cpumask *cpumask); 328 unsigned int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask, 329 const struct cpumask *andmask); 330 331 /* ipi */ 332 void (*send_IPI_mask)(const struct cpumask *mask, int vector); 333 void (*send_IPI_mask_allbutself)(const struct cpumask *mask, 334 int vector); 335 void (*send_IPI_allbutself)(int vector); 336 void (*send_IPI_all)(int vector); 337 void (*send_IPI_self)(int vector); 338 339 /* wakeup_secondary_cpu */ 340 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); 341 342 int trampoline_phys_low; 343 int trampoline_phys_high; 344 345 void (*wait_for_init_deassert)(atomic_t *deassert); 346 void (*smp_callin_clear_local_apic)(void); 347 void (*inquire_remote_apic)(int apicid); 348 349 /* apic ops */ 350 u32 (*read)(u32 reg); 351 void (*write)(u32 reg, u32 v); 352 u64 (*icr_read)(void); 353 void (*icr_write)(u32 low, u32 high); 354 void (*wait_icr_idle)(void); 355 u32 (*safe_wait_icr_idle)(void); 356}; 357 358/* 359 * Pointer to the local APIC driver in use on this system (there's 360 * always just one such driver in use - the kernel decides via an 361 * early probing process which one it picks - and then sticks to it): 362 */ 363extern struct apic *apic; 364 365/* 366 * APIC functionality to boot other CPUs - only used on SMP: 367 */ 368#ifdef CONFIG_SMP 369extern atomic_t init_deasserted; 370extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip); 371#endif 372 373#ifdef CONFIG_X86_LOCAL_APIC 374static inline u32 apic_read(u32 reg) 375{ 376 return apic->read(reg); 377} 378 379static inline void apic_write(u32 reg, u32 val) 380{ 381 apic->write(reg, val); 382} 383 384static inline u64 apic_icr_read(void) 385{ 386 return apic->icr_read(); 387} 388 389static inline void apic_icr_write(u32 low, u32 high) 390{ 391 apic->icr_write(low, high); 392} 393 394static inline void apic_wait_icr_idle(void) 395{ 396 apic->wait_icr_idle(); 397} 398 399static inline u32 safe_apic_wait_icr_idle(void) 400{ 401 return apic->safe_wait_icr_idle(); 402} 403 404#else /* CONFIG_X86_LOCAL_APIC */ 405 406static inline u32 apic_read(u32 reg) { return 0; } 407static inline void apic_write(u32 reg, u32 val) { } 408static inline u64 apic_icr_read(void) { return 0; } 409static inline void apic_icr_write(u32 low, u32 high) { } 410static inline void apic_wait_icr_idle(void) { } 411static inline u32 safe_apic_wait_icr_idle(void) { return 0; } 412 413#endif /* CONFIG_X86_LOCAL_APIC */ 414 415static inline void ack_APIC_irq(void) 416{ 417 /* 418 * ack_APIC_irq() actually gets compiled as a single instruction 419 * ... yummie. 420 */ 421 422 /* Docs say use 0 for future compatibility */ 423 apic_write(APIC_EOI, 0); 424} 425 426static inline unsigned default_get_apic_id(unsigned long x) 427{ 428 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); 429 430 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) 431 return (x >> 24) & 0xFF; 432 else 433 return (x >> 24) & 0x0F; 434} 435 436/* 437 * Warm reset vector default position: 438 */ 439#define DEFAULT_TRAMPOLINE_PHYS_LOW 0x467 440#define DEFAULT_TRAMPOLINE_PHYS_HIGH 0x469 441 442#ifdef CONFIG_X86_64 443extern struct apic apic_flat; 444extern struct apic apic_physflat; 445extern struct apic apic_x2apic_cluster; 446extern struct apic apic_x2apic_phys; 447extern int default_acpi_madt_oem_check(char *, char *); 448 449extern void apic_send_IPI_self(int vector); 450 451extern struct apic apic_x2apic_uv_x; 452DECLARE_PER_CPU(int, x2apic_extra_bits); 453 454extern int default_cpu_present_to_apicid(int mps_cpu); 455extern int default_check_phys_apicid_present(int phys_apicid); 456#endif 457 458static inline void default_wait_for_init_deassert(atomic_t *deassert) 459{ 460 while (!atomic_read(deassert)) 461 cpu_relax(); 462 return; 463} 464 465extern void generic_bigsmp_probe(void); 466 467 468#ifdef CONFIG_X86_LOCAL_APIC 469 470#include <asm/smp.h> 471 472#define APIC_DFR_VALUE (APIC_DFR_FLAT) 473 474static inline const struct cpumask *default_target_cpus(void) 475{ 476#ifdef CONFIG_SMP 477 return cpu_online_mask; 478#else 479 return cpumask_of(0); 480#endif 481} 482 483DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid); 484 485 486static inline unsigned int read_apic_id(void) 487{ 488 unsigned int reg; 489 490 reg = apic_read(APIC_ID); 491 492 return apic->get_apic_id(reg); 493} 494 495extern void default_setup_apic_routing(void); 496 497extern struct apic apic_noop; 498 499#ifdef CONFIG_X86_32 500 501extern struct apic apic_default; 502 503/* 504 * Set up the logical destination ID. 505 * 506 * Intel recommends to set DFR, LDR and TPR before enabling 507 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 508 * document number 292116). So here it goes... 509 */ 510extern void default_init_apic_ldr(void); 511 512static inline int default_apic_id_registered(void) 513{ 514 return physid_isset(read_apic_id(), phys_cpu_present_map); 515} 516 517static inline int default_phys_pkg_id(int cpuid_apic, int index_msb) 518{ 519 return cpuid_apic >> index_msb; 520} 521 522extern int default_apicid_to_node(int logical_apicid); 523 524#endif 525 526static inline unsigned int 527default_cpu_mask_to_apicid(const struct cpumask *cpumask) 528{ 529 return cpumask_bits(cpumask)[0] & APIC_ALL_CPUS; 530} 531 532static inline unsigned int 533default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 534 const struct cpumask *andmask) 535{ 536 unsigned long mask1 = cpumask_bits(cpumask)[0]; 537 unsigned long mask2 = cpumask_bits(andmask)[0]; 538 unsigned long mask3 = cpumask_bits(cpu_online_mask)[0]; 539 540 return (unsigned int)(mask1 & mask2 & mask3); 541} 542 543static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid) 544{ 545 return physid_isset(apicid, *map); 546} 547 548static inline unsigned long default_check_apicid_present(int bit) 549{ 550 return physid_isset(bit, phys_cpu_present_map); 551} 552 553static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap) 554{ 555 *retmap = *phys_map; 556} 557 558/* Mapping from cpu number to logical apicid */ 559static inline int default_cpu_to_logical_apicid(int cpu) 560{ 561 return 1 << cpu; 562} 563 564static inline int __default_cpu_present_to_apicid(int mps_cpu) 565{ 566 if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) 567 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); 568 else 569 return BAD_APICID; 570} 571 572static inline int 573__default_check_phys_apicid_present(int phys_apicid) 574{ 575 return physid_isset(phys_apicid, phys_cpu_present_map); 576} 577 578#ifdef CONFIG_X86_32 579static inline int default_cpu_present_to_apicid(int mps_cpu) 580{ 581 return __default_cpu_present_to_apicid(mps_cpu); 582} 583 584static inline int 585default_check_phys_apicid_present(int phys_apicid) 586{ 587 return __default_check_phys_apicid_present(phys_apicid); 588} 589#else 590extern int default_cpu_present_to_apicid(int mps_cpu); 591extern int default_check_phys_apicid_present(int phys_apicid); 592#endif 593 594#endif /* CONFIG_X86_LOCAL_APIC */ 595 596#ifdef CONFIG_X86_32 597extern u8 cpu_2_logical_apicid[NR_CPUS]; 598#endif 599 600#endif /* _ASM_X86_APIC_H */ 601