1/* pci_psycho.c: PSYCHO/U2P specific PCI controller support. 2 * 3 * Copyright (C) 1997, 1998, 1999, 2007 David S. Miller (davem@davemloft.net) 4 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be) 5 * Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com) 6 */ 7 8#include <linux/kernel.h> 9#include <linux/types.h> 10#include <linux/pci.h> 11#include <linux/init.h> 12#include <linux/slab.h> 13#include <linux/interrupt.h> 14#include <linux/of_device.h> 15 16#include <asm/iommu.h> 17#include <asm/irq.h> 18#include <asm/starfire.h> 19#include <asm/prom.h> 20#include <asm/upa.h> 21 22#include "pci_impl.h" 23#include "iommu_common.h" 24#include "psycho_common.h" 25 26#define DRIVER_NAME "psycho" 27#define PFX DRIVER_NAME ": " 28 29/* Misc. PSYCHO PCI controller register offsets and definitions. */ 30#define PSYCHO_CONTROL 0x0010UL 31#define PSYCHO_CONTROL_IMPL 0xf000000000000000UL /* Implementation of this PSYCHO*/ 32#define PSYCHO_CONTROL_VER 0x0f00000000000000UL /* Version of this PSYCHO */ 33#define PSYCHO_CONTROL_MID 0x00f8000000000000UL /* UPA Module ID of PSYCHO */ 34#define PSYCHO_CONTROL_IGN 0x0007c00000000000UL /* Interrupt Group Number */ 35#define PSYCHO_CONTROL_RESV 0x00003ffffffffff0UL /* Reserved */ 36#define PSYCHO_CONTROL_APCKEN 0x0000000000000008UL /* Address Parity Check Enable */ 37#define PSYCHO_CONTROL_APERR 0x0000000000000004UL /* Incoming System Addr Parerr */ 38#define PSYCHO_CONTROL_IAP 0x0000000000000002UL /* Invert UPA Parity */ 39#define PSYCHO_CONTROL_MODE 0x0000000000000001UL /* PSYCHO clock mode */ 40#define PSYCHO_PCIA_CTRL 0x2000UL 41#define PSYCHO_PCIB_CTRL 0x4000UL 42#define PSYCHO_PCICTRL_RESV1 0xfffffff000000000UL /* Reserved */ 43#define PSYCHO_PCICTRL_SBH_ERR 0x0000000800000000UL /* Streaming byte hole error */ 44#define PSYCHO_PCICTRL_SERR 0x0000000400000000UL /* SERR signal asserted */ 45#define PSYCHO_PCICTRL_SPEED 0x0000000200000000UL /* PCI speed (1 is U2P clock) */ 46#define PSYCHO_PCICTRL_RESV2 0x00000001ffc00000UL /* Reserved */ 47#define PSYCHO_PCICTRL_ARB_PARK 0x0000000000200000UL /* PCI arbitration parking */ 48#define PSYCHO_PCICTRL_RESV3 0x00000000001ff800UL /* Reserved */ 49#define PSYCHO_PCICTRL_SBH_INT 0x0000000000000400UL /* Streaming byte hole int enab */ 50#define PSYCHO_PCICTRL_WEN 0x0000000000000200UL /* Power Mgmt Wake Enable */ 51#define PSYCHO_PCICTRL_EEN 0x0000000000000100UL /* PCI Error Interrupt Enable */ 52#define PSYCHO_PCICTRL_RESV4 0x00000000000000c0UL /* Reserved */ 53#define PSYCHO_PCICTRL_AEN 0x000000000000003fUL /* PCI DVMA Arbitration Enable */ 54 55/* PSYCHO error handling support. */ 56 57/* Helper function of IOMMU error checking, which checks out 58 * the state of the streaming buffers. The IOMMU lock is 59 * held when this is called. 60 * 61 * For the PCI error case we know which PBM (and thus which 62 * streaming buffer) caused the error, but for the uncorrectable 63 * error case we do not. So we always check both streaming caches. 64 */ 65#define PSYCHO_STRBUF_CONTROL_A 0x2800UL 66#define PSYCHO_STRBUF_CONTROL_B 0x4800UL 67#define PSYCHO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */ 68#define PSYCHO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */ 69#define PSYCHO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */ 70#define PSYCHO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */ 71#define PSYCHO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */ 72#define PSYCHO_STRBUF_FLUSH_A 0x2808UL 73#define PSYCHO_STRBUF_FLUSH_B 0x4808UL 74#define PSYCHO_STRBUF_FSYNC_A 0x2810UL 75#define PSYCHO_STRBUF_FSYNC_B 0x4810UL 76#define PSYCHO_STC_DATA_A 0xb000UL 77#define PSYCHO_STC_DATA_B 0xc000UL 78#define PSYCHO_STC_ERR_A 0xb400UL 79#define PSYCHO_STC_ERR_B 0xc400UL 80#define PSYCHO_STC_TAG_A 0xb800UL 81#define PSYCHO_STC_TAG_B 0xc800UL 82#define PSYCHO_STC_LINE_A 0xb900UL 83#define PSYCHO_STC_LINE_B 0xc900UL 84 85/* When an Uncorrectable Error or a PCI Error happens, we 86 * interrogate the IOMMU state to see if it is the cause. 87 */ 88#define PSYCHO_IOMMU_CONTROL 0x0200UL 89#define PSYCHO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */ 90#define PSYCHO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */ 91#define PSYCHO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */ 92#define PSYCHO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */ 93#define PSYCHO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */ 94#define PSYCHO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */ 95#define PSYCHO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */ 96#define PSYCHO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */ 97#define PSYCHO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */ 98#define PSYCHO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */ 99#define PSYCHO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */ 100#define PSYCHO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */ 101#define PSYCHO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */ 102#define PSYCHO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */ 103#define PSYCHO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */ 104#define PSYCHO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */ 105#define PSYCHO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */ 106#define PSYCHO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */ 107#define PSYCHO_IOMMU_TSBBASE 0x0208UL 108#define PSYCHO_IOMMU_FLUSH 0x0210UL 109#define PSYCHO_IOMMU_TAG 0xa580UL 110#define PSYCHO_IOMMU_DATA 0xa600UL 111 112/* Uncorrectable Errors. Cause of the error and the address are 113 * recorded in the UE_AFSR and UE_AFAR of PSYCHO. They are errors 114 * relating to UPA interface transactions. 115 */ 116#define PSYCHO_UE_AFSR 0x0030UL 117#define PSYCHO_UEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */ 118#define PSYCHO_UEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */ 119#define PSYCHO_UEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */ 120#define PSYCHO_UEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */ 121#define PSYCHO_UEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */ 122#define PSYCHO_UEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/ 123#define PSYCHO_UEAFSR_RESV1 0x03ff000000000000UL /* Reserved */ 124#define PSYCHO_UEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */ 125#define PSYCHO_UEAFSR_DOFF 0x00000000e0000000UL /* Doubleword Offset */ 126#define PSYCHO_UEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */ 127#define PSYCHO_UEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */ 128#define PSYCHO_UEAFSR_RESV2 0x00000000007fffffUL /* Reserved */ 129#define PSYCHO_UE_AFAR 0x0038UL 130 131static irqreturn_t psycho_ue_intr(int irq, void *dev_id) 132{ 133 struct pci_pbm_info *pbm = dev_id; 134 unsigned long afsr_reg = pbm->controller_regs + PSYCHO_UE_AFSR; 135 unsigned long afar_reg = pbm->controller_regs + PSYCHO_UE_AFAR; 136 unsigned long afsr, afar, error_bits; 137 int reported; 138 139 /* Latch uncorrectable error status. */ 140 afar = upa_readq(afar_reg); 141 afsr = upa_readq(afsr_reg); 142 143 /* Clear the primary/secondary error status bits. */ 144 error_bits = afsr & 145 (PSYCHO_UEAFSR_PPIO | PSYCHO_UEAFSR_PDRD | PSYCHO_UEAFSR_PDWR | 146 PSYCHO_UEAFSR_SPIO | PSYCHO_UEAFSR_SDRD | PSYCHO_UEAFSR_SDWR); 147 if (!error_bits) 148 return IRQ_NONE; 149 upa_writeq(error_bits, afsr_reg); 150 151 /* Log the error. */ 152 printk("%s: Uncorrectable Error, primary error type[%s]\n", 153 pbm->name, 154 (((error_bits & PSYCHO_UEAFSR_PPIO) ? 155 "PIO" : 156 ((error_bits & PSYCHO_UEAFSR_PDRD) ? 157 "DMA Read" : 158 ((error_bits & PSYCHO_UEAFSR_PDWR) ? 159 "DMA Write" : "???"))))); 160 printk("%s: bytemask[%04lx] dword_offset[%lx] UPA_MID[%02lx] was_block(%d)\n", 161 pbm->name, 162 (afsr & PSYCHO_UEAFSR_BMSK) >> 32UL, 163 (afsr & PSYCHO_UEAFSR_DOFF) >> 29UL, 164 (afsr & PSYCHO_UEAFSR_MID) >> 24UL, 165 ((afsr & PSYCHO_UEAFSR_BLK) ? 1 : 0)); 166 printk("%s: UE AFAR [%016lx]\n", pbm->name, afar); 167 printk("%s: UE Secondary errors [", pbm->name); 168 reported = 0; 169 if (afsr & PSYCHO_UEAFSR_SPIO) { 170 reported++; 171 printk("(PIO)"); 172 } 173 if (afsr & PSYCHO_UEAFSR_SDRD) { 174 reported++; 175 printk("(DMA Read)"); 176 } 177 if (afsr & PSYCHO_UEAFSR_SDWR) { 178 reported++; 179 printk("(DMA Write)"); 180 } 181 if (!reported) 182 printk("(none)"); 183 printk("]\n"); 184 185 /* Interrogate both IOMMUs for error status. */ 186 psycho_check_iommu_error(pbm, afsr, afar, UE_ERR); 187 if (pbm->sibling) 188 psycho_check_iommu_error(pbm->sibling, afsr, afar, UE_ERR); 189 190 return IRQ_HANDLED; 191} 192 193/* Correctable Errors. */ 194#define PSYCHO_CE_AFSR 0x0040UL 195#define PSYCHO_CEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */ 196#define PSYCHO_CEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */ 197#define PSYCHO_CEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */ 198#define PSYCHO_CEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */ 199#define PSYCHO_CEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */ 200#define PSYCHO_CEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/ 201#define PSYCHO_CEAFSR_RESV1 0x0300000000000000UL /* Reserved */ 202#define PSYCHO_CEAFSR_ESYND 0x00ff000000000000UL /* Syndrome Bits */ 203#define PSYCHO_CEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */ 204#define PSYCHO_CEAFSR_DOFF 0x00000000e0000000UL /* Double Offset */ 205#define PSYCHO_CEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */ 206#define PSYCHO_CEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */ 207#define PSYCHO_CEAFSR_RESV2 0x00000000007fffffUL /* Reserved */ 208#define PSYCHO_CE_AFAR 0x0040UL 209 210static irqreturn_t psycho_ce_intr(int irq, void *dev_id) 211{ 212 struct pci_pbm_info *pbm = dev_id; 213 unsigned long afsr_reg = pbm->controller_regs + PSYCHO_CE_AFSR; 214 unsigned long afar_reg = pbm->controller_regs + PSYCHO_CE_AFAR; 215 unsigned long afsr, afar, error_bits; 216 int reported; 217 218 /* Latch error status. */ 219 afar = upa_readq(afar_reg); 220 afsr = upa_readq(afsr_reg); 221 222 /* Clear primary/secondary error status bits. */ 223 error_bits = afsr & 224 (PSYCHO_CEAFSR_PPIO | PSYCHO_CEAFSR_PDRD | PSYCHO_CEAFSR_PDWR | 225 PSYCHO_CEAFSR_SPIO | PSYCHO_CEAFSR_SDRD | PSYCHO_CEAFSR_SDWR); 226 if (!error_bits) 227 return IRQ_NONE; 228 upa_writeq(error_bits, afsr_reg); 229 230 /* Log the error. */ 231 printk("%s: Correctable Error, primary error type[%s]\n", 232 pbm->name, 233 (((error_bits & PSYCHO_CEAFSR_PPIO) ? 234 "PIO" : 235 ((error_bits & PSYCHO_CEAFSR_PDRD) ? 236 "DMA Read" : 237 ((error_bits & PSYCHO_CEAFSR_PDWR) ? 238 "DMA Write" : "???"))))); 239 240 printk("%s: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] " 241 "UPA_MID[%02lx] was_block(%d)\n", 242 pbm->name, 243 (afsr & PSYCHO_CEAFSR_ESYND) >> 48UL, 244 (afsr & PSYCHO_CEAFSR_BMSK) >> 32UL, 245 (afsr & PSYCHO_CEAFSR_DOFF) >> 29UL, 246 (afsr & PSYCHO_CEAFSR_MID) >> 24UL, 247 ((afsr & PSYCHO_CEAFSR_BLK) ? 1 : 0)); 248 printk("%s: CE AFAR [%016lx]\n", pbm->name, afar); 249 printk("%s: CE Secondary errors [", pbm->name); 250 reported = 0; 251 if (afsr & PSYCHO_CEAFSR_SPIO) { 252 reported++; 253 printk("(PIO)"); 254 } 255 if (afsr & PSYCHO_CEAFSR_SDRD) { 256 reported++; 257 printk("(DMA Read)"); 258 } 259 if (afsr & PSYCHO_CEAFSR_SDWR) { 260 reported++; 261 printk("(DMA Write)"); 262 } 263 if (!reported) 264 printk("(none)"); 265 printk("]\n"); 266 267 return IRQ_HANDLED; 268} 269 270/* PCI Errors. They are signalled by the PCI bus module since they 271 * are associated with a specific bus segment. 272 */ 273#define PSYCHO_PCI_AFSR_A 0x2010UL 274#define PSYCHO_PCI_AFSR_B 0x4010UL 275#define PSYCHO_PCI_AFAR_A 0x2018UL 276#define PSYCHO_PCI_AFAR_B 0x4018UL 277 278#define PSYCHO_ECC_CTRL 0x0020 279#define PSYCHO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */ 280#define PSYCHO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */ 281#define PSYCHO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */ 282static void psycho_register_error_handlers(struct pci_pbm_info *pbm) 283{ 284 struct platform_device *op = of_find_device_by_node(pbm->op->dev.of_node); 285 unsigned long base = pbm->controller_regs; 286 u64 tmp; 287 int err; 288 289 if (!op) 290 return; 291 292 /* Psycho interrupt property order is: 293 * 0: PCIERR INO for this PBM 294 * 1: UE ERR 295 * 2: CE ERR 296 * 3: POWER FAIL 297 * 4: SPARE HARDWARE 298 * 5: POWER MANAGEMENT 299 */ 300 301 if (op->archdata.num_irqs < 6) 302 return; 303 304 /* We really mean to ignore the return result here. Two 305 * PCI controller share the same interrupt numbers and 306 * drive the same front-end hardware. 307 */ 308 err = request_irq(op->archdata.irqs[1], psycho_ue_intr, IRQF_SHARED, 309 "PSYCHO_UE", pbm); 310 err = request_irq(op->archdata.irqs[2], psycho_ce_intr, IRQF_SHARED, 311 "PSYCHO_CE", pbm); 312 313 /* This one, however, ought not to fail. We can just warn 314 * about it since the system can still operate properly even 315 * if this fails. 316 */ 317 err = request_irq(op->archdata.irqs[0], psycho_pcierr_intr, IRQF_SHARED, 318 "PSYCHO_PCIERR", pbm); 319 if (err) 320 printk(KERN_WARNING "%s: Could not register PCIERR, " 321 "err=%d\n", pbm->name, err); 322 323 /* Enable UE and CE interrupts for controller. */ 324 upa_writeq((PSYCHO_ECCCTRL_EE | 325 PSYCHO_ECCCTRL_UE | 326 PSYCHO_ECCCTRL_CE), base + PSYCHO_ECC_CTRL); 327 328 /* Enable PCI Error interrupts and clear error 329 * bits for each PBM. 330 */ 331 tmp = upa_readq(base + PSYCHO_PCIA_CTRL); 332 tmp |= (PSYCHO_PCICTRL_SERR | 333 PSYCHO_PCICTRL_SBH_ERR | 334 PSYCHO_PCICTRL_EEN); 335 tmp &= ~(PSYCHO_PCICTRL_SBH_INT); 336 upa_writeq(tmp, base + PSYCHO_PCIA_CTRL); 337 338 tmp = upa_readq(base + PSYCHO_PCIB_CTRL); 339 tmp |= (PSYCHO_PCICTRL_SERR | 340 PSYCHO_PCICTRL_SBH_ERR | 341 PSYCHO_PCICTRL_EEN); 342 tmp &= ~(PSYCHO_PCICTRL_SBH_INT); 343 upa_writeq(tmp, base + PSYCHO_PCIB_CTRL); 344} 345 346/* PSYCHO boot time probing and initialization. */ 347static void pbm_config_busmastering(struct pci_pbm_info *pbm) 348{ 349 u8 *addr; 350 351 /* Set cache-line size to 64 bytes, this is actually 352 * a nop but I do it for completeness. 353 */ 354 addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno, 355 0, PCI_CACHE_LINE_SIZE); 356 pci_config_write8(addr, 64 / sizeof(u32)); 357 358 /* Set PBM latency timer to 64 PCI clocks. */ 359 addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno, 360 0, PCI_LATENCY_TIMER); 361 pci_config_write8(addr, 64); 362} 363 364static void __devinit psycho_scan_bus(struct pci_pbm_info *pbm, 365 struct device *parent) 366{ 367 pbm_config_busmastering(pbm); 368 pbm->is_66mhz_capable = 0; 369 pbm->pci_bus = pci_scan_one_pbm(pbm, parent); 370 371 /* After the PCI bus scan is complete, we can register 372 * the error interrupt handlers. 373 */ 374 psycho_register_error_handlers(pbm); 375} 376 377#define PSYCHO_IRQ_RETRY 0x1a00UL 378#define PSYCHO_PCIA_DIAG 0x2020UL 379#define PSYCHO_PCIB_DIAG 0x4020UL 380#define PSYCHO_PCIDIAG_RESV 0xffffffffffffff80UL /* Reserved */ 381#define PSYCHO_PCIDIAG_DRETRY 0x0000000000000040UL /* Disable retry limit */ 382#define PSYCHO_PCIDIAG_DISYNC 0x0000000000000020UL /* Disable DMA wr / irq sync */ 383#define PSYCHO_PCIDIAG_DDWSYNC 0x0000000000000010UL /* Disable DMA wr / PIO rd sync */ 384#define PSYCHO_PCIDIAG_IDDPAR 0x0000000000000008UL /* Invert DMA data parity */ 385#define PSYCHO_PCIDIAG_IPDPAR 0x0000000000000004UL /* Invert PIO data parity */ 386#define PSYCHO_PCIDIAG_IPAPAR 0x0000000000000002UL /* Invert PIO address parity */ 387#define PSYCHO_PCIDIAG_LPBACK 0x0000000000000001UL /* Enable loopback mode */ 388 389static void psycho_controller_hwinit(struct pci_pbm_info *pbm) 390{ 391 u64 tmp; 392 393 upa_writeq(5, pbm->controller_regs + PSYCHO_IRQ_RETRY); 394 395 /* Enable arbiter for all PCI slots. */ 396 tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIA_CTRL); 397 tmp |= PSYCHO_PCICTRL_AEN; 398 upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIA_CTRL); 399 400 tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIB_CTRL); 401 tmp |= PSYCHO_PCICTRL_AEN; 402 upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIB_CTRL); 403 404 /* Disable DMA write / PIO read synchronization on 405 * both PCI bus segments. 406 * [ U2P Erratum 1243770, STP2223BGA data sheet ] 407 */ 408 tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIA_DIAG); 409 tmp |= PSYCHO_PCIDIAG_DDWSYNC; 410 upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIA_DIAG); 411 412 tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIB_DIAG); 413 tmp |= PSYCHO_PCIDIAG_DDWSYNC; 414 upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIB_DIAG); 415} 416 417static void psycho_pbm_strbuf_init(struct pci_pbm_info *pbm, 418 int is_pbm_a) 419{ 420 unsigned long base = pbm->controller_regs; 421 u64 control; 422 423 if (is_pbm_a) { 424 pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_A; 425 pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_A; 426 pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_A; 427 pbm->stc.strbuf_err_stat = base + PSYCHO_STC_ERR_A; 428 pbm->stc.strbuf_tag_diag = base + PSYCHO_STC_TAG_A; 429 pbm->stc.strbuf_line_diag= base + PSYCHO_STC_LINE_A; 430 } else { 431 pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_B; 432 pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_B; 433 pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_B; 434 pbm->stc.strbuf_err_stat = base + PSYCHO_STC_ERR_B; 435 pbm->stc.strbuf_tag_diag = base + PSYCHO_STC_TAG_B; 436 pbm->stc.strbuf_line_diag= base + PSYCHO_STC_LINE_B; 437 } 438 /* PSYCHO's streaming buffer lacks ctx flushing. */ 439 pbm->stc.strbuf_ctxflush = 0; 440 pbm->stc.strbuf_ctxmatch_base = 0; 441 442 pbm->stc.strbuf_flushflag = (volatile unsigned long *) 443 ((((unsigned long)&pbm->stc.__flushflag_buf[0]) 444 + 63UL) 445 & ~63UL); 446 pbm->stc.strbuf_flushflag_pa = (unsigned long) 447 __pa(pbm->stc.strbuf_flushflag); 448 449 /* Enable the streaming buffer. We have to be careful 450 * just in case OBP left it with LRU locking enabled. 451 * 452 * It is possible to control if PBM will be rerun on 453 * line misses. Currently I just retain whatever setting 454 * OBP left us with. All checks so far show it having 455 * a value of zero. 456 */ 457#undef PSYCHO_STRBUF_RERUN_ENABLE 458#undef PSYCHO_STRBUF_RERUN_DISABLE 459 control = upa_readq(pbm->stc.strbuf_control); 460 control |= PSYCHO_STRBUF_CTRL_ENAB; 461 control &= ~(PSYCHO_STRBUF_CTRL_LENAB | PSYCHO_STRBUF_CTRL_LPTR); 462#ifdef PSYCHO_STRBUF_RERUN_ENABLE 463 control &= ~(PSYCHO_STRBUF_CTRL_RRDIS); 464#else 465#ifdef PSYCHO_STRBUF_RERUN_DISABLE 466 control |= PSYCHO_STRBUF_CTRL_RRDIS; 467#endif 468#endif 469 upa_writeq(control, pbm->stc.strbuf_control); 470 471 pbm->stc.strbuf_enabled = 1; 472} 473 474#define PSYCHO_IOSPACE_A 0x002000000UL 475#define PSYCHO_IOSPACE_B 0x002010000UL 476#define PSYCHO_IOSPACE_SIZE 0x00000ffffUL 477#define PSYCHO_MEMSPACE_A 0x100000000UL 478#define PSYCHO_MEMSPACE_B 0x180000000UL 479#define PSYCHO_MEMSPACE_SIZE 0x07fffffffUL 480 481static void __devinit psycho_pbm_init(struct pci_pbm_info *pbm, 482 struct platform_device *op, int is_pbm_a) 483{ 484 psycho_pbm_init_common(pbm, op, "PSYCHO", PBM_CHIP_TYPE_PSYCHO); 485 psycho_pbm_strbuf_init(pbm, is_pbm_a); 486 psycho_scan_bus(pbm, &op->dev); 487} 488 489static struct pci_pbm_info * __devinit psycho_find_sibling(u32 upa_portid) 490{ 491 struct pci_pbm_info *pbm; 492 493 for (pbm = pci_pbm_root; pbm; pbm = pbm->next) { 494 if (pbm->portid == upa_portid) 495 return pbm; 496 } 497 return NULL; 498} 499 500#define PSYCHO_CONFIGSPACE 0x001000000UL 501 502static int __devinit psycho_probe(struct platform_device *op, 503 const struct of_device_id *match) 504{ 505 const struct linux_prom64_registers *pr_regs; 506 struct device_node *dp = op->dev.of_node; 507 struct pci_pbm_info *pbm; 508 struct iommu *iommu; 509 int is_pbm_a, err; 510 u32 upa_portid; 511 512 upa_portid = of_getintprop_default(dp, "upa-portid", 0xff); 513 514 err = -ENOMEM; 515 pbm = kzalloc(sizeof(*pbm), GFP_KERNEL); 516 if (!pbm) { 517 printk(KERN_ERR PFX "Cannot allocate pci_pbm_info.\n"); 518 goto out_err; 519 } 520 521 pbm->sibling = psycho_find_sibling(upa_portid); 522 if (pbm->sibling) { 523 iommu = pbm->sibling->iommu; 524 } else { 525 iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL); 526 if (!iommu) { 527 printk(KERN_ERR PFX "Cannot allocate PBM iommu.\n"); 528 goto out_free_controller; 529 } 530 } 531 532 pbm->iommu = iommu; 533 pbm->portid = upa_portid; 534 535 pr_regs = of_get_property(dp, "reg", NULL); 536 err = -ENODEV; 537 if (!pr_regs) { 538 printk(KERN_ERR PFX "No reg property.\n"); 539 goto out_free_iommu; 540 } 541 542 is_pbm_a = ((pr_regs[0].phys_addr & 0x6000) == 0x2000); 543 544 pbm->controller_regs = pr_regs[2].phys_addr; 545 pbm->config_space = (pr_regs[2].phys_addr + PSYCHO_CONFIGSPACE); 546 547 if (is_pbm_a) { 548 pbm->pci_afsr = pbm->controller_regs + PSYCHO_PCI_AFSR_A; 549 pbm->pci_afar = pbm->controller_regs + PSYCHO_PCI_AFAR_A; 550 pbm->pci_csr = pbm->controller_regs + PSYCHO_PCIA_CTRL; 551 } else { 552 pbm->pci_afsr = pbm->controller_regs + PSYCHO_PCI_AFSR_B; 553 pbm->pci_afar = pbm->controller_regs + PSYCHO_PCI_AFAR_B; 554 pbm->pci_csr = pbm->controller_regs + PSYCHO_PCIB_CTRL; 555 } 556 557 psycho_controller_hwinit(pbm); 558 if (!pbm->sibling) { 559 err = psycho_iommu_init(pbm, 128, 0xc0000000, 560 0xffffffff, PSYCHO_CONTROL); 561 if (err) 562 goto out_free_iommu; 563 564 /* If necessary, hook us up for starfire IRQ translations. */ 565 if (this_is_starfire) 566 starfire_hookup(pbm->portid); 567 } 568 569 psycho_pbm_init(pbm, op, is_pbm_a); 570 571 pbm->next = pci_pbm_root; 572 pci_pbm_root = pbm; 573 574 if (pbm->sibling) 575 pbm->sibling->sibling = pbm; 576 577 dev_set_drvdata(&op->dev, pbm); 578 579 return 0; 580 581out_free_iommu: 582 if (!pbm->sibling) 583 kfree(pbm->iommu); 584 585out_free_controller: 586 kfree(pbm); 587 588out_err: 589 return err; 590} 591 592static struct of_device_id __initdata psycho_match[] = { 593 { 594 .name = "pci", 595 .compatible = "pci108e,8000", 596 }, 597 {}, 598}; 599 600static struct of_platform_driver psycho_driver = { 601 .driver = { 602 .name = DRIVER_NAME, 603 .owner = THIS_MODULE, 604 .of_match_table = psycho_match, 605 }, 606 .probe = psycho_probe, 607}; 608 609static int __init psycho_init(void) 610{ 611 return of_register_platform_driver(&psycho_driver); 612} 613 614subsys_initcall(psycho_init); 615