1/* 2 * Low-Level PCI Express Support for the SH7786 3 * 4 * Copyright (C) 2009 - 2010 Paul Mundt 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10#include <linux/pci.h> 11#include <linux/init.h> 12#include <linux/kernel.h> 13#include <linux/io.h> 14#include <linux/delay.h> 15#include <linux/slab.h> 16#include "pcie-sh7786.h" 17#include <asm/sizes.h> 18 19struct sh7786_pcie_port { 20 struct pci_channel *hose; 21 unsigned int index; 22 int endpoint; 23 int link; 24}; 25 26static struct sh7786_pcie_port *sh7786_pcie_ports; 27static unsigned int nr_ports; 28 29static struct sh7786_pcie_hwops { 30 int (*core_init)(void); 31 int (*port_init_hw)(struct sh7786_pcie_port *port); 32} *sh7786_pcie_hwops; 33 34static struct resource sh7786_pci0_resources[] = { 35 { 36 .name = "PCIe0 IO", 37 .start = 0xfd000000, 38 .end = 0xfd000000 + SZ_8M - 1, 39 .flags = IORESOURCE_IO, 40 }, { 41 .name = "PCIe0 MEM 0", 42 .start = 0xc0000000, 43 .end = 0xc0000000 + SZ_512M - 1, 44 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT, 45 }, { 46 .name = "PCIe0 MEM 1", 47 .start = 0x10000000, 48 .end = 0x10000000 + SZ_64M - 1, 49 .flags = IORESOURCE_MEM, 50 }, { 51 .name = "PCIe0 MEM 2", 52 .start = 0xfe100000, 53 .end = 0xfe100000 + SZ_1M - 1, 54 }, 55}; 56 57static struct resource sh7786_pci1_resources[] = { 58 { 59 .name = "PCIe1 IO", 60 .start = 0xfd800000, 61 .end = 0xfd800000 + SZ_8M - 1, 62 .flags = IORESOURCE_IO, 63 }, { 64 .name = "PCIe1 MEM 0", 65 .start = 0xa0000000, 66 .end = 0xa0000000 + SZ_512M - 1, 67 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT, 68 }, { 69 .name = "PCIe1 MEM 1", 70 .start = 0x30000000, 71 .end = 0x30000000 + SZ_256M - 1, 72 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT, 73 }, { 74 .name = "PCIe1 MEM 2", 75 .start = 0xfe300000, 76 .end = 0xfe300000 + SZ_1M - 1, 77 }, 78}; 79 80static struct resource sh7786_pci2_resources[] = { 81 { 82 .name = "PCIe2 IO", 83 .start = 0xfc800000, 84 .end = 0xfc800000 + SZ_4M - 1, 85 }, { 86 .name = "PCIe2 MEM 0", 87 .start = 0x80000000, 88 .end = 0x80000000 + SZ_512M - 1, 89 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT, 90 }, { 91 .name = "PCIe2 MEM 1", 92 .start = 0x20000000, 93 .end = 0x20000000 + SZ_256M - 1, 94 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT, 95 }, { 96 .name = "PCIe2 MEM 2", 97 .start = 0xfcd00000, 98 .end = 0xfcd00000 + SZ_1M - 1, 99 }, 100}; 101 102extern struct pci_ops sh7786_pci_ops; 103 104#define DEFINE_CONTROLLER(start, idx) \ 105{ \ 106 .pci_ops = &sh7786_pci_ops, \ 107 .resources = sh7786_pci##idx##_resources, \ 108 .nr_resources = ARRAY_SIZE(sh7786_pci##idx##_resources), \ 109 .reg_base = start, \ 110 .mem_offset = 0, \ 111 .io_offset = 0, \ 112} 113 114static struct pci_channel sh7786_pci_channels[] = { 115 DEFINE_CONTROLLER(0xfe000000, 0), 116 DEFINE_CONTROLLER(0xfe200000, 1), 117 DEFINE_CONTROLLER(0xfcc00000, 2), 118}; 119 120static int phy_wait_for_ack(struct pci_channel *chan) 121{ 122 unsigned int timeout = 100; 123 124 while (timeout--) { 125 if (pci_read_reg(chan, SH4A_PCIEPHYADRR) & (1 << BITS_ACK)) 126 return 0; 127 128 udelay(100); 129 } 130 131 return -ETIMEDOUT; 132} 133 134static int pci_wait_for_irq(struct pci_channel *chan, unsigned int mask) 135{ 136 unsigned int timeout = 100; 137 138 while (timeout--) { 139 if ((pci_read_reg(chan, SH4A_PCIEINTR) & mask) == mask) 140 return 0; 141 142 udelay(100); 143 } 144 145 return -ETIMEDOUT; 146} 147 148static void phy_write_reg(struct pci_channel *chan, unsigned int addr, 149 unsigned int lane, unsigned int data) 150{ 151 unsigned long phyaddr, ctrl; 152 153 phyaddr = (1 << BITS_CMD) + ((lane & 0xf) << BITS_LANE) + 154 ((addr & 0xff) << BITS_ADR); 155 156 /* Enable clock */ 157 ctrl = pci_read_reg(chan, SH4A_PCIEPHYCTLR); 158 ctrl |= (1 << BITS_CKE); 159 pci_write_reg(chan, ctrl, SH4A_PCIEPHYCTLR); 160 161 /* Set write data */ 162 pci_write_reg(chan, data, SH4A_PCIEPHYDOUTR); 163 pci_write_reg(chan, phyaddr, SH4A_PCIEPHYADRR); 164 165 phy_wait_for_ack(chan); 166 167 /* Clear command */ 168 pci_write_reg(chan, 0, SH4A_PCIEPHYADRR); 169 170 phy_wait_for_ack(chan); 171 172 /* Disable clock */ 173 ctrl = pci_read_reg(chan, SH4A_PCIEPHYCTLR); 174 ctrl &= ~(1 << BITS_CKE); 175 pci_write_reg(chan, ctrl, SH4A_PCIEPHYCTLR); 176} 177 178static int phy_init(struct pci_channel *chan) 179{ 180 unsigned int timeout = 100; 181 182 /* Initialize the phy */ 183 phy_write_reg(chan, 0x60, 0xf, 0x004b008b); 184 phy_write_reg(chan, 0x61, 0xf, 0x00007b41); 185 phy_write_reg(chan, 0x64, 0xf, 0x00ff4f00); 186 phy_write_reg(chan, 0x65, 0xf, 0x09070907); 187 phy_write_reg(chan, 0x66, 0xf, 0x00000010); 188 phy_write_reg(chan, 0x74, 0xf, 0x0007001c); 189 phy_write_reg(chan, 0x79, 0xf, 0x01fc000d); 190 191 /* Deassert Standby */ 192 phy_write_reg(chan, 0x67, 0xf, 0x00000400); 193 194 while (timeout--) { 195 if (pci_read_reg(chan, SH4A_PCIEPHYSR)) 196 return 0; 197 198 udelay(100); 199 } 200 201 return -ETIMEDOUT; 202} 203 204static int pcie_init(struct sh7786_pcie_port *port) 205{ 206 struct pci_channel *chan = port->hose; 207 unsigned int data; 208 phys_addr_t memphys; 209 size_t memsize; 210 int ret, i; 211 212 /* Begin initialization */ 213 pci_write_reg(chan, 0, SH4A_PCIETCTLR); 214 215 /* Initialize as type1. */ 216 data = pci_read_reg(chan, SH4A_PCIEPCICONF3); 217 data &= ~(0x7f << 16); 218 data |= PCI_HEADER_TYPE_BRIDGE << 16; 219 pci_write_reg(chan, data, SH4A_PCIEPCICONF3); 220 221 /* Initialize default capabilities. */ 222 data = pci_read_reg(chan, SH4A_PCIEEXPCAP0); 223 data &= ~(PCI_EXP_FLAGS_TYPE << 16); 224 225 if (port->endpoint) 226 data |= PCI_EXP_TYPE_ENDPOINT << 20; 227 else 228 data |= PCI_EXP_TYPE_ROOT_PORT << 20; 229 230 data |= PCI_CAP_ID_EXP; 231 pci_write_reg(chan, data, SH4A_PCIEEXPCAP0); 232 233 /* Enable data link layer active state reporting */ 234 pci_write_reg(chan, PCI_EXP_LNKCAP_DLLLARC, SH4A_PCIEEXPCAP3); 235 236 /* Enable extended sync and ASPM L0s support */ 237 data = pci_read_reg(chan, SH4A_PCIEEXPCAP4); 238 data &= ~PCI_EXP_LNKCTL_ASPMC; 239 data |= PCI_EXP_LNKCTL_ES | 1; 240 pci_write_reg(chan, data, SH4A_PCIEEXPCAP4); 241 242 /* Write out the physical slot number */ 243 data = pci_read_reg(chan, SH4A_PCIEEXPCAP5); 244 data &= ~PCI_EXP_SLTCAP_PSN; 245 data |= (port->index + 1) << 19; 246 pci_write_reg(chan, data, SH4A_PCIEEXPCAP5); 247 248 /* Set the completion timer timeout to the maximum 32ms. */ 249 data = pci_read_reg(chan, SH4A_PCIETLCTLR); 250 data &= ~0x3f00; 251 data |= 0x32 << 8; 252 pci_write_reg(chan, data, SH4A_PCIETLCTLR); 253 254 /* 255 * Set fast training sequences to the maximum 255, 256 * and enable MAC data scrambling. 257 */ 258 data = pci_read_reg(chan, SH4A_PCIEMACCTLR); 259 data &= ~PCIEMACCTLR_SCR_DIS; 260 data |= (0xff << 16); 261 pci_write_reg(chan, data, SH4A_PCIEMACCTLR); 262 263 memphys = __pa(memory_start); 264 memsize = roundup_pow_of_two(memory_end - memory_start); 265 266 /* 267 * If there's more than 512MB of memory, we need to roll over to 268 * LAR1/LAMR1. 269 */ 270 if (memsize > SZ_512M) { 271 __raw_writel(memphys + SZ_512M, chan->reg_base + SH4A_PCIELAR1); 272 __raw_writel(((memsize - SZ_512M) - SZ_256) | 1, 273 chan->reg_base + SH4A_PCIELAMR1); 274 memsize = SZ_512M; 275 } else { 276 /* 277 * Otherwise just zero it out and disable it. 278 */ 279 __raw_writel(0, chan->reg_base + SH4A_PCIELAR1); 280 __raw_writel(0, chan->reg_base + SH4A_PCIELAMR1); 281 } 282 283 /* 284 * LAR0/LAMR0 covers up to the first 512MB, which is enough to 285 * cover all of lowmem on most platforms. 286 */ 287 __raw_writel(memphys, chan->reg_base + SH4A_PCIELAR0); 288 __raw_writel((memsize - SZ_256) | 1, chan->reg_base + SH4A_PCIELAMR0); 289 290 /* Finish initialization */ 291 data = pci_read_reg(chan, SH4A_PCIETCTLR); 292 data |= 0x1; 293 pci_write_reg(chan, data, SH4A_PCIETCTLR); 294 295 /* Enable DL_Active Interrupt generation */ 296 data = pci_read_reg(chan, SH4A_PCIEDLINTENR); 297 data |= PCIEDLINTENR_DLL_ACT_ENABLE; 298 pci_write_reg(chan, data, SH4A_PCIEDLINTENR); 299 300 /* Disable MAC data scrambling. */ 301 data = pci_read_reg(chan, SH4A_PCIEMACCTLR); 302 data |= PCIEMACCTLR_SCR_DIS | (0xff << 16); 303 pci_write_reg(chan, data, SH4A_PCIEMACCTLR); 304 305 ret = pci_wait_for_irq(chan, MASK_INT_TX_CTRL); 306 if (unlikely(ret != 0)) 307 return -ENODEV; 308 309 data = pci_read_reg(chan, SH4A_PCIEPCICONF1); 310 data &= ~(PCI_STATUS_DEVSEL_MASK << 16); 311 data |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | 312 (PCI_STATUS_CAP_LIST | PCI_STATUS_DEVSEL_FAST) << 16; 313 pci_write_reg(chan, data, SH4A_PCIEPCICONF1); 314 315 pci_write_reg(chan, 0x80888000, SH4A_PCIETXVC0DCTLR); 316 pci_write_reg(chan, 0x00222000, SH4A_PCIERXVC0DCTLR); 317 318 wmb(); 319 320 data = pci_read_reg(chan, SH4A_PCIEMACSR); 321 printk(KERN_NOTICE "PCI: PCIe#%d link width %d\n", 322 port->index, (data >> 20) & 0x3f); 323 324 325 for (i = 0; i < chan->nr_resources; i++) { 326 struct resource *res = chan->resources + i; 327 resource_size_t size; 328 u32 enable_mask; 329 330 pci_write_reg(chan, 0x00000000, SH4A_PCIEPTCTLR(i)); 331 332 size = resource_size(res); 333 334 /* 335 * The PAMR mask is calculated in units of 256kB, which 336 * keeps things pretty simple. 337 */ 338 __raw_writel(((roundup_pow_of_two(size) / SZ_256K) - 1) << 18, 339 chan->reg_base + SH4A_PCIEPAMR(i)); 340 341 pci_write_reg(chan, 0x00000000, SH4A_PCIEPARH(i)); 342 pci_write_reg(chan, 0x00000000, SH4A_PCIEPARL(i)); 343 344 enable_mask = MASK_PARE; 345 if (res->flags & IORESOURCE_IO) 346 enable_mask |= MASK_SPC; 347 348 pci_write_reg(chan, enable_mask, SH4A_PCIEPTCTLR(i)); 349 } 350 351 return 0; 352} 353 354int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin) 355{ 356 return 71; 357} 358 359static int sh7786_pcie_core_init(void) 360{ 361 /* Return the number of ports */ 362 return test_mode_pin(MODE_PIN12) ? 3 : 2; 363} 364 365static int __devinit sh7786_pcie_init_hw(struct sh7786_pcie_port *port) 366{ 367 int ret; 368 369 ret = phy_init(port->hose); 370 if (unlikely(ret < 0)) 371 return ret; 372 373 /* 374 * Check if we are configured in endpoint or root complex mode, 375 * this is a fixed pin setting that applies to all PCIe ports. 376 */ 377 port->endpoint = test_mode_pin(MODE_PIN11); 378 379 ret = pcie_init(port); 380 if (unlikely(ret < 0)) 381 return ret; 382 383 return register_pci_controller(port->hose); 384} 385 386static struct sh7786_pcie_hwops sh7786_65nm_pcie_hwops __initdata = { 387 .core_init = sh7786_pcie_core_init, 388 .port_init_hw = sh7786_pcie_init_hw, 389}; 390 391static int __init sh7786_pcie_init(void) 392{ 393 int ret = 0, i; 394 395 printk(KERN_NOTICE "PCI: Starting intialization.\n"); 396 397 sh7786_pcie_hwops = &sh7786_65nm_pcie_hwops; 398 399 nr_ports = sh7786_pcie_hwops->core_init(); 400 BUG_ON(nr_ports > ARRAY_SIZE(sh7786_pci_channels)); 401 402 if (unlikely(nr_ports == 0)) 403 return -ENODEV; 404 405 sh7786_pcie_ports = kzalloc(nr_ports * sizeof(struct sh7786_pcie_port), 406 GFP_KERNEL); 407 if (unlikely(!sh7786_pcie_ports)) 408 return -ENOMEM; 409 410 printk(KERN_NOTICE "PCI: probing %d ports.\n", nr_ports); 411 412 for (i = 0; i < nr_ports; i++) { 413 struct sh7786_pcie_port *port = sh7786_pcie_ports + i; 414 415 port->index = i; 416 port->hose = sh7786_pci_channels + i; 417 port->hose->io_map_base = port->hose->resources[0].start; 418 419 ret |= sh7786_pcie_hwops->port_init_hw(port); 420 } 421 422 if (unlikely(ret)) 423 return ret; 424 425 return 0; 426} 427arch_initcall(sh7786_pcie_init); 428