1/* 2 * June 2006 steve.glendinning@smsc.com 3 * 4 * Polaris-specific resource declaration 5 * 6 */ 7 8#include <linux/init.h> 9#include <linux/interrupt.h> 10#include <linux/irq.h> 11#include <linux/platform_device.h> 12#include <linux/smsc911x.h> 13#include <linux/io.h> 14#include <asm/irq.h> 15#include <asm/machvec.h> 16#include <asm/heartbeat.h> 17#include <cpu/gpio.h> 18#include <mach-se/mach/se.h> 19 20#define BCR2 (0xFFFFFF62) 21#define WCR2 (0xFFFFFF66) 22#define AREA5_WAIT_CTRL (0x1C00) 23#define WAIT_STATES_10 (0x7) 24 25static struct resource smsc911x_resources[] = { 26 [0] = { 27 .name = "smsc911x-memory", 28 .start = PA_EXT5, 29 .end = PA_EXT5 + 0x1fff, 30 .flags = IORESOURCE_MEM, 31 }, 32 [1] = { 33 .name = "smsc911x-irq", 34 .start = IRQ0_IRQ, 35 .end = IRQ0_IRQ, 36 .flags = IORESOURCE_IRQ, 37 }, 38}; 39 40static struct smsc911x_platform_config smsc911x_config = { 41 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, 42 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, 43 .flags = SMSC911X_USE_32BIT, 44 .phy_interface = PHY_INTERFACE_MODE_MII, 45}; 46 47static struct platform_device smsc911x_device = { 48 .name = "smsc911x", 49 .id = 0, 50 .num_resources = ARRAY_SIZE(smsc911x_resources), 51 .resource = smsc911x_resources, 52 .dev = { 53 .platform_data = &smsc911x_config, 54 }, 55}; 56 57static unsigned char heartbeat_bit_pos[] = { 0, 1, 2, 3 }; 58 59static struct heartbeat_data heartbeat_data = { 60 .bit_pos = heartbeat_bit_pos, 61 .nr_bits = ARRAY_SIZE(heartbeat_bit_pos), 62}; 63 64static struct resource heartbeat_resource = { 65 .start = PORT_PCDR, 66 .end = PORT_PCDR, 67 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT, 68}; 69 70static struct platform_device heartbeat_device = { 71 .name = "heartbeat", 72 .id = -1, 73 .dev = { 74 .platform_data = &heartbeat_data, 75 }, 76 .num_resources = 1, 77 .resource = &heartbeat_resource, 78}; 79 80static struct platform_device *polaris_devices[] __initdata = { 81 &smsc911x_device, 82 &heartbeat_device, 83}; 84 85static int __init polaris_initialise(void) 86{ 87 u16 wcr, bcr_mask; 88 89 printk(KERN_INFO "Configuring Polaris external bus\n"); 90 91 /* Configure area 5 with 2 wait states */ 92 wcr = __raw_readw(WCR2); 93 wcr &= (~AREA5_WAIT_CTRL); 94 wcr |= (WAIT_STATES_10 << 10); 95 __raw_writew(wcr, WCR2); 96 97 /* Configure area 5 for 32-bit access */ 98 bcr_mask = __raw_readw(BCR2); 99 bcr_mask |= 1 << 10; 100 __raw_writew(bcr_mask, BCR2); 101 102 return platform_add_devices(polaris_devices, 103 ARRAY_SIZE(polaris_devices)); 104} 105arch_initcall(polaris_initialise); 106 107static struct ipr_data ipr_irq_table[] = { 108 /* External IRQs */ 109 { IRQ0_IRQ, 0, 0, 1, }, /* IRQ0 */ 110 { IRQ1_IRQ, 0, 4, 1, }, /* IRQ1 */ 111}; 112 113static unsigned long ipr_offsets[] = { 114 INTC_IPRC 115}; 116 117static struct ipr_desc ipr_irq_desc = { 118 .ipr_offsets = ipr_offsets, 119 .nr_offsets = ARRAY_SIZE(ipr_offsets), 120 121 .ipr_data = ipr_irq_table, 122 .nr_irqs = ARRAY_SIZE(ipr_irq_table), 123 .chip = { 124 .name = "sh7709-ext", 125 }, 126}; 127 128static void __init init_polaris_irq(void) 129{ 130 /* Disable all interrupts */ 131 __raw_writew(0, BCR_ILCRA); 132 __raw_writew(0, BCR_ILCRB); 133 __raw_writew(0, BCR_ILCRC); 134 __raw_writew(0, BCR_ILCRD); 135 __raw_writew(0, BCR_ILCRE); 136 __raw_writew(0, BCR_ILCRF); 137 __raw_writew(0, BCR_ILCRG); 138 139 register_ipr_controller(&ipr_irq_desc); 140} 141 142static struct sh_machine_vector mv_polaris __initmv = { 143 .mv_name = "Polaris", 144 .mv_nr_irqs = 61, 145 .mv_init_irq = init_polaris_irq, 146}; 147