• Home
  • History
  • Annotate
  • Line#
  • Navigate
  • Raw
  • Download
  • only in /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mn10300/include/asm/
1/* MN10300 Cache flushing
2 *
3 * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public Licence
8 * as published by the Free Software Foundation; either version
9 * 2 of the Licence, or (at your option) any later version.
10 */
11#ifndef _ASM_CACHEFLUSH_H
12#define _ASM_CACHEFLUSH_H
13
14#ifndef __ASSEMBLY__
15
16/* Keep includes the same across arches.  */
17#include <linux/mm.h>
18
19/*
20 * virtually-indexed cache management (our cache is physically indexed)
21 */
22#define flush_cache_all()			do {} while (0)
23#define flush_cache_mm(mm)			do {} while (0)
24#define flush_cache_dup_mm(mm)			do {} while (0)
25#define flush_cache_range(mm, start, end)	do {} while (0)
26#define flush_cache_page(vma, vmaddr, pfn)	do {} while (0)
27#define flush_cache_vmap(start, end)		do {} while (0)
28#define flush_cache_vunmap(start, end)		do {} while (0)
29#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
30#define flush_dcache_page(page)			do {} while (0)
31#define flush_dcache_mmap_lock(mapping)		do {} while (0)
32#define flush_dcache_mmap_unlock(mapping)	do {} while (0)
33
34/*
35 * physically-indexed cache management
36 */
37#ifndef CONFIG_MN10300_CACHE_DISABLED
38
39extern void flush_icache_range(unsigned long start, unsigned long end);
40extern void flush_icache_page(struct vm_area_struct *vma, struct page *pg);
41
42#else
43
44#define flush_icache_range(start, end)		do {} while (0)
45#define flush_icache_page(vma, pg)		do {} while (0)
46
47#endif
48
49#define flush_icache_user_range(vma, pg, adr, len) \
50	flush_icache_range(adr, adr + len)
51
52#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
53	do {					\
54		memcpy(dst, src, len);		\
55		flush_icache_page(vma, page);	\
56	} while (0)
57
58#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
59	memcpy(dst, src, len)
60
61/*
62 * primitive routines
63 */
64#ifndef CONFIG_MN10300_CACHE_DISABLED
65extern void mn10300_icache_inv(void);
66extern void mn10300_dcache_inv(void);
67extern void mn10300_dcache_inv_page(unsigned start);
68extern void mn10300_dcache_inv_range(unsigned start, unsigned end);
69extern void mn10300_dcache_inv_range2(unsigned start, unsigned size);
70#ifdef CONFIG_MN10300_CACHE_WBACK
71extern void mn10300_dcache_flush(void);
72extern void mn10300_dcache_flush_page(unsigned start);
73extern void mn10300_dcache_flush_range(unsigned start, unsigned end);
74extern void mn10300_dcache_flush_range2(unsigned start, unsigned size);
75extern void mn10300_dcache_flush_inv(void);
76extern void mn10300_dcache_flush_inv_page(unsigned start);
77extern void mn10300_dcache_flush_inv_range(unsigned start, unsigned end);
78extern void mn10300_dcache_flush_inv_range2(unsigned start, unsigned size);
79#else
80#define mn10300_dcache_flush()				do {} while (0)
81#define mn10300_dcache_flush_page(start)		do {} while (0)
82#define mn10300_dcache_flush_range(start, end)		do {} while (0)
83#define mn10300_dcache_flush_range2(start, size)	do {} while (0)
84#define mn10300_dcache_flush_inv()			mn10300_dcache_inv()
85#define mn10300_dcache_flush_inv_page(start) \
86	mn10300_dcache_inv_page((start))
87#define mn10300_dcache_flush_inv_range(start, end) \
88	mn10300_dcache_inv_range((start), (end))
89#define mn10300_dcache_flush_inv_range2(start, size) \
90	mn10300_dcache_inv_range2((start), (size))
91#endif /* CONFIG_MN10300_CACHE_WBACK */
92#else
93#define mn10300_icache_inv()				do {} while (0)
94#define mn10300_dcache_inv()				do {} while (0)
95#define mn10300_dcache_inv_page(start)			do {} while (0)
96#define mn10300_dcache_inv_range(start, end)		do {} while (0)
97#define mn10300_dcache_inv_range2(start, size)		do {} while (0)
98#define mn10300_dcache_flush()				do {} while (0)
99#define mn10300_dcache_flush_inv_page(start)		do {} while (0)
100#define mn10300_dcache_flush_inv()			do {} while (0)
101#define mn10300_dcache_flush_inv_range(start, end)	do {} while (0)
102#define mn10300_dcache_flush_inv_range2(start, size)	do {} while (0)
103#define mn10300_dcache_flush_page(start)		do {} while (0)
104#define mn10300_dcache_flush_range(start, end)		do {} while (0)
105#define mn10300_dcache_flush_range2(start, size)	do {} while (0)
106#endif /* CONFIG_MN10300_CACHE_DISABLED */
107
108/*
109 * internal debugging function
110 */
111#ifdef CONFIG_DEBUG_PAGEALLOC
112extern void kernel_map_pages(struct page *page, int numpages, int enable);
113#endif
114
115#endif /* __ASSEMBLY__ */
116
117#endif /* _ASM_CACHEFLUSH_H */
118