1/* 2 * Toshiba rbtx4927 specific setup 3 * 4 * Author: MontaVista Software, Inc. 5 * source@mvista.com 6 * 7 * Copyright 2001-2002 MontaVista Software Inc. 8 * 9 * Copyright (C) 1996, 97, 2001, 04 Ralf Baechle (ralf@linux-mips.org) 10 * Copyright (C) 2000 RidgeRun, Inc. 11 * Author: RidgeRun, Inc. 12 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com 13 * 14 * Copyright 2001 MontaVista Software Inc. 15 * Author: jsun@mvista.com or jsun@junsun.net 16 * 17 * Copyright 2002 MontaVista Software Inc. 18 * Author: Michael Pruznick, michael_pruznick@mvista.com 19 * 20 * Copyright (C) 2000-2001 Toshiba Corporation 21 * 22 * Copyright (C) 2004 MontaVista Software Inc. 23 * Author: Manish Lachwani, mlachwani@mvista.com 24 * 25 * This program is free software; you can redistribute it and/or modify it 26 * under the terms of the GNU General Public License as published by the 27 * Free Software Foundation; either version 2 of the License, or (at your 28 * option) any later version. 29 * 30 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 31 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 32 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 33 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 34 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 35 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 36 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 37 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 38 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE 39 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * You should have received a copy of the GNU General Public License along 42 * with this program; if not, write to the Free Software Foundation, Inc., 43 * 675 Mass Ave, Cambridge, MA 02139, USA. 44 */ 45#include <linux/init.h> 46#include <linux/kernel.h> 47#include <linux/types.h> 48#include <linux/ioport.h> 49#include <linux/platform_device.h> 50#include <linux/delay.h> 51#include <linux/gpio.h> 52#include <linux/leds.h> 53#include <asm/io.h> 54#include <asm/reboot.h> 55#include <asm/txx9/generic.h> 56#include <asm/txx9/pci.h> 57#include <asm/txx9/rbtx4927.h> 58#include <asm/txx9/tx4938.h> /* for TX4937 */ 59 60#ifdef CONFIG_PCI 61static void __init tx4927_pci_setup(void) 62{ 63 int extarb = !(__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCIARB); 64 struct pci_controller *c = &txx9_primary_pcic; 65 66 register_pci_controller(c); 67 68 if (__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCI66) 69 txx9_pci_option = 70 (txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) | 71 TXX9_PCI_OPT_CLK_66; /* already configured */ 72 73 /* Reset PCI Bus */ 74 writeb(1, rbtx4927_pcireset_addr); 75 /* Reset PCIC */ 76 txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST); 77 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) == 78 TXX9_PCI_OPT_CLK_66) 79 tx4927_pciclk66_setup(); 80 mdelay(10); 81 /* clear PCIC reset */ 82 txx9_clear64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST); 83 writeb(0, rbtx4927_pcireset_addr); 84 iob(); 85 86 tx4927_report_pciclk(); 87 tx4927_pcic_setup(tx4927_pcicptr, c, extarb); 88 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) == 89 TXX9_PCI_OPT_CLK_AUTO && 90 txx9_pci66_check(c, 0, 0)) { 91 /* Reset PCI Bus */ 92 writeb(1, rbtx4927_pcireset_addr); 93 /* Reset PCIC */ 94 txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST); 95 tx4927_pciclk66_setup(); 96 mdelay(10); 97 /* clear PCIC reset */ 98 txx9_clear64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST); 99 writeb(0, rbtx4927_pcireset_addr); 100 iob(); 101 /* Reinitialize PCIC */ 102 tx4927_report_pciclk(); 103 tx4927_pcic_setup(tx4927_pcicptr, c, extarb); 104 } 105 tx4927_setup_pcierr_irq(); 106} 107 108static void __init tx4937_pci_setup(void) 109{ 110 int extarb = !(__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB); 111 struct pci_controller *c = &txx9_primary_pcic; 112 113 register_pci_controller(c); 114 115 if (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66) 116 txx9_pci_option = 117 (txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) | 118 TXX9_PCI_OPT_CLK_66; /* already configured */ 119 120 /* Reset PCI Bus */ 121 writeb(1, rbtx4927_pcireset_addr); 122 /* Reset PCIC */ 123 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST); 124 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) == 125 TXX9_PCI_OPT_CLK_66) 126 tx4938_pciclk66_setup(); 127 mdelay(10); 128 /* clear PCIC reset */ 129 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST); 130 writeb(0, rbtx4927_pcireset_addr); 131 iob(); 132 133 tx4938_report_pciclk(); 134 tx4927_pcic_setup(tx4938_pcicptr, c, extarb); 135 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) == 136 TXX9_PCI_OPT_CLK_AUTO && 137 txx9_pci66_check(c, 0, 0)) { 138 /* Reset PCI Bus */ 139 writeb(1, rbtx4927_pcireset_addr); 140 /* Reset PCIC */ 141 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST); 142 tx4938_pciclk66_setup(); 143 mdelay(10); 144 /* clear PCIC reset */ 145 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST); 146 writeb(0, rbtx4927_pcireset_addr); 147 iob(); 148 /* Reinitialize PCIC */ 149 tx4938_report_pciclk(); 150 tx4927_pcic_setup(tx4938_pcicptr, c, extarb); 151 } 152 tx4938_setup_pcierr_irq(); 153} 154 155static void __init rbtx4927_arch_init(void) 156{ 157 tx4927_pci_setup(); 158} 159 160static void __init rbtx4937_arch_init(void) 161{ 162 tx4937_pci_setup(); 163} 164#else 165#define rbtx4927_arch_init NULL 166#define rbtx4937_arch_init NULL 167#endif /* CONFIG_PCI */ 168 169static void toshiba_rbtx4927_restart(char *command) 170{ 171 /* enable the s/w reset register */ 172 writeb(1, rbtx4927_softresetlock_addr); 173 174 /* wait for enable to be seen */ 175 while (!(readb(rbtx4927_softresetlock_addr) & 1)) 176 ; 177 178 /* do a s/w reset */ 179 writeb(1, rbtx4927_softreset_addr); 180 181 /* fallback */ 182 (*_machine_halt)(); 183} 184 185static void __init rbtx4927_clock_init(void); 186static void __init rbtx4937_clock_init(void); 187 188static void __init rbtx4927_mem_setup(void) 189{ 190 if (TX4927_REV_PCODE() == 0x4927) { 191 rbtx4927_clock_init(); 192 tx4927_setup(); 193 } else { 194 rbtx4937_clock_init(); 195 tx4938_setup(); 196 } 197 198 _machine_restart = toshiba_rbtx4927_restart; 199 200#ifdef CONFIG_PCI 201 txx9_alloc_pci_controller(&txx9_primary_pcic, 202 RBTX4927_PCIMEM, RBTX4927_PCIMEM_SIZE, 203 RBTX4927_PCIIO, RBTX4927_PCIIO_SIZE); 204 txx9_board_pcibios_setup = tx4927_pcibios_setup; 205#else 206 set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET); 207#endif 208 209 /* TX4927-SIO DTR on (PIO[15]) */ 210 gpio_request(15, "sio-dtr"); 211 gpio_direction_output(15, 1); 212 213 tx4927_sio_init(0, 0); 214} 215 216static void __init rbtx4927_clock_init(void) 217{ 218 /* 219 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. 220 * 221 * For TX4927: 222 * PCIDIVMODE[12:11]'s initial value is given by S9[4:3] (ON:0, OFF:1). 223 * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5) 224 * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3) 225 * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5) 226 * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6) 227 * i.e. S9[3]: ON (83MHz), OFF (100MHz) 228 */ 229 switch ((unsigned long)__raw_readq(&tx4927_ccfgptr->ccfg) & 230 TX4927_CCFG_PCIDIVMODE_MASK) { 231 case TX4927_CCFG_PCIDIVMODE_2_5: 232 case TX4927_CCFG_PCIDIVMODE_5: 233 txx9_cpu_clock = 166666666; /* 166MHz */ 234 break; 235 default: 236 txx9_cpu_clock = 200000000; /* 200MHz */ 237 } 238} 239 240static void __init rbtx4937_clock_init(void) 241{ 242 /* 243 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. 244 * 245 * For TX4937: 246 * PCIDIVMODE[12:11]'s initial value is given by S1[5:4] (ON:0, OFF:1) 247 * PCIDIVMODE[10] is 0. 248 * CPU 266MHz: PCI 33MHz : PCIDIVMODE: 000 (1/8) 249 * CPU 266MHz: PCI 66MHz : PCIDIVMODE: 001 (1/4) 250 * CPU 300MHz: PCI 33MHz : PCIDIVMODE: 010 (1/9) 251 * CPU 300MHz: PCI 66MHz : PCIDIVMODE: 011 (1/4.5) 252 * CPU 333MHz: PCI 33MHz : PCIDIVMODE: 100 (1/10) 253 * CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5) 254 */ 255 switch ((unsigned long)__raw_readq(&tx4938_ccfgptr->ccfg) & 256 TX4938_CCFG_PCIDIVMODE_MASK) { 257 case TX4938_CCFG_PCIDIVMODE_8: 258 case TX4938_CCFG_PCIDIVMODE_4: 259 txx9_cpu_clock = 266666666; /* 266MHz */ 260 break; 261 case TX4938_CCFG_PCIDIVMODE_9: 262 case TX4938_CCFG_PCIDIVMODE_4_5: 263 txx9_cpu_clock = 300000000; /* 300MHz */ 264 break; 265 default: 266 txx9_cpu_clock = 333333333; /* 333MHz */ 267 } 268} 269 270static void __init rbtx4927_time_init(void) 271{ 272 tx4927_time_init(0); 273} 274 275static void __init toshiba_rbtx4927_rtc_init(void) 276{ 277 struct resource res = { 278 .start = RBTX4927_BRAMRTC_BASE - IO_BASE, 279 .end = RBTX4927_BRAMRTC_BASE - IO_BASE + 0x800 - 1, 280 .flags = IORESOURCE_MEM, 281 }; 282 platform_device_register_simple("rtc-ds1742", -1, &res, 1); 283} 284 285static void __init rbtx4927_ne_init(void) 286{ 287 struct resource res[] = { 288 { 289 .start = RBTX4927_RTL_8019_BASE, 290 .end = RBTX4927_RTL_8019_BASE + 0x20 - 1, 291 .flags = IORESOURCE_IO, 292 }, { 293 .start = RBTX4927_RTL_8019_IRQ, 294 .flags = IORESOURCE_IRQ, 295 } 296 }; 297 platform_device_register_simple("ne", -1, res, ARRAY_SIZE(res)); 298} 299 300static void __init rbtx4927_mtd_init(void) 301{ 302 int i; 303 304 for (i = 0; i < 2; i++) 305 tx4927_mtd_init(i); 306} 307 308static void __init rbtx4927_gpioled_init(void) 309{ 310 static struct gpio_led leds[] = { 311 { .name = "gpioled:green:0", .gpio = 0, .active_low = 1, }, 312 { .name = "gpioled:green:1", .gpio = 1, .active_low = 1, }, 313 }; 314 static struct gpio_led_platform_data pdata = { 315 .num_leds = ARRAY_SIZE(leds), 316 .leds = leds, 317 }; 318 struct platform_device *pdev = platform_device_alloc("leds-gpio", 0); 319 320 if (!pdev) 321 return; 322 pdev->dev.platform_data = &pdata; 323 if (platform_device_add(pdev)) 324 platform_device_put(pdev); 325} 326 327static void __init rbtx4927_device_init(void) 328{ 329 toshiba_rbtx4927_rtc_init(); 330 rbtx4927_ne_init(); 331 tx4927_wdt_init(); 332 rbtx4927_mtd_init(); 333 if (TX4927_REV_PCODE() == 0x4927) { 334 tx4927_dmac_init(2); 335 tx4927_aclc_init(0, 1); 336 } else { 337 tx4938_dmac_init(0, 2); 338 tx4938_aclc_init(); 339 } 340 platform_device_register_simple("txx9aclc-generic", -1, NULL, 0); 341 txx9_iocled_init(RBTX4927_LED_ADDR - IO_BASE, -1, 3, 1, "green", NULL); 342 rbtx4927_gpioled_init(); 343} 344 345struct txx9_board_vec rbtx4927_vec __initdata = { 346 .system = "Toshiba RBTX4927", 347 .prom_init = rbtx4927_prom_init, 348 .mem_setup = rbtx4927_mem_setup, 349 .irq_setup = rbtx4927_irq_setup, 350 .time_init = rbtx4927_time_init, 351 .device_init = rbtx4927_device_init, 352 .arch_init = rbtx4927_arch_init, 353#ifdef CONFIG_PCI 354 .pci_map_irq = rbtx4927_pci_map_irq, 355#endif 356}; 357struct txx9_board_vec rbtx4937_vec __initdata = { 358 .system = "Toshiba RBTX4937", 359 .prom_init = rbtx4927_prom_init, 360 .mem_setup = rbtx4927_mem_setup, 361 .irq_setup = rbtx4927_irq_setup, 362 .time_init = rbtx4927_time_init, 363 .device_init = rbtx4927_device_init, 364 .arch_init = rbtx4937_arch_init, 365#ifdef CONFIG_PCI 366 .pci_map_irq = rbtx4927_pci_map_irq, 367#endif 368}; 369