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  • only in /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/pmc-sierra/yosemite/
1/*
2 *  Copyright (C) 2003 PMC-Sierra Inc.
3 *  Author: Manish Lachwani (lachwani@pmc-sierra.com)
4 *
5 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
6 *
7 *  This program is free software; you can redistribute  it and/or modify it
8 *  under  the terms of  the GNU General  Public License as published by the
9 *  Free Software Foundation;  either version 2 of the  License, or (at your
10 *  option) any later version.
11 *
12 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
13 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
14 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
15 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
16 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
18 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
20 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 *  You should have received a copy of the  GNU General Public License along
24 *  with this program; if not, write  to the Free Software Foundation, Inc.,
25 *  675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27#include <linux/bcd.h>
28#include <linux/init.h>
29#include <linux/kernel.h>
30#include <linux/types.h>
31#include <linux/mm.h>
32#include <linux/bootmem.h>
33#include <linux/swap.h>
34#include <linux/ioport.h>
35#include <linux/sched.h>
36#include <linux/interrupt.h>
37#include <linux/timex.h>
38#include <linux/termios.h>
39#include <linux/tty.h>
40#include <linux/serial.h>
41#include <linux/serial_core.h>
42#include <linux/serial_8250.h>
43
44#include <asm/time.h>
45#include <asm/bootinfo.h>
46#include <asm/page.h>
47#include <asm/io.h>
48#include <asm/irq.h>
49#include <asm/processor.h>
50#include <asm/reboot.h>
51#include <asm/serial.h>
52#include <asm/titan_dep.h>
53#include <asm/m48t37.h>
54
55#include "setup.h"
56
57unsigned char titan_ge_mac_addr_base[6] = {
58	// 0x00, 0x03, 0xcc, 0x1d, 0x22, 0x00
59	0x00, 0xe0, 0x04, 0x00, 0x00, 0x21
60};
61
62unsigned long cpu_clock_freq;
63unsigned long yosemite_base;
64
65static struct m48t37_rtc *m48t37_base;
66
67void __init bus_error_init(void)
68{
69	/* Do nothing */
70}
71
72
73void read_persistent_clock(struct timespec *ts)
74{
75	unsigned int year, month, day, hour, min, sec;
76	unsigned long flags;
77
78	spin_lock_irqsave(&rtc_lock, flags);
79	/* Stop the update to the time */
80	m48t37_base->control = 0x40;
81
82	year = bcd2bin(m48t37_base->year);
83	year += bcd2bin(m48t37_base->century) * 100;
84
85	month = bcd2bin(m48t37_base->month);
86	day = bcd2bin(m48t37_base->date);
87	hour = bcd2bin(m48t37_base->hour);
88	min = bcd2bin(m48t37_base->min);
89	sec = bcd2bin(m48t37_base->sec);
90
91	/* Start the update to the time again */
92	m48t37_base->control = 0x00;
93	spin_unlock_irqrestore(&rtc_lock, flags);
94
95	ts->tv_sec = mktime(year, month, day, hour, min, sec);
96	ts->tv_nsec = 0;
97}
98
99int rtc_mips_set_time(unsigned long tim)
100{
101	struct rtc_time tm;
102	unsigned long flags;
103
104	/*
105	 * Convert to a more useful format -- note months count from 0
106	 * and years from 1900
107	 */
108	rtc_time_to_tm(tim, &tm);
109	tm.tm_year += 1900;
110	tm.tm_mon += 1;
111
112	spin_lock_irqsave(&rtc_lock, flags);
113	/* enable writing */
114	m48t37_base->control = 0x80;
115
116	/* year */
117	m48t37_base->year = bin2bcd(tm.tm_year % 100);
118	m48t37_base->century = bin2bcd(tm.tm_year / 100);
119
120	/* month */
121	m48t37_base->month = bin2bcd(tm.tm_mon);
122
123	/* day */
124	m48t37_base->date = bin2bcd(tm.tm_mday);
125
126	/* hour/min/sec */
127	m48t37_base->hour = bin2bcd(tm.tm_hour);
128	m48t37_base->min = bin2bcd(tm.tm_min);
129	m48t37_base->sec = bin2bcd(tm.tm_sec);
130
131	/* day of week -- not really used, but let's keep it up-to-date */
132	m48t37_base->day = bin2bcd(tm.tm_wday + 1);
133
134	/* disable writing */
135	m48t37_base->control = 0x00;
136	spin_unlock_irqrestore(&rtc_lock, flags);
137
138	return 0;
139}
140
141void __init plat_time_init(void)
142{
143	mips_hpt_frequency = cpu_clock_freq / 2;
144mips_hpt_frequency = 33000000 * 3 * 5;
145}
146
147unsigned long ocd_base;
148
149EXPORT_SYMBOL(ocd_base);
150
151/*
152 * Common setup before any secondaries are started
153 */
154
155#define TITAN_UART_CLK		3686400
156#define TITAN_SERIAL_BASE_BAUD	(TITAN_UART_CLK / 16)
157#define TITAN_SERIAL_IRQ	4
158#define TITAN_SERIAL_BASE	0xfd000008UL
159
160static void __init py_map_ocd(void)
161{
162	ocd_base = (unsigned long) ioremap(OCD_BASE, OCD_SIZE);
163	if (!ocd_base)
164		panic("Mapping OCD failed - game over.  Your score is 0.");
165
166	/* Kludge for PMON bug ... */
167	OCD_WRITE(0x0710, 0x0ffff029);
168}
169
170static void __init py_uart_setup(void)
171{
172#ifdef CONFIG_SERIAL_8250
173	struct uart_port up;
174
175	/*
176	 * Register to interrupt zero because we share the interrupt with
177	 * the serial driver which we don't properly support yet.
178	 */
179	memset(&up, 0, sizeof(up));
180	up.membase      = (unsigned char *) ioremap(TITAN_SERIAL_BASE, 8);
181	up.irq          = TITAN_SERIAL_IRQ;
182	up.uartclk      = TITAN_UART_CLK;
183	up.regshift     = 0;
184	up.iotype       = UPIO_MEM;
185	up.flags        = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
186	up.line         = 0;
187
188	if (early_serial_setup(&up))
189		printk(KERN_ERR "Early serial init of port 0 failed\n");
190#endif /* CONFIG_SERIAL_8250 */
191}
192
193static void __init py_rtc_setup(void)
194{
195	m48t37_base = ioremap(YOSEMITE_RTC_BASE, YOSEMITE_RTC_SIZE);
196	if (!m48t37_base)
197		printk(KERN_ERR "Mapping the RTC failed\n");
198}
199
200/* Not only time init but that's what the hook it's called through is named */
201static void __init py_late_time_init(void)
202{
203	py_map_ocd();
204	py_uart_setup();
205	py_rtc_setup();
206}
207
208void __init plat_mem_setup(void)
209{
210	late_time_init = py_late_time_init;
211
212	/* Add memory regions */
213	add_memory_region(0x00000000, 0x10000000, BOOT_MEM_RAM);
214
215}
216