1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2005-2009 Cavium Networks 7 */ 8#include <linux/kernel.h> 9#include <linux/init.h> 10#include <linux/pci.h> 11#include <linux/interrupt.h> 12#include <linux/time.h> 13#include <linux/delay.h> 14 15#include <asm/time.h> 16 17#include <asm/octeon/octeon.h> 18#include <asm/octeon/cvmx-npi-defs.h> 19#include <asm/octeon/cvmx-pci-defs.h> 20#include <asm/octeon/pci-octeon.h> 21 22#define USE_OCTEON_INTERNAL_ARBITER 23 24/* 25 * Octeon's PCI controller uses did=3, subdid=2 for PCI IO 26 * addresses. Use PCI endian swapping 1 so no address swapping is 27 * necessary. The Linux io routines will endian swap the data. 28 */ 29#define OCTEON_PCI_IOSPACE_BASE 0x80011a0400000000ull 30#define OCTEON_PCI_IOSPACE_SIZE (1ull<<32) 31 32/* Octeon't PCI controller uses did=3, subdid=3 for PCI memory. */ 33#define OCTEON_PCI_MEMSPACE_OFFSET (0x00011b0000000000ull) 34 35/** 36 * This is the bit decoding used for the Octeon PCI controller addresses 37 */ 38union octeon_pci_address { 39 uint64_t u64; 40 struct { 41 uint64_t upper:2; 42 uint64_t reserved:13; 43 uint64_t io:1; 44 uint64_t did:5; 45 uint64_t subdid:3; 46 uint64_t reserved2:4; 47 uint64_t endian_swap:2; 48 uint64_t reserved3:10; 49 uint64_t bus:8; 50 uint64_t dev:5; 51 uint64_t func:3; 52 uint64_t reg:8; 53 } s; 54}; 55 56int __initdata (*octeon_pcibios_map_irq)(const struct pci_dev *dev, 57 u8 slot, u8 pin); 58enum octeon_dma_bar_type octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_INVALID; 59 60/** 61 * Map a PCI device to the appropriate interrupt line 62 * 63 * @dev: The Linux PCI device structure for the device to map 64 * @slot: The slot number for this device on __BUS 0__. Linux 65 * enumerates through all the bridges and figures out the 66 * slot on Bus 0 where this device eventually hooks to. 67 * @pin: The PCI interrupt pin read from the device, then swizzled 68 * as it goes through each bridge. 69 * Returns Interrupt number for the device 70 */ 71int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 72{ 73 if (octeon_pcibios_map_irq) 74 return octeon_pcibios_map_irq(dev, slot, pin); 75 else 76 panic("octeon_pcibios_map_irq not set."); 77} 78 79 80/* 81 * Called to perform platform specific PCI setup 82 */ 83int pcibios_plat_dev_init(struct pci_dev *dev) 84{ 85 uint16_t config; 86 uint32_t dconfig; 87 int pos; 88 /* 89 * Force the Cache line setting to 64 bytes. The standard 90 * Linux bus scan doesn't seem to set it. Octeon really has 91 * 128 byte lines, but Intel bridges get really upset if you 92 * try and set values above 64 bytes. Value is specified in 93 * 32bit words. 94 */ 95 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 64 / 4); 96 /* Set latency timers for all devices */ 97 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 48); 98 99 /* Enable reporting System errors and parity errors on all devices */ 100 /* Enable parity checking and error reporting */ 101 pci_read_config_word(dev, PCI_COMMAND, &config); 102 config |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR; 103 pci_write_config_word(dev, PCI_COMMAND, config); 104 105 if (dev->subordinate) { 106 /* Set latency timers on sub bridges */ 107 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 48); 108 /* More bridge error detection */ 109 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config); 110 config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR; 111 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config); 112 } 113 114 /* Enable the PCIe normal error reporting */ 115 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 116 if (pos) { 117 /* Update Device Control */ 118 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config); 119 /* Correctable Error Reporting */ 120 config |= PCI_EXP_DEVCTL_CERE; 121 /* Non-Fatal Error Reporting */ 122 config |= PCI_EXP_DEVCTL_NFERE; 123 /* Fatal Error Reporting */ 124 config |= PCI_EXP_DEVCTL_FERE; 125 /* Unsupported Request */ 126 config |= PCI_EXP_DEVCTL_URRE; 127 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config); 128 } 129 130 /* Find the Advanced Error Reporting capability */ 131 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); 132 if (pos) { 133 /* Clear Uncorrectable Error Status */ 134 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, 135 &dconfig); 136 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, 137 dconfig); 138 /* Enable reporting of all uncorrectable errors */ 139 /* Uncorrectable Error Mask - turned on bits disable errors */ 140 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0); 141 /* 142 * Leave severity at HW default. This only controls if 143 * errors are reported as uncorrectable or 144 * correctable, not if the error is reported. 145 */ 146 /* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */ 147 /* Clear Correctable Error Status */ 148 pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &dconfig); 149 pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, dconfig); 150 /* Enable reporting of all correctable errors */ 151 /* Correctable Error Mask - turned on bits disable errors */ 152 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0); 153 /* Advanced Error Capabilities */ 154 pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig); 155 /* ECRC Generation Enable */ 156 if (config & PCI_ERR_CAP_ECRC_GENC) 157 config |= PCI_ERR_CAP_ECRC_GENE; 158 /* ECRC Check Enable */ 159 if (config & PCI_ERR_CAP_ECRC_CHKC) 160 config |= PCI_ERR_CAP_ECRC_CHKE; 161 pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig); 162 /* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */ 163 /* Report all errors to the root complex */ 164 pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, 165 PCI_ERR_ROOT_CMD_COR_EN | 166 PCI_ERR_ROOT_CMD_NONFATAL_EN | 167 PCI_ERR_ROOT_CMD_FATAL_EN); 168 /* Clear the Root status register */ 169 pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &dconfig); 170 pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig); 171 } 172 173 return 0; 174} 175 176/** 177 * Return the mapping of PCI device number to IRQ line. Each 178 * character in the return string represents the interrupt 179 * line for the device at that position. Device 1 maps to the 180 * first character, etc. The characters A-D are used for PCI 181 * interrupts. 182 * 183 * Returns PCI interrupt mapping 184 */ 185const char *octeon_get_pci_interrupts(void) 186{ 187 /* 188 * Returning an empty string causes the interrupts to be 189 * routed based on the PCI specification. From the PCI spec: 190 * 191 * INTA# of Device Number 0 is connected to IRQW on the system 192 * board. (Device Number has no significance regarding being 193 * located on the system board or in a connector.) INTA# of 194 * Device Number 1 is connected to IRQX on the system 195 * board. INTA# of Device Number 2 is connected to IRQY on the 196 * system board. INTA# of Device Number 3 is connected to IRQZ 197 * on the system board. The table below describes how each 198 * agent's INTx# lines are connected to the system board 199 * interrupt lines. The following equation can be used to 200 * determine to which INTx# signal on the system board a given 201 * device's INTx# line(s) is connected. 202 * 203 * MB = (D + I) MOD 4 MB = System board Interrupt (IRQW = 0, 204 * IRQX = 1, IRQY = 2, and IRQZ = 3) D = Device Number I = 205 * Interrupt Number (INTA# = 0, INTB# = 1, INTC# = 2, and 206 * INTD# = 3) 207 */ 208 switch (octeon_bootinfo->board_type) { 209 case CVMX_BOARD_TYPE_NAO38: 210 /* This is really the NAC38 */ 211 return "AAAAADABAAAAAAAAAAAAAAAAAAAAAAAA"; 212 case CVMX_BOARD_TYPE_EBH3100: 213 case CVMX_BOARD_TYPE_CN3010_EVB_HS5: 214 case CVMX_BOARD_TYPE_CN3005_EVB_HS5: 215 return "AAABAAAAAAAAAAAAAAAAAAAAAAAAAAAA"; 216 case CVMX_BOARD_TYPE_BBGW_REF: 217 return "AABCD"; 218 case CVMX_BOARD_TYPE_THUNDER: 219 case CVMX_BOARD_TYPE_EBH3000: 220 default: 221 return ""; 222 } 223} 224 225/** 226 * Map a PCI device to the appropriate interrupt line 227 * 228 * @dev: The Linux PCI device structure for the device to map 229 * @slot: The slot number for this device on __BUS 0__. Linux 230 * enumerates through all the bridges and figures out the 231 * slot on Bus 0 where this device eventually hooks to. 232 * @pin: The PCI interrupt pin read from the device, then swizzled 233 * as it goes through each bridge. 234 * Returns Interrupt number for the device 235 */ 236int __init octeon_pci_pcibios_map_irq(const struct pci_dev *dev, 237 u8 slot, u8 pin) 238{ 239 int irq_num; 240 const char *interrupts; 241 int dev_num; 242 243 /* Get the board specific interrupt mapping */ 244 interrupts = octeon_get_pci_interrupts(); 245 246 dev_num = dev->devfn >> 3; 247 if (dev_num < strlen(interrupts)) 248 irq_num = ((interrupts[dev_num] - 'A' + pin - 1) & 3) + 249 OCTEON_IRQ_PCI_INT0; 250 else 251 irq_num = ((slot + pin - 3) & 3) + OCTEON_IRQ_PCI_INT0; 252 return irq_num; 253} 254 255 256/* 257 * Read a value from configuration space 258 */ 259static int octeon_read_config(struct pci_bus *bus, unsigned int devfn, 260 int reg, int size, u32 *val) 261{ 262 union octeon_pci_address pci_addr; 263 264 pci_addr.u64 = 0; 265 pci_addr.s.upper = 2; 266 pci_addr.s.io = 1; 267 pci_addr.s.did = 3; 268 pci_addr.s.subdid = 1; 269 pci_addr.s.endian_swap = 1; 270 pci_addr.s.bus = bus->number; 271 pci_addr.s.dev = devfn >> 3; 272 pci_addr.s.func = devfn & 0x7; 273 pci_addr.s.reg = reg; 274 275#if PCI_CONFIG_SPACE_DELAY 276 udelay(PCI_CONFIG_SPACE_DELAY); 277#endif 278 switch (size) { 279 case 4: 280 *val = le32_to_cpu(cvmx_read64_uint32(pci_addr.u64)); 281 return PCIBIOS_SUCCESSFUL; 282 case 2: 283 *val = le16_to_cpu(cvmx_read64_uint16(pci_addr.u64)); 284 return PCIBIOS_SUCCESSFUL; 285 case 1: 286 *val = cvmx_read64_uint8(pci_addr.u64); 287 return PCIBIOS_SUCCESSFUL; 288 } 289 return PCIBIOS_FUNC_NOT_SUPPORTED; 290} 291 292 293/* 294 * Write a value to PCI configuration space 295 */ 296static int octeon_write_config(struct pci_bus *bus, unsigned int devfn, 297 int reg, int size, u32 val) 298{ 299 union octeon_pci_address pci_addr; 300 301 pci_addr.u64 = 0; 302 pci_addr.s.upper = 2; 303 pci_addr.s.io = 1; 304 pci_addr.s.did = 3; 305 pci_addr.s.subdid = 1; 306 pci_addr.s.endian_swap = 1; 307 pci_addr.s.bus = bus->number; 308 pci_addr.s.dev = devfn >> 3; 309 pci_addr.s.func = devfn & 0x7; 310 pci_addr.s.reg = reg; 311 312#if PCI_CONFIG_SPACE_DELAY 313 udelay(PCI_CONFIG_SPACE_DELAY); 314#endif 315 switch (size) { 316 case 4: 317 cvmx_write64_uint32(pci_addr.u64, cpu_to_le32(val)); 318 return PCIBIOS_SUCCESSFUL; 319 case 2: 320 cvmx_write64_uint16(pci_addr.u64, cpu_to_le16(val)); 321 return PCIBIOS_SUCCESSFUL; 322 case 1: 323 cvmx_write64_uint8(pci_addr.u64, val); 324 return PCIBIOS_SUCCESSFUL; 325 } 326 return PCIBIOS_FUNC_NOT_SUPPORTED; 327} 328 329 330static struct pci_ops octeon_pci_ops = { 331 octeon_read_config, 332 octeon_write_config, 333}; 334 335static struct resource octeon_pci_mem_resource = { 336 .start = 0, 337 .end = 0, 338 .name = "Octeon PCI MEM", 339 .flags = IORESOURCE_MEM, 340}; 341 342/* 343 * PCI ports must be above 16KB so the ISA bus filtering in the PCI-X to PCI 344 * bridge 345 */ 346static struct resource octeon_pci_io_resource = { 347 .start = 0x4000, 348 .end = OCTEON_PCI_IOSPACE_SIZE - 1, 349 .name = "Octeon PCI IO", 350 .flags = IORESOURCE_IO, 351}; 352 353static struct pci_controller octeon_pci_controller = { 354 .pci_ops = &octeon_pci_ops, 355 .mem_resource = &octeon_pci_mem_resource, 356 .mem_offset = OCTEON_PCI_MEMSPACE_OFFSET, 357 .io_resource = &octeon_pci_io_resource, 358 .io_offset = 0, 359 .io_map_base = OCTEON_PCI_IOSPACE_BASE, 360}; 361 362 363/* 364 * Low level initialize the Octeon PCI controller 365 */ 366static void octeon_pci_initialize(void) 367{ 368 union cvmx_pci_cfg01 cfg01; 369 union cvmx_npi_ctl_status ctl_status; 370 union cvmx_pci_ctl_status_2 ctl_status_2; 371 union cvmx_pci_cfg19 cfg19; 372 union cvmx_pci_cfg16 cfg16; 373 union cvmx_pci_cfg22 cfg22; 374 union cvmx_pci_cfg56 cfg56; 375 376 /* Reset the PCI Bus */ 377 cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x1); 378 cvmx_read_csr(CVMX_CIU_SOFT_PRST); 379 380 udelay(2000); /* Hold PCI reset for 2 ms */ 381 382 ctl_status.u64 = 0; /* cvmx_read_csr(CVMX_NPI_CTL_STATUS); */ 383 ctl_status.s.max_word = 1; 384 ctl_status.s.timer = 1; 385 cvmx_write_csr(CVMX_NPI_CTL_STATUS, ctl_status.u64); 386 387 /* Deassert PCI reset and advertize PCX Host Mode Device Capability 388 (64b) */ 389 cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x4); 390 cvmx_read_csr(CVMX_CIU_SOFT_PRST); 391 392 udelay(2000); /* Wait 2 ms after deasserting PCI reset */ 393 394 ctl_status_2.u32 = 0; 395 ctl_status_2.s.tsr_hwm = 1; /* Initializes to 0. Must be set 396 before any PCI reads. */ 397 ctl_status_2.s.bar2pres = 1; /* Enable BAR2 */ 398 ctl_status_2.s.bar2_enb = 1; 399 ctl_status_2.s.bar2_cax = 1; /* Don't use L2 */ 400 ctl_status_2.s.bar2_esx = 1; 401 ctl_status_2.s.pmo_amod = 1; /* Round robin priority */ 402 if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) { 403 /* BAR1 hole */ 404 ctl_status_2.s.bb1_hole = OCTEON_PCI_BAR1_HOLE_BITS; 405 ctl_status_2.s.bb1_siz = 1; /* BAR1 is 2GB */ 406 ctl_status_2.s.bb_ca = 1; /* Don't use L2 with big bars */ 407 ctl_status_2.s.bb_es = 1; /* Big bar in byte swap mode */ 408 ctl_status_2.s.bb1 = 1; /* BAR1 is big */ 409 ctl_status_2.s.bb0 = 1; /* BAR0 is big */ 410 } 411 412 octeon_npi_write32(CVMX_NPI_PCI_CTL_STATUS_2, ctl_status_2.u32); 413 udelay(2000); /* Wait 2 ms before doing PCI reads */ 414 415 ctl_status_2.u32 = octeon_npi_read32(CVMX_NPI_PCI_CTL_STATUS_2); 416 pr_notice("PCI Status: %s %s-bit\n", 417 ctl_status_2.s.ap_pcix ? "PCI-X" : "PCI", 418 ctl_status_2.s.ap_64ad ? "64" : "32"); 419 420 if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)) { 421 union cvmx_pci_cnt_reg cnt_reg_start; 422 union cvmx_pci_cnt_reg cnt_reg_end; 423 unsigned long cycles, pci_clock; 424 425 cnt_reg_start.u64 = cvmx_read_csr(CVMX_NPI_PCI_CNT_REG); 426 cycles = read_c0_cvmcount(); 427 udelay(1000); 428 cnt_reg_end.u64 = cvmx_read_csr(CVMX_NPI_PCI_CNT_REG); 429 cycles = read_c0_cvmcount() - cycles; 430 pci_clock = (cnt_reg_end.s.pcicnt - cnt_reg_start.s.pcicnt) / 431 (cycles / (mips_hpt_frequency / 1000000)); 432 pr_notice("PCI Clock: %lu MHz\n", pci_clock); 433 } 434 435 /* 436 * TDOMC must be set to one in PCI mode. TDOMC should be set to 4 437 * in PCI-X mode to allow four oustanding splits. Otherwise, 438 * should not change from its reset value. Don't write PCI_CFG19 439 * in PCI mode (0x82000001 reset value), write it to 0x82000004 440 * after PCI-X mode is known. MRBCI,MDWE,MDRE -> must be zero. 441 * MRBCM -> must be one. 442 */ 443 if (ctl_status_2.s.ap_pcix) { 444 cfg19.u32 = 0; 445 /* 446 * Target Delayed/Split request outstanding maximum 447 * count. [1..31] and 0=32. NOTE: If the user 448 * programs these bits beyond the Designed Maximum 449 * outstanding count, then the designed maximum table 450 * depth will be used instead. No additional 451 * Deferred/Split transactions will be accepted if 452 * this outstanding maximum count is 453 * reached. Furthermore, no additional deferred/split 454 * transactions will be accepted if the I/O delay/ I/O 455 * Split Request outstanding maximum is reached. 456 */ 457 cfg19.s.tdomc = 4; 458 /* 459 * Master Deferred Read Request Outstanding Max Count 460 * (PCI only). CR4C[26:24] Max SAC cycles MAX DAC 461 * cycles 000 8 4 001 1 0 010 2 1 011 3 1 100 4 2 101 462 * 5 2 110 6 3 111 7 3 For example, if these bits are 463 * programmed to 100, the core can support 2 DAC 464 * cycles, 4 SAC cycles or a combination of 1 DAC and 465 * 2 SAC cycles. NOTE: For the PCI-X maximum 466 * outstanding split transactions, refer to 467 * CRE0[22:20]. 468 */ 469 cfg19.s.mdrrmc = 2; 470 /* 471 * Master Request (Memory Read) Byte Count/Byte Enable 472 * select. 0 = Byte Enables valid. In PCI mode, a 473 * burst transaction cannot be performed using Memory 474 * Read command=4?h6. 1 = DWORD Byte Count valid 475 * (default). In PCI Mode, the memory read byte 476 * enables are automatically generated by the 477 * core. Note: N3 Master Request transaction sizes are 478 * always determined through the 479 * am_attr[<35:32>|<7:0>] field. 480 */ 481 cfg19.s.mrbcm = 1; 482 octeon_npi_write32(CVMX_NPI_PCI_CFG19, cfg19.u32); 483 } 484 485 486 cfg01.u32 = 0; 487 cfg01.s.msae = 1; /* Memory Space Access Enable */ 488 cfg01.s.me = 1; /* Master Enable */ 489 cfg01.s.pee = 1; /* PERR# Enable */ 490 cfg01.s.see = 1; /* System Error Enable */ 491 cfg01.s.fbbe = 1; /* Fast Back to Back Transaction Enable */ 492 493 octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32); 494 495#ifdef USE_OCTEON_INTERNAL_ARBITER 496 /* 497 * When OCTEON is a PCI host, most systems will use OCTEON's 498 * internal arbiter, so must enable it before any PCI/PCI-X 499 * traffic can occur. 500 */ 501 { 502 union cvmx_npi_pci_int_arb_cfg pci_int_arb_cfg; 503 504 pci_int_arb_cfg.u64 = 0; 505 pci_int_arb_cfg.s.en = 1; /* Internal arbiter enable */ 506 cvmx_write_csr(CVMX_NPI_PCI_INT_ARB_CFG, pci_int_arb_cfg.u64); 507 } 508#endif /* USE_OCTEON_INTERNAL_ARBITER */ 509 510 /* 511 * Preferrably written to 1 to set MLTD. [RDSATI,TRTAE, 512 * TWTAE,TMAE,DPPMR -> must be zero. TILT -> must not be set to 513 * 1..7. 514 */ 515 cfg16.u32 = 0; 516 cfg16.s.mltd = 1; /* Master Latency Timer Disable */ 517 octeon_npi_write32(CVMX_NPI_PCI_CFG16, cfg16.u32); 518 519 /* 520 * Should be written to 0x4ff00. MTTV -> must be zero. 521 * FLUSH -> must be 1. MRV -> should be 0xFF. 522 */ 523 cfg22.u32 = 0; 524 /* Master Retry Value [1..255] and 0=infinite */ 525 cfg22.s.mrv = 0xff; 526 /* 527 * AM_DO_FLUSH_I control NOTE: This bit MUST BE ONE for proper 528 * N3K operation. 529 */ 530 cfg22.s.flush = 1; 531 octeon_npi_write32(CVMX_NPI_PCI_CFG22, cfg22.u32); 532 533 /* 534 * MOST Indicates the maximum number of outstanding splits (in -1 535 * notation) when OCTEON is in PCI-X mode. PCI-X performance is 536 * affected by the MOST selection. Should generally be written 537 * with one of 0x3be807, 0x2be807, 0x1be807, or 0x0be807, 538 * depending on the desired MOST of 3, 2, 1, or 0, respectively. 539 */ 540 cfg56.u32 = 0; 541 cfg56.s.pxcid = 7; /* RO - PCI-X Capability ID */ 542 cfg56.s.ncp = 0xe8; /* RO - Next Capability Pointer */ 543 cfg56.s.dpere = 1; /* Data Parity Error Recovery Enable */ 544 cfg56.s.roe = 1; /* Relaxed Ordering Enable */ 545 cfg56.s.mmbc = 1; /* Maximum Memory Byte Count 546 [0=512B,1=1024B,2=2048B,3=4096B] */ 547 cfg56.s.most = 3; /* Maximum outstanding Split transactions [0=1 548 .. 7=32] */ 549 550 octeon_npi_write32(CVMX_NPI_PCI_CFG56, cfg56.u32); 551 552 /* 553 * Affects PCI performance when OCTEON services reads to its 554 * BAR1/BAR2. Refer to Section 10.6.1. The recommended values are 555 * 0x22, 0x33, and 0x33 for PCI_READ_CMD_6, PCI_READ_CMD_C, and 556 * PCI_READ_CMD_E, respectively. Unfortunately due to errata DDR-700, 557 * these values need to be changed so they won't possibly prefetch off 558 * of the end of memory if PCI is DMAing a buffer at the end of 559 * memory. Note that these values differ from their reset values. 560 */ 561 octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_6, 0x21); 562 octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_C, 0x31); 563 octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_E, 0x31); 564} 565 566 567/* 568 * Initialize the Octeon PCI controller 569 */ 570static int __init octeon_pci_setup(void) 571{ 572 union cvmx_npi_mem_access_subidx mem_access; 573 int index; 574 575 /* Only these chips have PCI */ 576 if (octeon_has_feature(OCTEON_FEATURE_PCIE)) 577 return 0; 578 579 /* Point pcibios_map_irq() to the PCI version of it */ 580 octeon_pcibios_map_irq = octeon_pci_pcibios_map_irq; 581 582 /* Only use the big bars on chips that support it */ 583 if (OCTEON_IS_MODEL(OCTEON_CN31XX) || 584 OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) || 585 OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1)) 586 octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_SMALL; 587 else 588 octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_BIG; 589 590 /* PCI I/O and PCI MEM values */ 591 set_io_port_base(OCTEON_PCI_IOSPACE_BASE); 592 ioport_resource.start = 0; 593 ioport_resource.end = OCTEON_PCI_IOSPACE_SIZE - 1; 594 if (!octeon_is_pci_host()) { 595 pr_notice("Not in host mode, PCI Controller not initialized\n"); 596 return 0; 597 } 598 599 pr_notice("%s Octeon big bar support\n", 600 (octeon_dma_bar_type == 601 OCTEON_DMA_BAR_TYPE_BIG) ? "Enabling" : "Disabling"); 602 603 octeon_pci_initialize(); 604 605 mem_access.u64 = 0; 606 mem_access.s.esr = 1; /* Endian-Swap on read. */ 607 mem_access.s.esw = 1; /* Endian-Swap on write. */ 608 mem_access.s.nsr = 0; /* No-Snoop on read. */ 609 mem_access.s.nsw = 0; /* No-Snoop on write. */ 610 mem_access.s.ror = 0; /* Relax Read on read. */ 611 mem_access.s.row = 0; /* Relax Order on write. */ 612 mem_access.s.ba = 0; /* PCI Address bits [63:36]. */ 613 cvmx_write_csr(CVMX_NPI_MEM_ACCESS_SUBID3, mem_access.u64); 614 615 /* 616 * Remap the Octeon BAR 2 above all 32 bit devices 617 * (0x8000000000ul). This is done here so it is remapped 618 * before the readl()'s below. We don't want BAR2 overlapping 619 * with BAR0/BAR1 during these reads. 620 */ 621 octeon_npi_write32(CVMX_NPI_PCI_CFG08, 0); 622 octeon_npi_write32(CVMX_NPI_PCI_CFG09, 0x80); 623 624 /* Disable the BAR1 movable mappings */ 625 for (index = 0; index < 32; index++) 626 octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index), 0); 627 628 if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) { 629 /* Remap the Octeon BAR 0 to 0-2GB */ 630 octeon_npi_write32(CVMX_NPI_PCI_CFG04, 0); 631 octeon_npi_write32(CVMX_NPI_PCI_CFG05, 0); 632 633 /* 634 * Remap the Octeon BAR 1 to map 2GB-4GB (minus the 635 * BAR 1 hole). 636 */ 637 octeon_npi_write32(CVMX_NPI_PCI_CFG06, 2ul << 30); 638 octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0); 639 640 /* Devices go after BAR1 */ 641 octeon_pci_mem_resource.start = 642 OCTEON_PCI_MEMSPACE_OFFSET + (4ul << 30) - 643 (OCTEON_PCI_BAR1_HOLE_SIZE << 20); 644 octeon_pci_mem_resource.end = 645 octeon_pci_mem_resource.start + (1ul << 30); 646 } else { 647 /* Remap the Octeon BAR 0 to map 128MB-(128MB+4KB) */ 648 octeon_npi_write32(CVMX_NPI_PCI_CFG04, 128ul << 20); 649 octeon_npi_write32(CVMX_NPI_PCI_CFG05, 0); 650 651 /* Remap the Octeon BAR 1 to map 0-128MB */ 652 octeon_npi_write32(CVMX_NPI_PCI_CFG06, 0); 653 octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0); 654 655 /* Devices go after BAR0 */ 656 octeon_pci_mem_resource.start = 657 OCTEON_PCI_MEMSPACE_OFFSET + (128ul << 20) + 658 (4ul << 10); 659 octeon_pci_mem_resource.end = 660 octeon_pci_mem_resource.start + (1ul << 30); 661 } 662 663 register_pci_controller(&octeon_pci_controller); 664 665 /* 666 * Clear any errors that might be pending from before the bus 667 * was setup properly. 668 */ 669 cvmx_write_csr(CVMX_NPI_PCI_INT_SUM2, -1); 670 return 0; 671} 672 673arch_initcall(octeon_pci_setup); 674