1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * A small micro-assembler. It is intentionally kept simple, does only 7 * support a subset of instructions, and does not try to hide pipeline 8 * effects like branch delay slots. 9 * 10 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer 11 * Copyright (C) 2005, 2007 Maciej W. Rozycki 12 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) 13 */ 14 15#include <linux/kernel.h> 16#include <linux/types.h> 17#include <linux/init.h> 18 19#include <asm/inst.h> 20#include <asm/elf.h> 21#include <asm/bugs.h> 22#include <asm/uasm.h> 23 24enum fields { 25 RS = 0x001, 26 RT = 0x002, 27 RD = 0x004, 28 RE = 0x008, 29 SIMM = 0x010, 30 UIMM = 0x020, 31 BIMM = 0x040, 32 JIMM = 0x080, 33 FUNC = 0x100, 34 SET = 0x200, 35 SCIMM = 0x400 36}; 37 38#define OP_MASK 0x3f 39#define OP_SH 26 40#define RS_MASK 0x1f 41#define RS_SH 21 42#define RT_MASK 0x1f 43#define RT_SH 16 44#define RD_MASK 0x1f 45#define RD_SH 11 46#define RE_MASK 0x1f 47#define RE_SH 6 48#define IMM_MASK 0xffff 49#define IMM_SH 0 50#define JIMM_MASK 0x3ffffff 51#define JIMM_SH 0 52#define FUNC_MASK 0x3f 53#define FUNC_SH 0 54#define SET_MASK 0x7 55#define SET_SH 0 56#define SCIMM_MASK 0xfffff 57#define SCIMM_SH 6 58 59enum opcode { 60 insn_invalid, 61 insn_addu, insn_addiu, insn_and, insn_andi, insn_beq, 62 insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl, 63 insn_bne, insn_cache, insn_daddu, insn_daddiu, insn_dmfc0, 64 insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl, 65 insn_dsrl32, insn_drotr, insn_drotr32, insn_dsubu, insn_eret, 66 insn_iret, insn_ins, insn_ext, 67 insn_j, insn_jal, insn_jr, insn_ld, insn_ll, insn_lld, 68 insn_lui, insn_lw, insn_mfc0, insn_mtc0, insn_or, insn_ori, 69 insn_pref, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll, 70 insn_sra, insn_srl, insn_rotr, insn_subu, insn_sw, insn_tlbp, 71 insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori, 72 insn_dins, insn_dinsm, insn_syscall, insn_bbit0, insn_bbit1, 73 insn_lwx, insn_ldx 74}; 75 76struct insn { 77 enum opcode opcode; 78 u32 match; 79 enum fields fields; 80}; 81 82/* This macro sets the non-variable bits of an instruction. */ 83#define M(a, b, c, d, e, f) \ 84 ((a) << OP_SH \ 85 | (b) << RS_SH \ 86 | (c) << RT_SH \ 87 | (d) << RD_SH \ 88 | (e) << RE_SH \ 89 | (f) << FUNC_SH) 90 91static struct insn insn_table[] __uasminitdata = { 92 { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 93 { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD }, 94 { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD }, 95 { insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, 96 { insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, 97 { insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, 98 { insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM }, 99 { insn_bgezl, M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM }, 100 { insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM }, 101 { insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM }, 102 { insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, 103 { insn_cache, M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 104 { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 105 { insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD }, 106 { insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET}, 107 { insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET}, 108 { insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE }, 109 { insn_dsll32, M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE }, 110 { insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE }, 111 { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE }, 112 { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE }, 113 { insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE }, 114 { insn_drotr32, M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE }, 115 { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD }, 116 { insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 }, 117 { insn_iret, M(cop0_op, cop_op, 0, 0, 0, iret_op), 0 }, 118 { insn_ins, M(spec3_op, 0, 0, 0, 0, ins_op), RS | RT | RD | RE }, 119 { insn_ext, M(spec3_op, 0, 0, 0, 0, ext_op), RS | RT | RD | RE }, 120 { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM }, 121 { insn_jal, M(jal_op, 0, 0, 0, 0, 0), JIMM }, 122 { insn_jr, M(spec_op, 0, 0, 0, 0, jr_op), RS }, 123 { insn_ld, M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 124 { insn_ll, M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 125 { insn_lld, M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 126 { insn_lui, M(lui_op, 0, 0, 0, 0, 0), RT | SIMM }, 127 { insn_lw, M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 128 { insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET}, 129 { insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET}, 130 { insn_or, M(spec_op, 0, 0, 0, 0, or_op), RS | RT | RD }, 131 { insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, 132 { insn_pref, M(pref_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 133 { insn_rfe, M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0 }, 134 { insn_sc, M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 135 { insn_scd, M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 136 { insn_sd, M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 137 { insn_sll, M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE }, 138 { insn_sra, M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE }, 139 { insn_srl, M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE }, 140 { insn_rotr, M(spec_op, 1, 0, 0, 0, srl_op), RT | RD | RE }, 141 { insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD }, 142 { insn_sw, M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 143 { insn_tlbp, M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0 }, 144 { insn_tlbr, M(cop0_op, cop_op, 0, 0, 0, tlbr_op), 0 }, 145 { insn_tlbwi, M(cop0_op, cop_op, 0, 0, 0, tlbwi_op), 0 }, 146 { insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 }, 147 { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD }, 148 { insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, 149 { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE }, 150 { insn_dinsm, M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE }, 151 { insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM}, 152 { insn_bbit0, M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, 153 { insn_bbit1, M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, 154 { insn_lwx, M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD }, 155 { insn_ldx, M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD }, 156 { insn_invalid, 0, 0 } 157}; 158 159#undef M 160 161static inline __uasminit u32 build_rs(u32 arg) 162{ 163 WARN(arg & ~RS_MASK, KERN_WARNING "Micro-assembler field overflow\n"); 164 165 return (arg & RS_MASK) << RS_SH; 166} 167 168static inline __uasminit u32 build_rt(u32 arg) 169{ 170 WARN(arg & ~RT_MASK, KERN_WARNING "Micro-assembler field overflow\n"); 171 172 return (arg & RT_MASK) << RT_SH; 173} 174 175static inline __uasminit u32 build_rd(u32 arg) 176{ 177 WARN(arg & ~RD_MASK, KERN_WARNING "Micro-assembler field overflow\n"); 178 179 return (arg & RD_MASK) << RD_SH; 180} 181 182static inline __uasminit u32 build_re(u32 arg) 183{ 184 WARN(arg & ~RE_MASK, KERN_WARNING "Micro-assembler field overflow\n"); 185 186 return (arg & RE_MASK) << RE_SH; 187} 188 189static inline __uasminit u32 build_simm(s32 arg) 190{ 191 WARN(arg > 0x7fff || arg < -0x8000, 192 KERN_WARNING "Micro-assembler field overflow\n"); 193 194 return arg & 0xffff; 195} 196 197static inline __uasminit u32 build_uimm(u32 arg) 198{ 199 WARN(arg & ~IMM_MASK, KERN_WARNING "Micro-assembler field overflow\n"); 200 201 return arg & IMM_MASK; 202} 203 204static inline __uasminit u32 build_bimm(s32 arg) 205{ 206 WARN(arg > 0x1ffff || arg < -0x20000, 207 KERN_WARNING "Micro-assembler field overflow\n"); 208 209 WARN(arg & 0x3, KERN_WARNING "Invalid micro-assembler branch target\n"); 210 211 return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff); 212} 213 214static inline __uasminit u32 build_jimm(u32 arg) 215{ 216 WARN(arg & ~(JIMM_MASK << 2), 217 KERN_WARNING "Micro-assembler field overflow\n"); 218 219 return (arg >> 2) & JIMM_MASK; 220} 221 222static inline __uasminit u32 build_scimm(u32 arg) 223{ 224 WARN(arg & ~SCIMM_MASK, 225 KERN_WARNING "Micro-assembler field overflow\n"); 226 227 return (arg & SCIMM_MASK) << SCIMM_SH; 228} 229 230static inline __uasminit u32 build_func(u32 arg) 231{ 232 WARN(arg & ~FUNC_MASK, KERN_WARNING "Micro-assembler field overflow\n"); 233 234 return arg & FUNC_MASK; 235} 236 237static inline __uasminit u32 build_set(u32 arg) 238{ 239 WARN(arg & ~SET_MASK, KERN_WARNING "Micro-assembler field overflow\n"); 240 241 return arg & SET_MASK; 242} 243 244/* 245 * The order of opcode arguments is implicitly left to right, 246 * starting with RS and ending with FUNC or IMM. 247 */ 248static void __uasminit build_insn(u32 **buf, enum opcode opc, ...) 249{ 250 struct insn *ip = NULL; 251 unsigned int i; 252 va_list ap; 253 u32 op; 254 255 for (i = 0; insn_table[i].opcode != insn_invalid; i++) 256 if (insn_table[i].opcode == opc) { 257 ip = &insn_table[i]; 258 break; 259 } 260 261 if (!ip || (opc == insn_daddiu && r4k_daddiu_bug())) 262 panic("Unsupported Micro-assembler instruction %d", opc); 263 264 op = ip->match; 265 va_start(ap, opc); 266 if (ip->fields & RS) 267 op |= build_rs(va_arg(ap, u32)); 268 if (ip->fields & RT) 269 op |= build_rt(va_arg(ap, u32)); 270 if (ip->fields & RD) 271 op |= build_rd(va_arg(ap, u32)); 272 if (ip->fields & RE) 273 op |= build_re(va_arg(ap, u32)); 274 if (ip->fields & SIMM) 275 op |= build_simm(va_arg(ap, s32)); 276 if (ip->fields & UIMM) 277 op |= build_uimm(va_arg(ap, u32)); 278 if (ip->fields & BIMM) 279 op |= build_bimm(va_arg(ap, s32)); 280 if (ip->fields & JIMM) 281 op |= build_jimm(va_arg(ap, u32)); 282 if (ip->fields & FUNC) 283 op |= build_func(va_arg(ap, u32)); 284 if (ip->fields & SET) 285 op |= build_set(va_arg(ap, u32)); 286 if (ip->fields & SCIMM) 287 op |= build_scimm(va_arg(ap, u32)); 288 va_end(ap); 289 290 **buf = op; 291 (*buf)++; 292} 293 294#define I_bit_extract(op) \ 295Ip_bit_extract(op) \ 296{ \ 297 build_insn(buf, insn##op, b, a, d-1, c); \ 298} 299#define I_bit_insert(op) \ 300Ip_bit_insert(op) \ 301{ \ 302 build_insn(buf, insn##op, b, a, c+d-1, c); \ 303} 304#define I_u1u2u3(op) \ 305Ip_u1u2u3(op) \ 306{ \ 307 build_insn(buf, insn##op, a, b, c); \ 308} \ 309UASM_EXPORT_SYMBOL(uasm_i##op); 310 311#define I_u2u1u3(op) \ 312Ip_u2u1u3(op) \ 313{ \ 314 build_insn(buf, insn##op, b, a, c); \ 315} \ 316UASM_EXPORT_SYMBOL(uasm_i##op); 317 318#define I_u3u1u2(op) \ 319Ip_u3u1u2(op) \ 320{ \ 321 build_insn(buf, insn##op, b, c, a); \ 322} \ 323UASM_EXPORT_SYMBOL(uasm_i##op); 324 325#define I_u1u2s3(op) \ 326Ip_u1u2s3(op) \ 327{ \ 328 build_insn(buf, insn##op, a, b, c); \ 329} \ 330UASM_EXPORT_SYMBOL(uasm_i##op); 331 332#define I_u2s3u1(op) \ 333Ip_u2s3u1(op) \ 334{ \ 335 build_insn(buf, insn##op, c, a, b); \ 336} \ 337UASM_EXPORT_SYMBOL(uasm_i##op); 338 339#define I_u2u1s3(op) \ 340Ip_u2u1s3(op) \ 341{ \ 342 build_insn(buf, insn##op, b, a, c); \ 343} \ 344UASM_EXPORT_SYMBOL(uasm_i##op); 345 346#define I_u2u1msbu3(op) \ 347Ip_u2u1msbu3(op) \ 348{ \ 349 build_insn(buf, insn##op, b, a, c+d-1, c); \ 350} \ 351UASM_EXPORT_SYMBOL(uasm_i##op); 352 353#define I_u2u1msb32u3(op) \ 354Ip_u2u1msbu3(op) \ 355{ \ 356 build_insn(buf, insn##op, b, a, c+d-33, c); \ 357} \ 358UASM_EXPORT_SYMBOL(uasm_i##op); 359 360#define I_u1u2(op) \ 361Ip_u1u2(op) \ 362{ \ 363 build_insn(buf, insn##op, a, b); \ 364} \ 365UASM_EXPORT_SYMBOL(uasm_i##op); 366 367#define I_u1s2(op) \ 368Ip_u1s2(op) \ 369{ \ 370 build_insn(buf, insn##op, a, b); \ 371} \ 372UASM_EXPORT_SYMBOL(uasm_i##op); 373 374#define I_u1(op) \ 375Ip_u1(op) \ 376{ \ 377 build_insn(buf, insn##op, a); \ 378} \ 379UASM_EXPORT_SYMBOL(uasm_i##op); 380 381#define I_0(op) \ 382Ip_0(op) \ 383{ \ 384 build_insn(buf, insn##op); \ 385} \ 386UASM_EXPORT_SYMBOL(uasm_i##op); 387 388I_u2u1s3(_addiu) 389I_u3u1u2(_addu) 390I_u2u1u3(_andi) 391I_u3u1u2(_and) 392I_u1u2s3(_beq) 393I_u1u2s3(_beql) 394I_u1s2(_bgez) 395I_u1s2(_bgezl) 396I_u1s2(_bltz) 397I_u1s2(_bltzl) 398I_u1u2s3(_bne) 399I_u2s3u1(_cache) 400I_u1u2u3(_dmfc0) 401I_u1u2u3(_dmtc0) 402I_u2u1s3(_daddiu) 403I_u3u1u2(_daddu) 404I_u2u1u3(_dsll) 405I_u2u1u3(_dsll32) 406I_u2u1u3(_dsra) 407I_u2u1u3(_dsrl) 408I_u2u1u3(_dsrl32) 409I_u2u1u3(_drotr) 410I_u2u1u3(_drotr32) 411I_u3u1u2(_dsubu) 412I_0(_eret) 413I_0(_iret) 414I_bit_insert(_ins) 415I_bit_extract(_ext) 416I_u1(_j) 417I_u1(_jal) 418I_u1(_jr) 419I_u2s3u1(_ld) 420I_u2s3u1(_ll) 421I_u2s3u1(_lld) 422I_u1s2(_lui) 423I_u2s3u1(_lw) 424I_u1u2u3(_mfc0) 425I_u1u2u3(_mtc0) 426I_u2u1u3(_ori) 427I_u3u1u2(_or) 428I_u2s3u1(_pref) 429I_0(_rfe) 430I_u2s3u1(_sc) 431I_u2s3u1(_scd) 432I_u2s3u1(_sd) 433I_u2u1u3(_sll) 434I_u2u1u3(_sra) 435I_u2u1u3(_srl) 436I_u2u1u3(_rotr) 437I_u3u1u2(_subu) 438I_u2s3u1(_sw) 439I_0(_tlbp) 440I_0(_tlbr) 441I_0(_tlbwi) 442I_0(_tlbwr) 443I_u3u1u2(_xor) 444I_u2u1u3(_xori) 445I_u2u1msbu3(_dins); 446I_u2u1msb32u3(_dinsm); 447I_u1(_syscall); 448I_u1u2s3(_bbit0); 449I_u1u2s3(_bbit1); 450I_u3u1u2(_lwx) 451I_u3u1u2(_ldx) 452 453/* Handle labels. */ 454void __uasminit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid) 455{ 456 (*lab)->addr = addr; 457 (*lab)->lab = lid; 458 (*lab)++; 459} 460UASM_EXPORT_SYMBOL(uasm_build_label); 461 462int __uasminit uasm_in_compat_space_p(long addr) 463{ 464 /* Is this address in 32bit compat space? */ 465#ifdef CONFIG_64BIT 466 return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L); 467#else 468 return 1; 469#endif 470} 471UASM_EXPORT_SYMBOL(uasm_in_compat_space_p); 472 473static int __uasminit uasm_rel_highest(long val) 474{ 475#ifdef CONFIG_64BIT 476 return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000; 477#else 478 return 0; 479#endif 480} 481 482static int __uasminit uasm_rel_higher(long val) 483{ 484#ifdef CONFIG_64BIT 485 return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000; 486#else 487 return 0; 488#endif 489} 490 491int __uasminit uasm_rel_hi(long val) 492{ 493 return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000; 494} 495UASM_EXPORT_SYMBOL(uasm_rel_hi); 496 497int __uasminit uasm_rel_lo(long val) 498{ 499 return ((val & 0xffff) ^ 0x8000) - 0x8000; 500} 501UASM_EXPORT_SYMBOL(uasm_rel_lo); 502 503void __uasminit UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr) 504{ 505 if (!uasm_in_compat_space_p(addr)) { 506 uasm_i_lui(buf, rs, uasm_rel_highest(addr)); 507 if (uasm_rel_higher(addr)) 508 uasm_i_daddiu(buf, rs, rs, uasm_rel_higher(addr)); 509 if (uasm_rel_hi(addr)) { 510 uasm_i_dsll(buf, rs, rs, 16); 511 uasm_i_daddiu(buf, rs, rs, uasm_rel_hi(addr)); 512 uasm_i_dsll(buf, rs, rs, 16); 513 } else 514 uasm_i_dsll32(buf, rs, rs, 0); 515 } else 516 uasm_i_lui(buf, rs, uasm_rel_hi(addr)); 517} 518UASM_EXPORT_SYMBOL(UASM_i_LA_mostly); 519 520void __uasminit UASM_i_LA(u32 **buf, unsigned int rs, long addr) 521{ 522 UASM_i_LA_mostly(buf, rs, addr); 523 if (uasm_rel_lo(addr)) { 524 if (!uasm_in_compat_space_p(addr)) 525 uasm_i_daddiu(buf, rs, rs, uasm_rel_lo(addr)); 526 else 527 uasm_i_addiu(buf, rs, rs, uasm_rel_lo(addr)); 528 } 529} 530UASM_EXPORT_SYMBOL(UASM_i_LA); 531 532/* Handle relocations. */ 533void __uasminit 534uasm_r_mips_pc16(struct uasm_reloc **rel, u32 *addr, int lid) 535{ 536 (*rel)->addr = addr; 537 (*rel)->type = R_MIPS_PC16; 538 (*rel)->lab = lid; 539 (*rel)++; 540} 541UASM_EXPORT_SYMBOL(uasm_r_mips_pc16); 542 543static inline void __uasminit 544__resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab) 545{ 546 long laddr = (long)lab->addr; 547 long raddr = (long)rel->addr; 548 549 switch (rel->type) { 550 case R_MIPS_PC16: 551 *rel->addr |= build_bimm(laddr - (raddr + 4)); 552 break; 553 554 default: 555 panic("Unsupported Micro-assembler relocation %d", 556 rel->type); 557 } 558} 559 560void __uasminit 561uasm_resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab) 562{ 563 struct uasm_label *l; 564 565 for (; rel->lab != UASM_LABEL_INVALID; rel++) 566 for (l = lab; l->lab != UASM_LABEL_INVALID; l++) 567 if (rel->lab == l->lab) 568 __resolve_relocs(rel, l); 569} 570UASM_EXPORT_SYMBOL(uasm_resolve_relocs); 571 572void __uasminit 573uasm_move_relocs(struct uasm_reloc *rel, u32 *first, u32 *end, long off) 574{ 575 for (; rel->lab != UASM_LABEL_INVALID; rel++) 576 if (rel->addr >= first && rel->addr < end) 577 rel->addr += off; 578} 579UASM_EXPORT_SYMBOL(uasm_move_relocs); 580 581void __uasminit 582uasm_move_labels(struct uasm_label *lab, u32 *first, u32 *end, long off) 583{ 584 for (; lab->lab != UASM_LABEL_INVALID; lab++) 585 if (lab->addr >= first && lab->addr < end) 586 lab->addr += off; 587} 588UASM_EXPORT_SYMBOL(uasm_move_labels); 589 590void __uasminit 591uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab, u32 *first, 592 u32 *end, u32 *target) 593{ 594 long off = (long)(target - first); 595 596 memcpy(target, first, (end - first) * sizeof(u32)); 597 598 uasm_move_relocs(rel, first, end, off); 599 uasm_move_labels(lab, first, end, off); 600} 601UASM_EXPORT_SYMBOL(uasm_copy_handler); 602 603int __uasminit uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr) 604{ 605 for (; rel->lab != UASM_LABEL_INVALID; rel++) { 606 if (rel->addr == addr 607 && (rel->type == R_MIPS_PC16 608 || rel->type == R_MIPS_26)) 609 return 1; 610 } 611 612 return 0; 613} 614UASM_EXPORT_SYMBOL(uasm_insn_has_bdelay); 615 616/* Convenience functions for labeled branches. */ 617void __uasminit 618uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid) 619{ 620 uasm_r_mips_pc16(r, *p, lid); 621 uasm_i_bltz(p, reg, 0); 622} 623UASM_EXPORT_SYMBOL(uasm_il_bltz); 624 625void __uasminit 626uasm_il_b(u32 **p, struct uasm_reloc **r, int lid) 627{ 628 uasm_r_mips_pc16(r, *p, lid); 629 uasm_i_b(p, 0); 630} 631UASM_EXPORT_SYMBOL(uasm_il_b); 632 633void __uasminit 634uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid) 635{ 636 uasm_r_mips_pc16(r, *p, lid); 637 uasm_i_beqz(p, reg, 0); 638} 639UASM_EXPORT_SYMBOL(uasm_il_beqz); 640 641void __uasminit 642uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid) 643{ 644 uasm_r_mips_pc16(r, *p, lid); 645 uasm_i_beqzl(p, reg, 0); 646} 647UASM_EXPORT_SYMBOL(uasm_il_beqzl); 648 649void __uasminit 650uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1, 651 unsigned int reg2, int lid) 652{ 653 uasm_r_mips_pc16(r, *p, lid); 654 uasm_i_bne(p, reg1, reg2, 0); 655} 656UASM_EXPORT_SYMBOL(uasm_il_bne); 657 658void __uasminit 659uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid) 660{ 661 uasm_r_mips_pc16(r, *p, lid); 662 uasm_i_bnez(p, reg, 0); 663} 664UASM_EXPORT_SYMBOL(uasm_il_bnez); 665 666void __uasminit 667uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid) 668{ 669 uasm_r_mips_pc16(r, *p, lid); 670 uasm_i_bgezl(p, reg, 0); 671} 672UASM_EXPORT_SYMBOL(uasm_il_bgezl); 673 674void __uasminit 675uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid) 676{ 677 uasm_r_mips_pc16(r, *p, lid); 678 uasm_i_bgez(p, reg, 0); 679} 680UASM_EXPORT_SYMBOL(uasm_il_bgez); 681 682void __uasminit 683uasm_il_bbit0(u32 **p, struct uasm_reloc **r, unsigned int reg, 684 unsigned int bit, int lid) 685{ 686 uasm_r_mips_pc16(r, *p, lid); 687 uasm_i_bbit0(p, reg, bit, 0); 688} 689UASM_EXPORT_SYMBOL(uasm_il_bbit0); 690 691void __uasminit 692uasm_il_bbit1(u32 **p, struct uasm_reloc **r, unsigned int reg, 693 unsigned int bit, int lid) 694{ 695 uasm_r_mips_pc16(r, *p, lid); 696 uasm_i_bbit1(p, reg, bit, 0); 697} 698UASM_EXPORT_SYMBOL(uasm_il_bbit1); 699