1/* 2 * cpu.h: Values of the PRId register used to match up 3 * various MIPS cpu types. 4 * 5 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) 6 * Copyright (C) 2004 Maciej W. Rozycki 7 */ 8#ifndef _ASM_CPU_H 9#define _ASM_CPU_H 10 11/* Assigned Company values for bits 23:16 of the PRId Register 12 (CP0 register 15, select 0). As of the MIPS32 and MIPS64 specs from 13 MTI, the PRId register is defined in this (backwards compatible) 14 way: 15 16 +----------------+----------------+----------------+----------------+ 17 | Company Options| Company ID | Processor ID | Revision | 18 +----------------+----------------+----------------+----------------+ 19 31 24 23 16 15 8 7 20 21 I don't have docs for all the previous processors, but my impression is 22 that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64 23 spec. 24*/ 25 26#define PRID_COMP_LEGACY 0x000000 27#define PRID_COMP_MIPS 0x010000 28#define PRID_COMP_BROADCOM 0x020000 29#define PRID_COMP_ALCHEMY 0x030000 30#define PRID_COMP_SIBYTE 0x040000 31#define PRID_COMP_SANDCRAFT 0x050000 32#define PRID_COMP_NXP 0x060000 33#define PRID_COMP_TOSHIBA 0x070000 34#define PRID_COMP_LSI 0x080000 35#define PRID_COMP_LEXRA 0x0b0000 36#define PRID_COMP_CAVIUM 0x0d0000 37#define PRID_COMP_INGENIC 0xd00000 38 39/* 40 * Assigned values for the product ID register. In order to detect a 41 * certain CPU type exactly eventually additional registers may need to 42 * be examined. These are valid when 23:16 == PRID_COMP_LEGACY 43 */ 44#define PRID_IMP_R2000 0x0100 45#define PRID_IMP_AU1_REV1 0x0100 46#define PRID_IMP_AU1_REV2 0x0200 47#define PRID_IMP_R3000 0x0200 /* Same as R2000A */ 48#define PRID_IMP_R6000 0x0300 /* Same as R3000A */ 49#define PRID_IMP_R4000 0x0400 50#define PRID_IMP_R6000A 0x0600 51#define PRID_IMP_R10000 0x0900 52#define PRID_IMP_R4300 0x0b00 53#define PRID_IMP_VR41XX 0x0c00 54#define PRID_IMP_R12000 0x0e00 55#define PRID_IMP_R14000 0x0f00 56#define PRID_IMP_R8000 0x1000 57#define PRID_IMP_PR4450 0x1200 58#define PRID_IMP_R4600 0x2000 59#define PRID_IMP_R4700 0x2100 60#define PRID_IMP_TX39 0x2200 61#define PRID_IMP_R4640 0x2200 62#define PRID_IMP_R4650 0x2200 /* Same as R4640 */ 63#define PRID_IMP_R5000 0x2300 64#define PRID_IMP_TX49 0x2d00 65#define PRID_IMP_SONIC 0x2400 66#define PRID_IMP_MAGIC 0x2500 67#define PRID_IMP_RM7000 0x2700 68#define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */ 69#define PRID_IMP_RM9000 0x3400 70#define PRID_IMP_LOONGSON1 0x4200 71#define PRID_IMP_R5432 0x5400 72#define PRID_IMP_R5500 0x5500 73#define PRID_IMP_LOONGSON2 0x6300 74 75#define PRID_IMP_UNKNOWN 0xff00 76 77/* 78 * These are the PRID's for when 23:16 == PRID_COMP_MIPS 79 */ 80 81#define PRID_IMP_4KC 0x8000 82#define PRID_IMP_5KC 0x8100 83#define PRID_IMP_20KC 0x8200 84#define PRID_IMP_4KEC 0x8400 85#define PRID_IMP_4KSC 0x8600 86#define PRID_IMP_25KF 0x8800 87#define PRID_IMP_5KE 0x8900 88#define PRID_IMP_4KECR2 0x9000 89#define PRID_IMP_4KEMPR2 0x9100 90#define PRID_IMP_4KSD 0x9200 91#define PRID_IMP_24K 0x9300 92#define PRID_IMP_34K 0x9500 93#define PRID_IMP_24KE 0x9600 94#define PRID_IMP_74K 0x9700 95#define PRID_IMP_1004K 0x9900 96#define PRID_IMP_1074K 0x9a00 97#define PRID_IMP_14K 0x9c00 98#define PRID_IMP_14KE 0x9e00 99 100/* 101 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE 102 */ 103 104#define PRID_IMP_SB1 0x0100 105#define PRID_IMP_SB1A 0x1100 106 107/* 108 * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT 109 */ 110 111#define PRID_IMP_SR71000 0x0400 112 113/* 114 * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM 115 */ 116 117#define PRID_IMP_BCM4710 0x4000 118#define PRID_IMP_BCM3302 0x9000 119#define PRID_IMP_BCM6338 0x9000 120#define PRID_IMP_BCM6345 0x8000 121#define PRID_IMP_BCM6348 0x9100 122#define PRID_IMP_BCM4350 0xA000 123#define PRID_REV_BCM6358 0x0010 124#define PRID_REV_BCM6368 0x0030 125 126/* 127 * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM 128 */ 129 130#define PRID_IMP_CAVIUM_CN38XX 0x0000 131#define PRID_IMP_CAVIUM_CN31XX 0x0100 132#define PRID_IMP_CAVIUM_CN30XX 0x0200 133#define PRID_IMP_CAVIUM_CN58XX 0x0300 134#define PRID_IMP_CAVIUM_CN56XX 0x0400 135#define PRID_IMP_CAVIUM_CN50XX 0x0600 136#define PRID_IMP_CAVIUM_CN52XX 0x0700 137#define PRID_IMP_CAVIUM_CN63XX 0x9000 138 139/* 140 * These are the PRID's for when 23:16 == PRID_COMP_INGENIC 141 */ 142 143#define PRID_IMP_JZRISC 0x0200 144 145/* 146 * Definitions for 7:0 on legacy processors 147 */ 148 149#define PRID_REV_MASK 0x00ff 150 151#define PRID_REV_TX4927 0x0022 152#define PRID_REV_TX4937 0x0030 153#define PRID_REV_R4400 0x0040 154#define PRID_REV_R3000A 0x0030 155#define PRID_REV_R3000 0x0020 156#define PRID_REV_R2000A 0x0010 157#define PRID_REV_TX3912 0x0010 158#define PRID_REV_TX3922 0x0030 159#define PRID_REV_TX3927 0x0040 160#define PRID_REV_VR4111 0x0050 161#define PRID_REV_VR4181 0x0050 /* Same as VR4111 */ 162#define PRID_REV_VR4121 0x0060 163#define PRID_REV_VR4122 0x0070 164#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */ 165#define PRID_REV_VR4130 0x0080 166#define PRID_REV_34K_V1_0_2 0x0022 167#define PRID_REV_LOONGSON2E 0x0002 168#define PRID_REV_LOONGSON2F 0x0003 169 170/* 171 * Older processors used to encode processor version and revision in two 172 * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores 173 * have switched to use the 8-bits as 3:3:2 bitfield with the last field as 174 * the patch number. *ARGH* 175 */ 176#define PRID_REV_ENCODE_44(ver, rev) \ 177 ((ver) << 4 | (rev)) 178#define PRID_REV_ENCODE_332(ver, rev, patch) \ 179 ((ver) << 5 | (rev) << 2 | (patch)) 180 181/* 182 * FPU implementation/revision register (CP1 control register 0). 183 * 184 * +---------------------------------+----------------+----------------+ 185 * | 0 | Implementation | Revision | 186 * +---------------------------------+----------------+----------------+ 187 * 31 16 15 8 7 0 188 */ 189 190#define FPIR_IMP_NONE 0x0000 191 192enum cpu_type_enum { 193 CPU_UNKNOWN, 194 195 /* 196 * R2000 class processors 197 */ 198 CPU_R2000, CPU_R3000, CPU_R3000A, CPU_R3041, CPU_R3051, CPU_R3052, 199 CPU_R3081, CPU_R3081E, 200 201 /* 202 * R6000 class processors 203 */ 204 CPU_R6000, CPU_R6000A, 205 206 /* 207 * R4000 class processors 208 */ 209 CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310, 210 CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650, 211 CPU_R4700, CPU_R5000, CPU_R5000A, CPU_R5500, CPU_NEVADA, CPU_R5432, 212 CPU_R10000, CPU_R12000, CPU_R14000, CPU_VR41XX, CPU_VR4111, CPU_VR4121, 213 CPU_VR4122, CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000, 214 CPU_SR71000, CPU_RM9000, CPU_TX49XX, 215 216 /* 217 * R8000 class processors 218 */ 219 CPU_R8000, 220 221 /* 222 * TX3900 class processors 223 */ 224 CPU_TX3912, CPU_TX3922, CPU_TX3927, 225 226 /* 227 * MIPS32 class processors 228 */ 229 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, 230 CPU_ALCHEMY, CPU_PR4450, CPU_BCM3302, CPU_BCM4710, 231 CPU_BCM6338, CPU_BCM6345, CPU_BCM6348, CPU_BCM6358, CPU_14K, CPU_14KE, 232 CPU_1074K, CPU_JZRISC, 233 234 /* 235 * MIPS64 class processors 236 */ 237 CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, 238 CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2, 239 240 CPU_LAST 241}; 242 243 244/* 245 * ISA Level encodings 246 * 247 */ 248#define MIPS_CPU_ISA_I 0x00000001 249#define MIPS_CPU_ISA_II 0x00000002 250#define MIPS_CPU_ISA_III 0x00000004 251#define MIPS_CPU_ISA_IV 0x00000008 252#define MIPS_CPU_ISA_V 0x00000010 253#define MIPS_CPU_ISA_M32R1 0x00000020 254#define MIPS_CPU_ISA_M32R2 0x00000040 255#define MIPS_CPU_ISA_M64R1 0x00000080 256#define MIPS_CPU_ISA_M64R2 0x00000100 257 258#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | \ 259 MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2) 260#define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \ 261 MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2) 262 263/* 264 * CPU Option encodings 265 */ 266#define MIPS_CPU_TLB 0x00000001 /* CPU has TLB */ 267#define MIPS_CPU_4KEX 0x00000002 /* "R4K" exception model */ 268#define MIPS_CPU_3K_CACHE 0x00000004 /* R3000-style caches */ 269#define MIPS_CPU_4K_CACHE 0x00000008 /* R4000-style caches */ 270#define MIPS_CPU_TX39_CACHE 0x00000010 /* TX3900-style caches */ 271#define MIPS_CPU_FPU 0x00000020 /* CPU has FPU */ 272#define MIPS_CPU_32FPR 0x00000040 /* 32 dbl. prec. FP registers */ 273#define MIPS_CPU_COUNTER 0x00000080 /* Cycle count/compare */ 274#define MIPS_CPU_WATCH 0x00000100 /* watchpoint registers */ 275#define MIPS_CPU_DIVEC 0x00000200 /* dedicated interrupt vector */ 276#define MIPS_CPU_VCE 0x00000400 /* virt. coherence conflict possible */ 277#define MIPS_CPU_CACHE_CDEX_P 0x00000800 /* Create_Dirty_Exclusive CACHE op */ 278#define MIPS_CPU_CACHE_CDEX_S 0x00001000 /* ... same for seconary cache ... */ 279#define MIPS_CPU_MCHECK 0x00002000 /* Machine check exception */ 280#define MIPS_CPU_EJTAG 0x00004000 /* EJTAG exception */ 281#define MIPS_CPU_NOFPUEX 0x00008000 /* no FPU exception */ 282#define MIPS_CPU_LLSC 0x00010000 /* CPU has ll/sc instructions */ 283#define MIPS_CPU_INCLUSIVE_CACHES 0x00020000 /* P-cache subset enforced */ 284#define MIPS_CPU_PREFETCH 0x00040000 /* CPU has usable prefetch */ 285#define MIPS_CPU_VINT 0x00080000 /* CPU supports MIPSR2 vectored interrupts */ 286#define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */ 287#define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */ 288#define MIPS_CPU_CTXTC 0x00400000 /* CPU has ContextConfig feature */ 289#define MIPS_CPU_PGDC_CC 0x00800000 /* CPU has usable ContextConfig */ 290#define MIPS_CPU_MICROMIPS 0x01000000 /* CPU has microMIPS capability */ 291 292/* 293 * CPU ASE encodings 294 */ 295#define MIPS_ASE_MIPS16 0x00000001 /* code compression */ 296#define MIPS_ASE_MDMX 0x00000002 /* MIPS digital media extension */ 297#define MIPS_ASE_MIPS3D 0x00000004 /* MIPS-3D */ 298#define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */ 299#define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */ 300#define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */ 301 302 303#endif /* _ASM_CPU_H */ 304