1/* 2 * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu> 3 * Copyright (C) 2007-2009 PetaLogix 4 * Copyright (C) 2006 Atmark Techno, Inc. 5 * 6 * MMU code derived from arch/ppc/kernel/head_4xx.S: 7 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org> 8 * Initial PowerPC version. 9 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu> 10 * Rewritten for PReP 11 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au> 12 * Low-level exception handers, MMU support, and rewrite. 13 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net> 14 * PowerPC 8xx modifications. 15 * Copyright (c) 1998-1999 TiVo, Inc. 16 * PowerPC 403GCX modifications. 17 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> 18 * PowerPC 403GCX/405GP modifications. 19 * Copyright 2000 MontaVista Software Inc. 20 * PPC405 modifications 21 * PowerPC 403GCX/405GP modifications. 22 * Author: MontaVista Software, Inc. 23 * frank_rowand@mvista.com or source@mvista.com 24 * debbie_chu@mvista.com 25 * 26 * This file is subject to the terms and conditions of the GNU General Public 27 * License. See the file "COPYING" in the main directory of this archive 28 * for more details. 29 */ 30 31#include <linux/init.h> 32#include <linux/linkage.h> 33#include <asm/thread_info.h> 34#include <asm/page.h> 35#include <linux/of_fdt.h> /* for OF_DT_HEADER */ 36 37#ifdef CONFIG_MMU 38#include <asm/setup.h> /* COMMAND_LINE_SIZE */ 39#include <asm/mmu.h> 40#include <asm/processor.h> 41 42.data 43.global empty_zero_page 44.align 12 45empty_zero_page: 46 .space PAGE_SIZE 47.global swapper_pg_dir 48swapper_pg_dir: 49 .space PAGE_SIZE 50 51#endif /* CONFIG_MMU */ 52 53 __HEAD 54ENTRY(_start) 55#if CONFIG_KERNEL_BASE_ADDR == 0 56 brai TOPHYS(real_start) 57 .org 0x100 58real_start: 59#endif 60 61 mfs r1, rmsr 62 andi r1, r1, ~2 63 mts rmsr, r1 64/* 65 * Here is checking mechanism which check if Microblaze has msr instructions 66 * We load msr and compare it with previous r1 value - if is the same, 67 * msr instructions works if not - cpu don't have them. 68 */ 69 /* r8=0 - I have msr instr, 1 - I don't have them */ 70 rsubi r0, r0, 1 /* set the carry bit */ 71 msrclr r0, 0x4 /* try to clear it */ 72 /* read the carry bit, r8 will be '0' if msrclr exists */ 73 addik r8, r0, 0 74 75/* r7 may point to an FDT, or there may be one linked in. 76 if it's in r7, we've got to save it away ASAP. 77 We ensure r7 points to a valid FDT, just in case the bootloader 78 is broken or non-existent */ 79 beqi r7, no_fdt_arg /* NULL pointer? don't copy */ 80 lw r11, r0, r7 /* Does r7 point to a */ 81 rsubi r11, r11, OF_DT_HEADER /* valid FDT? */ 82 beqi r11, _prepare_copy_fdt 83 or r7, r0, r0 /* clear R7 when not valid DTB */ 84 bnei r11, no_fdt_arg /* No - get out of here */ 85_prepare_copy_fdt: 86 or r11, r0, r0 /* incremment */ 87 ori r4, r0, TOPHYS(_fdt_start) 88 ori r3, r0, (0x4000 - 4) 89_copy_fdt: 90 lw r12, r7, r11 /* r12 = r7 + r11 */ 91 sw r12, r4, r11 /* addr[r4 + r11] = r12 */ 92 addik r11, r11, 4 /* increment counting */ 93 bgtid r3, _copy_fdt /* loop for all entries */ 94 addik r3, r3, -4 /* descrement loop */ 95no_fdt_arg: 96 97#ifdef CONFIG_MMU 98 99#ifndef CONFIG_CMDLINE_BOOL 100/* 101 * handling command line 102 * copy command line to __init_end. There is space for storing command line. 103 */ 104 or r6, r0, r0 /* incremment */ 105 ori r4, r0, __init_end /* load address of command line */ 106 tophys(r4,r4) /* convert to phys address */ 107 ori r3, r0, COMMAND_LINE_SIZE - 1 /* number of loops */ 108_copy_command_line: 109 lbu r2, r5, r6 /* r2=r5+r6 - r5 contain pointer to command line */ 110 sb r2, r4, r6 /* addr[r4+r6]= r2*/ 111 addik r6, r6, 1 /* increment counting */ 112 bgtid r3, _copy_command_line /* loop for all entries */ 113 addik r3, r3, -1 /* descrement loop */ 114 addik r5, r4, 0 /* add new space for command line */ 115 tovirt(r5,r5) 116#endif /* CONFIG_CMDLINE_BOOL */ 117 118#ifdef NOT_COMPILE 119/* save bram context */ 120 or r6, r0, r0 /* incremment */ 121 ori r4, r0, TOPHYS(_bram_load_start) /* save bram context */ 122 ori r3, r0, (LMB_SIZE - 4) 123_copy_bram: 124 lw r7, r0, r6 /* r7 = r0 + r6 */ 125 sw r7, r4, r6 /* addr[r4 + r6] = r7*/ 126 addik r6, r6, 4 /* increment counting */ 127 bgtid r3, _copy_bram /* loop for all entries */ 128 addik r3, r3, -4 /* descrement loop */ 129#endif 130 /* We have to turn on the MMU right away. */ 131 132 /* 133 * Set up the initial MMU state so we can do the first level of 134 * kernel initialization. This maps the first 16 MBytes of memory 1:1 135 * virtual to physical. 136 */ 137 nop 138 addik r3, r0, MICROBLAZE_TLB_SIZE -1 /* Invalidate all TLB entries */ 139_invalidate: 140 mts rtlbx, r3 141 mts rtlbhi, r0 /* flush: ensure V is clear */ 142 bgtid r3, _invalidate /* loop for all entries */ 143 addik r3, r3, -1 144 /* sync */ 145 146 /* Setup the kernel PID */ 147 mts rpid,r0 /* Load the kernel PID */ 148 nop 149 bri 4 150 151 /* 152 * We should still be executing code at physical address area 153 * RAM_BASEADDR at this point. However, kernel code is at 154 * a virtual address. So, set up a TLB mapping to cover this once 155 * translation is enabled. 156 */ 157 158 addik r3,r0, CONFIG_KERNEL_START /* Load the kernel virtual address */ 159 tophys(r4,r3) /* Load the kernel physical address */ 160 161 /* 162 * Configure and load two entries into TLB slots 0 and 1. 163 * In case we are pinning TLBs, these are reserved in by the 164 * other TLB functions. If not reserving, then it doesn't 165 * matter where they are loaded. 166 */ 167 andi r4,r4,0xfffffc00 /* Mask off the real page number */ 168 ori r4,r4,(TLB_WR | TLB_EX) /* Set the write and execute bits */ 169 170 andi r3,r3,0xfffffc00 /* Mask off the effective page number */ 171 ori r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_16M)) 172 173 mts rtlbx,r0 /* TLB slow 0 */ 174 175 mts rtlblo,r4 /* Load the data portion of the entry */ 176 mts rtlbhi,r3 /* Load the tag portion of the entry */ 177 178 addik r4, r4, 0x01000000 /* Map next 16 M entries */ 179 addik r3, r3, 0x01000000 180 181 ori r6,r0,1 /* TLB slot 1 */ 182 mts rtlbx,r6 183 184 mts rtlblo,r4 /* Load the data portion of the entry */ 185 mts rtlbhi,r3 /* Load the tag portion of the entry */ 186 187 /* 188 * Load a TLB entry for LMB, since we need access to 189 * the exception vectors, using a 4k real==virtual mapping. 190 */ 191 ori r6,r0,3 /* TLB slot 3 */ 192 mts rtlbx,r6 193 194 ori r4,r0,(TLB_WR | TLB_EX) 195 ori r3,r0,(TLB_VALID | TLB_PAGESZ(PAGESZ_4K)) 196 197 mts rtlblo,r4 /* Load the data portion of the entry */ 198 mts rtlbhi,r3 /* Load the tag portion of the entry */ 199 200 /* 201 * We now have the lower 16 Meg of RAM mapped into TLB entries, and the 202 * caches ready to work. 203 */ 204turn_on_mmu: 205 ori r15,r0,start_here 206 ori r4,r0,MSR_KERNEL_VMS 207 mts rmsr,r4 208 nop 209 rted r15,0 /* enables MMU */ 210 nop 211 212start_here: 213#endif /* CONFIG_MMU */ 214 215 /* Initialize small data anchors */ 216 la r13, r0, _KERNEL_SDA_BASE_ 217 la r2, r0, _KERNEL_SDA2_BASE_ 218 219 /* Initialize stack pointer */ 220 la r1, r0, init_thread_union + THREAD_SIZE - 4 221 222 /* Initialize r31 with current task address */ 223 la r31, r0, init_task 224 225 /* 226 * Call platform dependent initialize function. 227 * Please see $(ARCH)/mach-$(SUBARCH)/setup.c for 228 * the function. 229 */ 230 la r9, r0, machine_early_init 231 brald r15, r9 232 nop 233 234#ifndef CONFIG_MMU 235 la r15, r0, machine_halt 236 braid start_kernel 237 nop 238#else 239 /* 240 * Initialize the MMU. 241 */ 242 bralid r15, mmu_init 243 nop 244 245 /* Go back to running unmapped so we can load up new values 246 * and change to using our exception vectors. 247 * On the MicroBlaze, all we invalidate the used TLB entries to clear 248 * the old 16M byte TLB mappings. 249 */ 250 ori r15,r0,TOPHYS(kernel_load_context) 251 ori r4,r0,MSR_KERNEL 252 mts rmsr,r4 253 nop 254 bri 4 255 rted r15,0 256 nop 257 258 /* Load up the kernel context */ 259kernel_load_context: 260 # Keep entry 0 and 1 valid. Entry 3 mapped to LMB can go away. 261 ori r5,r0,3 262 mts rtlbx,r5 263 nop 264 mts rtlbhi,r0 265 nop 266 addi r15, r0, machine_halt 267 ori r17, r0, start_kernel 268 ori r4, r0, MSR_KERNEL_VMS 269 mts rmsr, r4 270 nop 271 rted r17, 0 /* enable MMU and jump to start_kernel */ 272 nop 273#endif /* CONFIG_MMU */ 274