1/* 2 * linux/arch/m32r/platforms/m32104ut/setup.c 3 * 4 * Setup routines for M32104UT Board 5 * 6 * Copyright (c) 2002-2005 Hiroyuki Kondo, Hirokazu Takata, 7 * Hitoshi Yamamoto, Mamoru Sakugawa, 8 * Naoto Sugai, Hayato Fujiwara 9 */ 10 11#include <linux/irq.h> 12#include <linux/kernel.h> 13#include <linux/init.h> 14#include <linux/device.h> 15 16#include <asm/system.h> 17#include <asm/m32r.h> 18#include <asm/io.h> 19 20#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long))) 21 22icu_data_t icu_data[NR_IRQS]; 23 24static void disable_m32104ut_irq(unsigned int irq) 25{ 26 unsigned long port, data; 27 28 port = irq2port(irq); 29 data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7; 30 outl(data, port); 31} 32 33static void enable_m32104ut_irq(unsigned int irq) 34{ 35 unsigned long port, data; 36 37 port = irq2port(irq); 38 data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6; 39 outl(data, port); 40} 41 42static void mask_and_ack_m32104ut(unsigned int irq) 43{ 44 disable_m32104ut_irq(irq); 45} 46 47static void end_m32104ut_irq(unsigned int irq) 48{ 49 enable_m32104ut_irq(irq); 50} 51 52static unsigned int startup_m32104ut_irq(unsigned int irq) 53{ 54 enable_m32104ut_irq(irq); 55 return (0); 56} 57 58static void shutdown_m32104ut_irq(unsigned int irq) 59{ 60 unsigned long port; 61 62 port = irq2port(irq); 63 outl(M32R_ICUCR_ILEVEL7, port); 64} 65 66static struct irq_chip m32104ut_irq_type = 67{ 68 .typename = "M32104UT-IRQ", 69 .startup = startup_m32104ut_irq, 70 .shutdown = shutdown_m32104ut_irq, 71 .enable = enable_m32104ut_irq, 72 .disable = disable_m32104ut_irq, 73 .ack = mask_and_ack_m32104ut, 74 .end = end_m32104ut_irq 75}; 76 77void __init init_IRQ(void) 78{ 79 static int once = 0; 80 81 if (once) 82 return; 83 else 84 once++; 85 86#if defined(CONFIG_SMC91X) 87 /* INT#0: LAN controller on M32104UT-LAN (SMC91C111)*/ 88 irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED; 89 irq_desc[M32R_IRQ_INT0].chip = &m32104ut_irq_type; 90 irq_desc[M32R_IRQ_INT0].action = 0; 91 irq_desc[M32R_IRQ_INT0].depth = 1; 92 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD11; /* "H" level sense */ 93 disable_m32104ut_irq(M32R_IRQ_INT0); 94#endif /* CONFIG_SMC91X */ 95 96 /* MFT2 : system timer */ 97 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; 98 irq_desc[M32R_IRQ_MFT2].chip = &m32104ut_irq_type; 99 irq_desc[M32R_IRQ_MFT2].action = 0; 100 irq_desc[M32R_IRQ_MFT2].depth = 1; 101 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 102 disable_m32104ut_irq(M32R_IRQ_MFT2); 103 104#ifdef CONFIG_SERIAL_M32R_SIO 105 /* SIO0_R : uart receive data */ 106 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; 107 irq_desc[M32R_IRQ_SIO0_R].chip = &m32104ut_irq_type; 108 irq_desc[M32R_IRQ_SIO0_R].action = 0; 109 irq_desc[M32R_IRQ_SIO0_R].depth = 1; 110 icu_data[M32R_IRQ_SIO0_R].icucr = M32R_ICUCR_IEN; 111 disable_m32104ut_irq(M32R_IRQ_SIO0_R); 112 113 /* SIO0_S : uart send data */ 114 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; 115 irq_desc[M32R_IRQ_SIO0_S].chip = &m32104ut_irq_type; 116 irq_desc[M32R_IRQ_SIO0_S].action = 0; 117 irq_desc[M32R_IRQ_SIO0_S].depth = 1; 118 icu_data[M32R_IRQ_SIO0_S].icucr = M32R_ICUCR_IEN; 119 disable_m32104ut_irq(M32R_IRQ_SIO0_S); 120#endif /* CONFIG_SERIAL_M32R_SIO */ 121} 122 123#if defined(CONFIG_SMC91X) 124 125#define LAN_IOSTART 0x300 126#define LAN_IOEND 0x320 127static struct resource smc91x_resources[] = { 128 [0] = { 129 .start = (LAN_IOSTART), 130 .end = (LAN_IOEND), 131 .flags = IORESOURCE_MEM, 132 }, 133 [1] = { 134 .start = M32R_IRQ_INT0, 135 .end = M32R_IRQ_INT0, 136 .flags = IORESOURCE_IRQ, 137 } 138}; 139 140static struct platform_device smc91x_device = { 141 .name = "smc91x", 142 .id = 0, 143 .num_resources = ARRAY_SIZE(smc91x_resources), 144 .resource = smc91x_resources, 145}; 146#endif 147 148static int __init platform_init(void) 149{ 150#if defined(CONFIG_SMC91X) 151 platform_device_register(&smc91x_device); 152#endif 153 return 0; 154} 155arch_initcall(platform_init); 156