1/* 2 * linux/arch/cris/arch-v32/kernel/time.c 3 * 4 * Copyright (C) 2003-2010 Axis Communications AB 5 * 6 */ 7 8#include <linux/timex.h> 9#include <linux/time.h> 10#include <linux/clocksource.h> 11#include <linux/interrupt.h> 12#include <linux/swap.h> 13#include <linux/sched.h> 14#include <linux/init.h> 15#include <linux/threads.h> 16#include <linux/cpufreq.h> 17#include <asm/types.h> 18#include <asm/signal.h> 19#include <asm/io.h> 20#include <asm/delay.h> 21#include <asm/rtc.h> 22#include <asm/irq.h> 23#include <asm/irq_regs.h> 24 25#include <hwregs/reg_map.h> 26#include <hwregs/reg_rdwr.h> 27#include <hwregs/timer_defs.h> 28#include <hwregs/intr_vect_defs.h> 29#ifdef CONFIG_CRIS_MACH_ARTPEC3 30#include <hwregs/clkgen_defs.h> 31#endif 32 33/* Watchdog defines */ 34#define ETRAX_WD_KEY_MASK 0x7F /* key is 7 bit */ 35#define ETRAX_WD_HZ 763 /* watchdog counts at 763 Hz */ 36/* Number of 763 counts before watchdog bites */ 37#define ETRAX_WD_CNT ((2*ETRAX_WD_HZ)/HZ + 1) 38 39/* Register the continuos readonly timer available in FS and ARTPEC-3. */ 40static cycle_t read_cont_rotime(struct clocksource *cs) 41{ 42 return (u32)REG_RD(timer, regi_timer0, r_time); 43} 44 45static struct clocksource cont_rotime = { 46 .name = "crisv32_rotime", 47 .rating = 300, 48 .read = read_cont_rotime, 49 .mask = CLOCKSOURCE_MASK(32), 50 .shift = 10, 51 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 52}; 53 54static int __init etrax_init_cont_rotime(void) 55{ 56 cont_rotime.mult = clocksource_khz2mult(100000, cont_rotime.shift); 57 clocksource_register(&cont_rotime); 58 return 0; 59} 60arch_initcall(etrax_init_cont_rotime); 61 62 63unsigned long timer_regs[NR_CPUS] = 64{ 65 regi_timer0, 66#ifdef CONFIG_SMP 67 regi_timer2 68#endif 69}; 70 71extern int set_rtc_mmss(unsigned long nowtime); 72extern int have_rtc; 73 74#ifdef CONFIG_CPU_FREQ 75static int 76cris_time_freq_notifier(struct notifier_block *nb, unsigned long val, 77 void *data); 78 79static struct notifier_block cris_time_freq_notifier_block = { 80 .notifier_call = cris_time_freq_notifier, 81}; 82#endif 83 84unsigned long get_ns_in_jiffie(void) 85{ 86 reg_timer_r_tmr0_data data; 87 unsigned long ns; 88 89 data = REG_RD(timer, regi_timer0, r_tmr0_data); 90 ns = (TIMER0_DIV - data) * 10; 91 return ns; 92} 93 94 95/* From timer MDS describing the hardware watchdog: 96 * 4.3.1 Watchdog Operation 97 * The watchdog timer is an 8-bit timer with a configurable start value. 98 * Once started the watchdog counts downwards with a frequency of 763 Hz 99 * (100/131072 MHz). When the watchdog counts down to 1, it generates an 100 * NMI (Non Maskable Interrupt), and when it counts down to 0, it resets the 101 * chip. 102 */ 103/* This gives us 1.3 ms to do something useful when the NMI comes */ 104 105/* Right now, starting the watchdog is the same as resetting it */ 106#define start_watchdog reset_watchdog 107 108#if defined(CONFIG_ETRAX_WATCHDOG) 109static short int watchdog_key = 42; /* arbitrary 7 bit number */ 110#endif 111 112/* Number of pages to consider "out of memory". It is normal that the memory 113 * is used though, so set this really low. */ 114#define WATCHDOG_MIN_FREE_PAGES 8 115 116void reset_watchdog(void) 117{ 118#if defined(CONFIG_ETRAX_WATCHDOG) 119 reg_timer_rw_wd_ctrl wd_ctrl = { 0 }; 120 121 /* Only keep watchdog happy as long as we have memory left! */ 122 if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES) { 123 /* Reset the watchdog with the inverse of the old key */ 124 /* Invert key, which is 7 bits */ 125 watchdog_key ^= ETRAX_WD_KEY_MASK; 126 wd_ctrl.cnt = ETRAX_WD_CNT; 127 wd_ctrl.cmd = regk_timer_start; 128 wd_ctrl.key = watchdog_key; 129 REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl); 130 } 131#endif 132} 133 134/* stop the watchdog - we still need the correct key */ 135 136void stop_watchdog(void) 137{ 138#if defined(CONFIG_ETRAX_WATCHDOG) 139 reg_timer_rw_wd_ctrl wd_ctrl = { 0 }; 140 watchdog_key ^= ETRAX_WD_KEY_MASK; /* invert key, which is 7 bits */ 141 wd_ctrl.cnt = ETRAX_WD_CNT; 142 wd_ctrl.cmd = regk_timer_stop; 143 wd_ctrl.key = watchdog_key; 144 REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl); 145#endif 146} 147 148extern void show_registers(struct pt_regs *regs); 149 150void handle_watchdog_bite(struct pt_regs *regs) 151{ 152#if defined(CONFIG_ETRAX_WATCHDOG) 153 extern int cause_of_death; 154 155 oops_in_progress = 1; 156 printk(KERN_WARNING "Watchdog bite\n"); 157 158 /* Check if forced restart or unexpected watchdog */ 159 if (cause_of_death == 0xbedead) { 160#ifdef CONFIG_CRIS_MACH_ARTPEC3 161 /* There is a bug in Artpec-3 (voodoo TR 78) that requires 162 * us to go to lower frequency for the reset to be reliable 163 */ 164 reg_clkgen_rw_clk_ctrl ctrl = 165 REG_RD(clkgen, regi_clkgen, rw_clk_ctrl); 166 ctrl.pll = 0; 167 REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, ctrl); 168#endif 169 while(1); 170 } 171 172 /* Unexpected watchdog, stop the watchdog and dump registers. */ 173 stop_watchdog(); 174 printk(KERN_WARNING "Oops: bitten by watchdog\n"); 175 show_registers(regs); 176 oops_in_progress = 0; 177#ifndef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY 178 reset_watchdog(); 179#endif 180 while(1) /* nothing */; 181#endif 182} 183 184/* 185 * timer_interrupt() needs to keep up the real-time clock, 186 * as well as call the "do_timer()" routine every clocktick. 187 */ 188extern void cris_do_profile(struct pt_regs *regs); 189 190static inline irqreturn_t timer_interrupt(int irq, void *dev_id) 191{ 192 struct pt_regs *regs = get_irq_regs(); 193 int cpu = smp_processor_id(); 194 reg_timer_r_masked_intr masked_intr; 195 reg_timer_rw_ack_intr ack_intr = { 0 }; 196 197 /* Check if the timer interrupt is for us (a tmr0 int) */ 198 masked_intr = REG_RD(timer, timer_regs[cpu], r_masked_intr); 199 if (!masked_intr.tmr0) 200 return IRQ_NONE; 201 202 /* Acknowledge the timer irq. */ 203 ack_intr.tmr0 = 1; 204 REG_WR(timer, timer_regs[cpu], rw_ack_intr, ack_intr); 205 206 /* Reset watchdog otherwise it resets us! */ 207 reset_watchdog(); 208 209 /* Update statistics. */ 210 update_process_times(user_mode(regs)); 211 212 cris_do_profile(regs); /* Save profiling information */ 213 214 /* The master CPU is responsible for the time keeping. */ 215 if (cpu != 0) 216 return IRQ_HANDLED; 217 218 /* Call the real timer interrupt handler */ 219 write_seqlock(&xtime_lock); 220 do_timer(1); 221 write_sequnlock(&xtime_lock); 222 return IRQ_HANDLED; 223} 224 225/* Timer is IRQF_SHARED so drivers can add stuff to the timer irq chain. 226 * It needs to be IRQF_DISABLED to make the jiffies update work properly. 227 */ 228static struct irqaction irq_timer = { 229 .handler = timer_interrupt, 230 .flags = IRQF_SHARED | IRQF_DISABLED, 231 .name = "timer" 232}; 233 234void __init cris_timer_init(void) 235{ 236 int cpu = smp_processor_id(); 237 reg_timer_rw_tmr0_ctrl tmr0_ctrl = { 0 }; 238 reg_timer_rw_tmr0_div tmr0_div = TIMER0_DIV; 239 reg_timer_rw_intr_mask timer_intr_mask; 240 241 /* Setup the etrax timers. 242 * Base frequency is 100MHz, divider 1000000 -> 100 HZ 243 * We use timer0, so timer1 is free. 244 * The trig timer is used by the fasttimer API if enabled. 245 */ 246 247 tmr0_ctrl.op = regk_timer_ld; 248 tmr0_ctrl.freq = regk_timer_f100; 249 REG_WR(timer, timer_regs[cpu], rw_tmr0_div, tmr0_div); 250 REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl); /* Load */ 251 tmr0_ctrl.op = regk_timer_run; 252 REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl); /* Start */ 253 254 /* Enable the timer irq. */ 255 timer_intr_mask = REG_RD(timer, timer_regs[cpu], rw_intr_mask); 256 timer_intr_mask.tmr0 = 1; 257 REG_WR(timer, timer_regs[cpu], rw_intr_mask, timer_intr_mask); 258} 259 260void __init time_init(void) 261{ 262 reg_intr_vect_rw_mask intr_mask; 263 264 /* Probe for the RTC and read it if it exists. 265 * Before the RTC can be probed the loops_per_usec variable needs 266 * to be initialized to make usleep work. A better value for 267 * loops_per_usec is calculated by the kernel later once the 268 * clock has started. 269 */ 270 loops_per_usec = 50; 271 272 if(RTC_INIT() < 0) 273 have_rtc = 0; 274 else 275 have_rtc = 1; 276 277 /* Start CPU local timer. */ 278 cris_timer_init(); 279 280 /* Enable the timer irq in global config. */ 281 intr_mask = REG_RD_VECT(intr_vect, regi_irq, rw_mask, 1); 282 intr_mask.timer0 = 1; 283 REG_WR_VECT(intr_vect, regi_irq, rw_mask, 1, intr_mask); 284 285 /* Now actually register the timer irq handler that calls 286 * timer_interrupt(). */ 287 setup_irq(TIMER0_INTR_VECT, &irq_timer); 288 289 /* Enable watchdog if we should use one. */ 290 291#if defined(CONFIG_ETRAX_WATCHDOG) 292 printk(KERN_INFO "Enabling watchdog...\n"); 293 start_watchdog(); 294 295 /* If we use the hardware watchdog, we want to trap it as an NMI 296 * and dump registers before it resets us. For this to happen, we 297 * must set the "m" NMI enable flag (which once set, is unset only 298 * when an NMI is taken). */ 299 { 300 unsigned long flags; 301 local_save_flags(flags); 302 flags |= (1<<30); /* NMI M flag is at bit 30 */ 303 local_irq_restore(flags); 304 } 305#endif 306 307#ifdef CONFIG_CPU_FREQ 308 cpufreq_register_notifier(&cris_time_freq_notifier_block, 309 CPUFREQ_TRANSITION_NOTIFIER); 310#endif 311} 312 313#ifdef CONFIG_CPU_FREQ 314static int 315cris_time_freq_notifier(struct notifier_block *nb, unsigned long val, 316 void *data) 317{ 318 struct cpufreq_freqs *freqs = data; 319 if (val == CPUFREQ_POSTCHANGE) { 320 reg_timer_r_tmr0_data data; 321 reg_timer_rw_tmr0_div div = (freqs->new * 500) / HZ; 322 do { 323 data = REG_RD(timer, timer_regs[freqs->cpu], 324 r_tmr0_data); 325 } while (data > 20); 326 REG_WR(timer, timer_regs[freqs->cpu], rw_tmr0_div, div); 327 } 328 return 0; 329} 330#endif 331