1/* 2 * Copyright 2008 Analog Devices Inc. 3 * 4 * Licensed under the GPL-2 or later. 5 */ 6 7#ifndef _BF538_IRQ_H_ 8#define _BF538_IRQ_H_ 9 10/* 11 * Interrupt source definitions 12 Event Source Core Event Name 13 Core Emulation ** 14 Events (highest priority) EMU 0 15 Reset RST 1 16 NMI NMI 2 17 Exception EVX 3 18 Reserved -- 4 19 Hardware Error IVHW 5 20 Core Timer IVTMR 6 * 21 22 ..... 23 24 Software Interrupt 1 IVG14 31 25 Software Interrupt 2 -- 26 (lowest priority) IVG15 32 * 27*/ 28 29#define NR_PERI_INTS (2 * 32) 30 31/* The ABSTRACT IRQ definitions */ 32/** the first seven of the following are fixed, the rest you change if you need to **/ 33#define IRQ_EMU 0 /* Emulation */ 34#define IRQ_RST 1 /* reset */ 35#define IRQ_NMI 2 /* Non Maskable */ 36#define IRQ_EVX 3 /* Exception */ 37#define IRQ_UNUSED 4 /* - unused interrupt */ 38#define IRQ_HWERR 5 /* Hardware Error */ 39#define IRQ_CORETMR 6 /* Core timer */ 40 41#define BFIN_IRQ(x) ((x) + 7) 42 43#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ 44#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */ 45#define IRQ_PPI_ERROR BFIN_IRQ(2) /* PPI Error */ 46#define IRQ_SPORT0_ERROR BFIN_IRQ(3) /* SPORT0 Status */ 47#define IRQ_SPORT1_ERROR BFIN_IRQ(4) /* SPORT1 Status */ 48#define IRQ_SPI0_ERROR BFIN_IRQ(5) /* SPI0 Status */ 49#define IRQ_UART0_ERROR BFIN_IRQ(6) /* UART0 Status */ 50#define IRQ_RTC BFIN_IRQ(7) /* RTC */ 51#define IRQ_PPI BFIN_IRQ(8) /* DMA Channel 0 (PPI) */ 52#define IRQ_SPORT0_RX BFIN_IRQ(9) /* DMA 1 Channel (SPORT0 RX) */ 53#define IRQ_SPORT0_TX BFIN_IRQ(10) /* DMA 2 Channel (SPORT0 TX) */ 54#define IRQ_SPORT1_RX BFIN_IRQ(11) /* DMA 3 Channel (SPORT1 RX) */ 55#define IRQ_SPORT1_TX BFIN_IRQ(12) /* DMA 4 Channel (SPORT1 TX) */ 56#define IRQ_SPI0 BFIN_IRQ(13) /* DMA 5 Channel (SPI0) */ 57#define IRQ_UART0_RX BFIN_IRQ(14) /* DMA 6 Channel (UART0 RX) */ 58#define IRQ_UART0_TX BFIN_IRQ(15) /* DMA 7 Channel (UART0 TX) */ 59#define IRQ_TIMER0 BFIN_IRQ(16) /* Timer 0 */ 60#define IRQ_TIMER1 BFIN_IRQ(17) /* Timer 1 */ 61#define IRQ_TIMER2 BFIN_IRQ(18) /* Timer 2 */ 62#define IRQ_PORTF_INTA BFIN_IRQ(19) /* Port F Interrupt A */ 63#define IRQ_PORTF_INTB BFIN_IRQ(20) /* Port F Interrupt B */ 64#define IRQ_MEM0_DMA0 BFIN_IRQ(21) /* MDMA0 Stream 0 */ 65#define IRQ_MEM0_DMA1 BFIN_IRQ(22) /* MDMA0 Stream 1 */ 66#define IRQ_WATCH BFIN_IRQ(23) /* Software Watchdog Timer */ 67#define IRQ_DMA1_ERROR BFIN_IRQ(24) /* DMA Error 1 (generic) */ 68#define IRQ_SPORT2_ERROR BFIN_IRQ(25) /* SPORT2 Status */ 69#define IRQ_SPORT3_ERROR BFIN_IRQ(26) /* SPORT3 Status */ 70#define IRQ_SPI1_ERROR BFIN_IRQ(28) /* SPI1 Status */ 71#define IRQ_SPI2_ERROR BFIN_IRQ(29) /* SPI2 Status */ 72#define IRQ_UART1_ERROR BFIN_IRQ(30) /* UART1 Status */ 73#define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status */ 74#define IRQ_CAN_ERROR BFIN_IRQ(32) /* CAN Status (Error) Interrupt */ 75#define IRQ_SPORT2_RX BFIN_IRQ(33) /* DMA 8 Channel (SPORT2 RX) */ 76#define IRQ_SPORT2_TX BFIN_IRQ(34) /* DMA 9 Channel (SPORT2 TX) */ 77#define IRQ_SPORT3_RX BFIN_IRQ(35) /* DMA 10 Channel (SPORT3 RX) */ 78#define IRQ_SPORT3_TX BFIN_IRQ(36) /* DMA 11 Channel (SPORT3 TX) */ 79#define IRQ_SPI1 BFIN_IRQ(39) /* DMA 14 Channel (SPI1) */ 80#define IRQ_SPI2 BFIN_IRQ(40) /* DMA 15 Channel (SPI2) */ 81#define IRQ_UART1_RX BFIN_IRQ(41) /* DMA 16 Channel (UART1 RX) */ 82#define IRQ_UART1_TX BFIN_IRQ(42) /* DMA 17 Channel (UART1 TX) */ 83#define IRQ_UART2_RX BFIN_IRQ(43) /* DMA 18 Channel (UART2 RX) */ 84#define IRQ_UART2_TX BFIN_IRQ(44) /* DMA 19 Channel (UART2 TX) */ 85#define IRQ_TWI0 BFIN_IRQ(45) /* TWI0 */ 86#define IRQ_TWI1 BFIN_IRQ(46) /* TWI1 */ 87#define IRQ_CAN_RX BFIN_IRQ(47) /* CAN Receive Interrupt */ 88#define IRQ_CAN_TX BFIN_IRQ(48) /* CAN Transmit Interrupt */ 89#define IRQ_MEM1_DMA0 BFIN_IRQ(49) /* MDMA1 Stream 0 */ 90#define IRQ_MEM1_DMA1 BFIN_IRQ(50) /* MDMA1 Stream 1 */ 91 92#define SYS_IRQS BFIN_IRQ(63) /* 70 */ 93 94#define IRQ_PF0 71 95#define IRQ_PF1 72 96#define IRQ_PF2 73 97#define IRQ_PF3 74 98#define IRQ_PF4 75 99#define IRQ_PF5 76 100#define IRQ_PF6 77 101#define IRQ_PF7 78 102#define IRQ_PF8 79 103#define IRQ_PF9 80 104#define IRQ_PF10 81 105#define IRQ_PF11 82 106#define IRQ_PF12 83 107#define IRQ_PF13 84 108#define IRQ_PF14 85 109#define IRQ_PF15 86 110 111#define GPIO_IRQ_BASE IRQ_PF0 112 113#define NR_MACH_IRQS (IRQ_PF15 + 1) 114#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS) 115 116#define IVG7 7 117#define IVG8 8 118#define IVG9 9 119#define IVG10 10 120#define IVG11 11 121#define IVG12 12 122#define IVG13 13 123#define IVG14 14 124#define IVG15 15 125 126/* IAR0 BIT FIELDS */ 127#define IRQ_PLL_WAKEUP_POS 0 128#define IRQ_DMA0_ERROR_POS 4 129#define IRQ_PPI_ERROR_POS 8 130#define IRQ_SPORT0_ERROR_POS 12 131#define IRQ_SPORT1_ERROR_POS 16 132#define IRQ_SPI0_ERROR_POS 20 133#define IRQ_UART0_ERROR_POS 24 134#define IRQ_RTC_POS 28 135 136/* IAR1 BIT FIELDS */ 137#define IRQ_PPI_POS 0 138#define IRQ_SPORT0_RX_POS 4 139#define IRQ_SPORT0_TX_POS 8 140#define IRQ_SPORT1_RX_POS 12 141#define IRQ_SPORT1_TX_POS 16 142#define IRQ_SPI0_POS 20 143#define IRQ_UART0_RX_POS 24 144#define IRQ_UART0_TX_POS 28 145 146/* IAR2 BIT FIELDS */ 147#define IRQ_TIMER0_POS 0 148#define IRQ_TIMER1_POS 4 149#define IRQ_TIMER2_POS 8 150#define IRQ_PORTF_INTA_POS 12 151#define IRQ_PORTF_INTB_POS 16 152#define IRQ_MEM0_DMA0_POS 20 153#define IRQ_MEM0_DMA1_POS 24 154#define IRQ_WATCH_POS 28 155 156/* IAR3 BIT FIELDS */ 157#define IRQ_DMA1_ERROR_POS 0 158#define IRQ_SPORT2_ERROR_POS 4 159#define IRQ_SPORT3_ERROR_POS 8 160#define IRQ_SPI1_ERROR_POS 16 161#define IRQ_SPI2_ERROR_POS 20 162#define IRQ_UART1_ERROR_POS 24 163#define IRQ_UART2_ERROR_POS 28 164 165/* IAR4 BIT FIELDS */ 166#define IRQ_CAN_ERROR_POS 0 167#define IRQ_SPORT2_RX_POS 4 168#define IRQ_SPORT2_TX_POS 8 169#define IRQ_SPORT3_RX_POS 12 170#define IRQ_SPORT3_TX_POS 16 171#define IRQ_SPI1_POS 28 172 173/* IAR5 BIT FIELDS */ 174#define IRQ_SPI2_POS 0 175#define IRQ_UART1_RX_POS 4 176#define IRQ_UART1_TX_POS 8 177#define IRQ_UART2_RX_POS 12 178#define IRQ_UART2_TX_POS 16 179#define IRQ_TWI0_POS 20 180#define IRQ_TWI1_POS 24 181#define IRQ_CAN_RX_POS 28 182 183/* IAR6 BIT FIELDS */ 184#define IRQ_CAN_TX_POS 0 185#define IRQ_MEM1_DMA0_POS 4 186#define IRQ_MEM1_DMA1_POS 8 187#endif /* _BF538_IRQ_H_ */ 188