1/* 2 * Copyright 2004-2009 Analog Devices Inc. 3 * 2008-2009 Cambridge Signal Processing 4 * 2005 National ICT Australia (NICTA) 5 * Aidan Williams <aidan@nicta.com.au> 6 * 7 * Licensed under the GPL-2 or later. 8 */ 9 10#include <linux/device.h> 11#include <linux/platform_device.h> 12#include <linux/mtd/mtd.h> 13#include <linux/mtd/partitions.h> 14#include <linux/spi/spi.h> 15#include <linux/spi/flash.h> 16#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) 17#include <linux/usb/isp1362.h> 18#endif 19#include <linux/ata_platform.h> 20#include <linux/irq.h> 21#include <linux/interrupt.h> 22#include <linux/usb/sl811.h> 23#include <asm/dma.h> 24#include <asm/bfin5xx_spi.h> 25#include <asm/reboot.h> 26#include <asm/portmux.h> 27#include <linux/spi/ad7877.h> 28 29/* 30 * Name the Board for the /proc/cpuinfo 31 */ 32const char bfin_board_name[] = "CamSig Minotaur BF537"; 33 34#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE) 35static struct resource bfin_pcmcia_cf_resources[] = { 36 { 37 .start = 0x20310000, /* IO PORT */ 38 .end = 0x20312000, 39 .flags = IORESOURCE_MEM, 40 }, { 41 .start = 0x20311000, /* Attribute Memory */ 42 .end = 0x20311FFF, 43 .flags = IORESOURCE_MEM, 44 }, { 45 .start = IRQ_PF4, 46 .end = IRQ_PF4, 47 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, 48 }, { 49 .start = IRQ_PF6, /* Card Detect PF6 */ 50 .end = IRQ_PF6, 51 .flags = IORESOURCE_IRQ, 52 }, 53}; 54 55static struct platform_device bfin_pcmcia_cf_device = { 56 .name = "bfin_cf_pcmcia", 57 .id = -1, 58 .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources), 59 .resource = bfin_pcmcia_cf_resources, 60}; 61#endif 62 63#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) 64static struct platform_device rtc_device = { 65 .name = "rtc-bfin", 66 .id = -1, 67}; 68#endif 69 70#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) 71static struct platform_device bfin_mii_bus = { 72 .name = "bfin_mii_bus", 73}; 74 75static struct platform_device bfin_mac_device = { 76 .name = "bfin_mac", 77 .dev.platform_data = &bfin_mii_bus, 78}; 79#endif 80 81#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE) 82static struct resource net2272_bfin_resources[] = { 83 { 84 .start = 0x20300000, 85 .end = 0x20300000 + 0x100, 86 .flags = IORESOURCE_MEM, 87 }, { 88 .start = IRQ_PF7, 89 .end = IRQ_PF7, 90 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 91 }, 92}; 93 94static struct platform_device net2272_bfin_device = { 95 .name = "net2272", 96 .id = -1, 97 .num_resources = ARRAY_SIZE(net2272_bfin_resources), 98 .resource = net2272_bfin_resources, 99}; 100#endif 101 102#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) 103/* all SPI peripherals info goes here */ 104 105#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) 106 107/* Partition sizes */ 108#define FLASH_SIZE 0x00400000 109#define PSIZE_UBOOT 0x00030000 110#define PSIZE_INITRAMFS 0x00240000 111 112static struct mtd_partition bfin_spi_flash_partitions[] = { 113 { 114 .name = "bootloader(spi)", 115 .size = PSIZE_UBOOT, 116 .offset = 0x000000, 117 .mask_flags = MTD_CAP_ROM 118 }, { 119 .name = "initramfs(spi)", 120 .size = PSIZE_INITRAMFS, 121 .offset = PSIZE_UBOOT 122 }, { 123 .name = "opt(spi)", 124 .size = FLASH_SIZE - (PSIZE_UBOOT + PSIZE_INITRAMFS), 125 .offset = PSIZE_UBOOT + PSIZE_INITRAMFS, 126 } 127}; 128 129static struct flash_platform_data bfin_spi_flash_data = { 130 .name = "m25p80", 131 .parts = bfin_spi_flash_partitions, 132 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), 133 .type = "m25p64", 134}; 135 136/* SPI flash chip (m25p64) */ 137static struct bfin5xx_spi_chip spi_flash_chip_info = { 138 .enable_dma = 0, /* use dma transfer with this chip*/ 139 .bits_per_word = 8, 140}; 141#endif 142 143#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) 144static struct bfin5xx_spi_chip mmc_spi_chip_info = { 145 .enable_dma = 0, 146 .bits_per_word = 8, 147}; 148#endif 149 150static struct spi_board_info bfin_spi_board_info[] __initdata = { 151#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) 152 { 153 /* the modalias must be the same as spi device driver name */ 154 .modalias = "m25p80", /* Name of spi_driver for this device */ 155 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ 156 .bus_num = 0, /* Framework bus number */ 157 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/ 158 .platform_data = &bfin_spi_flash_data, 159 .controller_data = &spi_flash_chip_info, 160 .mode = SPI_MODE_3, 161 }, 162#endif 163 164#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) 165 { 166 .modalias = "mmc_spi", 167 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ 168 .bus_num = 0, 169 .chip_select = 5, 170 .controller_data = &mmc_spi_chip_info, 171 .mode = SPI_MODE_3, 172 }, 173#endif 174}; 175 176/* SPI controller data */ 177static struct bfin5xx_spi_master bfin_spi0_info = { 178 .num_chipselect = 8, 179 .enable_dma = 1, /* master has the ability to do dma transfer */ 180}; 181 182/* SPI (0) */ 183static struct resource bfin_spi0_resource[] = { 184 [0] = { 185 .start = SPI0_REGBASE, 186 .end = SPI0_REGBASE + 0xFF, 187 .flags = IORESOURCE_MEM, 188 }, 189 [1] = { 190 .start = CH_SPI, 191 .end = CH_SPI, 192 .flags = IORESOURCE_DMA, 193 }, 194 [2] = { 195 .start = IRQ_SPI, 196 .end = IRQ_SPI, 197 .flags = IORESOURCE_IRQ, 198 }, 199}; 200 201static struct platform_device bfin_spi0_device = { 202 .name = "bfin-spi", 203 .id = 0, /* Bus number */ 204 .num_resources = ARRAY_SIZE(bfin_spi0_resource), 205 .resource = bfin_spi0_resource, 206 .dev = { 207 .platform_data = &bfin_spi0_info, /* Passed to driver */ 208 }, 209}; 210#endif /* spi master and devices */ 211 212#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) 213#ifdef CONFIG_SERIAL_BFIN_UART0 214static struct resource bfin_uart0_resources[] = { 215 { 216 .start = UART0_THR, 217 .end = UART0_GCTL+2, 218 .flags = IORESOURCE_MEM, 219 }, 220 { 221 .start = IRQ_UART0_RX, 222 .end = IRQ_UART0_RX+1, 223 .flags = IORESOURCE_IRQ, 224 }, 225 { 226 .start = IRQ_UART0_ERROR, 227 .end = IRQ_UART0_ERROR, 228 .flags = IORESOURCE_IRQ, 229 }, 230 { 231 .start = CH_UART0_TX, 232 .end = CH_UART0_TX, 233 .flags = IORESOURCE_DMA, 234 }, 235 { 236 .start = CH_UART0_RX, 237 .end = CH_UART0_RX, 238 .flags = IORESOURCE_DMA, 239 }, 240}; 241 242unsigned short bfin_uart0_peripherals[] = { 243 P_UART0_TX, P_UART0_RX, 0 244}; 245 246static struct platform_device bfin_uart0_device = { 247 .name = "bfin-uart", 248 .id = 0, 249 .num_resources = ARRAY_SIZE(bfin_uart0_resources), 250 .resource = bfin_uart0_resources, 251 .dev = { 252 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ 253 }, 254}; 255#endif 256#ifdef CONFIG_SERIAL_BFIN_UART1 257static struct resource bfin_uart1_resources[] = { 258 { 259 .start = UART1_THR, 260 .end = UART1_GCTL+2, 261 .flags = IORESOURCE_MEM, 262 }, 263 { 264 .start = IRQ_UART1_RX, 265 .end = IRQ_UART1_RX+1, 266 .flags = IORESOURCE_IRQ, 267 }, 268 { 269 .start = IRQ_UART1_ERROR, 270 .end = IRQ_UART1_ERROR, 271 .flags = IORESOURCE_IRQ, 272 }, 273 { 274 .start = CH_UART1_TX, 275 .end = CH_UART1_TX, 276 .flags = IORESOURCE_DMA, 277 }, 278 { 279 .start = CH_UART1_RX, 280 .end = CH_UART1_RX, 281 .flags = IORESOURCE_DMA, 282 }, 283}; 284 285unsigned short bfin_uart1_peripherals[] = { 286 P_UART1_TX, P_UART1_RX, 0 287}; 288 289static struct platform_device bfin_uart1_device = { 290 .name = "bfin-uart", 291 .id = 1, 292 .num_resources = ARRAY_SIZE(bfin_uart1_resources), 293 .resource = bfin_uart1_resources, 294 .dev = { 295 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */ 296 }, 297}; 298#endif 299#endif 300 301#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) 302#ifdef CONFIG_BFIN_SIR0 303static struct resource bfin_sir0_resources[] = { 304 { 305 .start = 0xFFC00400, 306 .end = 0xFFC004FF, 307 .flags = IORESOURCE_MEM, 308 }, 309 { 310 .start = IRQ_UART0_RX, 311 .end = IRQ_UART0_RX+1, 312 .flags = IORESOURCE_IRQ, 313 }, 314 { 315 .start = CH_UART0_RX, 316 .end = CH_UART0_RX+1, 317 .flags = IORESOURCE_DMA, 318 }, 319}; 320 321static struct platform_device bfin_sir0_device = { 322 .name = "bfin_sir", 323 .id = 0, 324 .num_resources = ARRAY_SIZE(bfin_sir0_resources), 325 .resource = bfin_sir0_resources, 326}; 327#endif 328#ifdef CONFIG_BFIN_SIR1 329static struct resource bfin_sir1_resources[] = { 330 { 331 .start = 0xFFC02000, 332 .end = 0xFFC020FF, 333 .flags = IORESOURCE_MEM, 334 }, 335 { 336 .start = IRQ_UART1_RX, 337 .end = IRQ_UART1_RX+1, 338 .flags = IORESOURCE_IRQ, 339 }, 340 { 341 .start = CH_UART1_RX, 342 .end = CH_UART1_RX+1, 343 .flags = IORESOURCE_DMA, 344 }, 345}; 346 347static struct platform_device bfin_sir1_device = { 348 .name = "bfin_sir", 349 .id = 1, 350 .num_resources = ARRAY_SIZE(bfin_sir1_resources), 351 .resource = bfin_sir1_resources, 352}; 353#endif 354#endif 355 356#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) 357static struct resource bfin_twi0_resource[] = { 358 [0] = { 359 .start = TWI0_REGBASE, 360 .end = TWI0_REGBASE + 0xFF, 361 .flags = IORESOURCE_MEM, 362 }, 363 [1] = { 364 .start = IRQ_TWI, 365 .end = IRQ_TWI, 366 .flags = IORESOURCE_IRQ, 367 }, 368}; 369 370static struct platform_device i2c_bfin_twi_device = { 371 .name = "i2c-bfin-twi", 372 .id = 0, 373 .num_resources = ARRAY_SIZE(bfin_twi0_resource), 374 .resource = bfin_twi0_resource, 375}; 376#endif 377 378#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) 379#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART 380static struct resource bfin_sport0_uart_resources[] = { 381 { 382 .start = SPORT0_TCR1, 383 .end = SPORT0_MRCS3+4, 384 .flags = IORESOURCE_MEM, 385 }, 386 { 387 .start = IRQ_SPORT0_RX, 388 .end = IRQ_SPORT0_RX+1, 389 .flags = IORESOURCE_IRQ, 390 }, 391 { 392 .start = IRQ_SPORT0_ERROR, 393 .end = IRQ_SPORT0_ERROR, 394 .flags = IORESOURCE_IRQ, 395 }, 396}; 397 398unsigned short bfin_sport0_peripherals[] = { 399 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, 400 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 401}; 402 403static struct platform_device bfin_sport0_uart_device = { 404 .name = "bfin-sport-uart", 405 .id = 0, 406 .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources), 407 .resource = bfin_sport0_uart_resources, 408 .dev = { 409 .platform_data = &bfin_sport0_peripherals, /* Passed to driver */ 410 }, 411}; 412#endif 413#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART 414static struct resource bfin_sport1_uart_resources[] = { 415 { 416 .start = SPORT1_TCR1, 417 .end = SPORT1_MRCS3+4, 418 .flags = IORESOURCE_MEM, 419 }, 420 { 421 .start = IRQ_SPORT1_RX, 422 .end = IRQ_SPORT1_RX+1, 423 .flags = IORESOURCE_IRQ, 424 }, 425 { 426 .start = IRQ_SPORT1_ERROR, 427 .end = IRQ_SPORT1_ERROR, 428 .flags = IORESOURCE_IRQ, 429 }, 430}; 431 432unsigned short bfin_sport1_peripherals[] = { 433 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, 434 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 435}; 436 437static struct platform_device bfin_sport1_uart_device = { 438 .name = "bfin-sport-uart", 439 .id = 1, 440 .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources), 441 .resource = bfin_sport1_uart_resources, 442 .dev = { 443 .platform_data = &bfin_sport1_peripherals, /* Passed to driver */ 444 }, 445}; 446#endif 447#endif 448 449static struct platform_device *minotaur_devices[] __initdata = { 450#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE) 451 &bfin_pcmcia_cf_device, 452#endif 453 454#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) 455 &rtc_device, 456#endif 457 458#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) 459 &bfin_mii_bus, 460 &bfin_mac_device, 461#endif 462 463#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE) 464 &net2272_bfin_device, 465#endif 466 467#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) 468 &bfin_spi0_device, 469#endif 470 471#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) 472#ifdef CONFIG_SERIAL_BFIN_UART0 473 &bfin_uart0_device, 474#endif 475#ifdef CONFIG_SERIAL_BFIN_UART1 476 &bfin_uart1_device, 477#endif 478#endif 479 480#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) 481#ifdef CONFIG_BFIN_SIR0 482 &bfin_sir0_device, 483#endif 484#ifdef CONFIG_BFIN_SIR1 485 &bfin_sir1_device, 486#endif 487#endif 488 489#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) 490 &i2c_bfin_twi_device, 491#endif 492 493#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) 494#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART 495 &bfin_sport0_uart_device, 496#endif 497#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART 498 &bfin_sport1_uart_device, 499#endif 500#endif 501 502}; 503 504static int __init minotaur_init(void) 505{ 506 printk(KERN_INFO "%s(): registering device resources\n", __func__); 507 platform_add_devices(minotaur_devices, ARRAY_SIZE(minotaur_devices)); 508#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) 509 spi_register_board_info(bfin_spi_board_info, 510 ARRAY_SIZE(bfin_spi_board_info)); 511#endif 512 513 return 0; 514} 515 516arch_initcall(minotaur_init); 517 518static struct platform_device *minotaur_early_devices[] __initdata = { 519#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) 520#ifdef CONFIG_SERIAL_BFIN_UART0 521 &bfin_uart0_device, 522#endif 523#ifdef CONFIG_SERIAL_BFIN_UART1 524 &bfin_uart1_device, 525#endif 526#endif 527 528#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE) 529#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART 530 &bfin_sport0_uart_device, 531#endif 532#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART 533 &bfin_sport1_uart_device, 534#endif 535#endif 536}; 537 538void __init native_machine_early_platform_add_devices(void) 539{ 540 printk(KERN_INFO "register early platform devices\n"); 541 early_platform_add_devices(minotaur_early_devices, 542 ARRAY_SIZE(minotaur_early_devices)); 543} 544 545void native_machine_restart(char *cmd) 546{ 547 if ((bfin_read_SYSCR() & 0x7) == 0x3) 548 bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS); 549} 550