1/* 2 * DO NOT EDIT THIS FILE 3 * This file is under version control at 4 * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/ 5 * and can be replaced with that version at any time 6 * DO NOT EDIT THIS FILE 7 * 8 * Copyright 2004-2010 Analog Devices Inc. 9 * Licensed under the ADI BSD license. 10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd 11 */ 12 13/* This file should be up to date with: 14 * - Revision E, 09/18/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List 15 */ 16 17#ifndef _MACH_ANOMALY_H_ 18#define _MACH_ANOMALY_H_ 19 20/* We do not support 0.1 or 0.2 silicon - sorry */ 21#if __SILICON_REVISION__ < 3 22# error will not work on BF533 silicon version 0.0, 0.1, or 0.2 23#endif 24 25#if defined(__ADSPBF531__) 26# define ANOMALY_BF531 1 27#else 28# define ANOMALY_BF531 0 29#endif 30#if defined(__ADSPBF532__) 31# define ANOMALY_BF532 1 32#else 33# define ANOMALY_BF532 0 34#endif 35#if defined(__ADSPBF533__) 36# define ANOMALY_BF533 1 37#else 38# define ANOMALY_BF533 0 39#endif 40 41/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ 42#define ANOMALY_05000074 (1) 43/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */ 44#define ANOMALY_05000099 (__SILICON_REVISION__ < 5) 45/* Watchpoint Status Register (WPSTAT) Bits Are Set on Every Corresponding Match */ 46#define ANOMALY_05000105 (__SILICON_REVISION__ > 2) 47/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ 48#define ANOMALY_05000119 (1) 49/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ 50#define ANOMALY_05000122 (1) 51/* Instruction DMA Can Cause Data Cache Fills to Fail (Boot Implications) */ 52#define ANOMALY_05000158 (__SILICON_REVISION__ < 5) 53/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */ 54#define ANOMALY_05000166 (1) 55/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */ 56#define ANOMALY_05000167 (1) 57/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */ 58#define ANOMALY_05000179 (__SILICON_REVISION__ < 5) 59/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ 60#define ANOMALY_05000180 (1) 61/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */ 62#define ANOMALY_05000183 (__SILICON_REVISION__ < 4) 63/* False Protection Exceptions when Speculative Fetch Is Cancelled */ 64#define ANOMALY_05000189 (__SILICON_REVISION__ < 4) 65/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */ 66#define ANOMALY_05000193 (__SILICON_REVISION__ < 4) 67/* Restarting SPORT in Specific Modes May Cause Data Corruption */ 68#define ANOMALY_05000194 (__SILICON_REVISION__ < 4) 69/* Failing MMR Accesses when Preceding Memory Read Stalls */ 70#define ANOMALY_05000198 (__SILICON_REVISION__ < 5) 71/* Current DMA Address Shows Wrong Value During Carry Fix */ 72#define ANOMALY_05000199 (__SILICON_REVISION__ < 4) 73/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */ 74#define ANOMALY_05000200 (__SILICON_REVISION__ == 3 || __SILICON_REVISION__ == 4) 75/* Receive Frame Sync Not Ignored During Active Frames in SPORT Multi-Channel Mode */ 76#define ANOMALY_05000201 (__SILICON_REVISION__ == 3) 77/* Possible Infinite Stall with Specific Dual-DAG Situation */ 78#define ANOMALY_05000202 (__SILICON_REVISION__ < 5) 79/* Specific Sequence That Can Cause DMA Error or DMA Stopping */ 80#define ANOMALY_05000203 (__SILICON_REVISION__ < 4) 81/* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */ 82#define ANOMALY_05000204 (__SILICON_REVISION__ < 4 && ANOMALY_BF533) 83/* Recovery from "Brown-Out" Condition */ 84#define ANOMALY_05000207 (__SILICON_REVISION__ < 4) 85/* VSTAT Status Bit in PLL_STAT Register Is Not Functional */ 86#define ANOMALY_05000208 (1) 87/* Speed Path in Computational Unit Affects Certain Instructions */ 88#define ANOMALY_05000209 (__SILICON_REVISION__ < 4) 89/* UART TX Interrupt Masked Erroneously */ 90#define ANOMALY_05000215 (__SILICON_REVISION__ < 5) 91/* NMI Event at Boot Time Results in Unpredictable State */ 92#define ANOMALY_05000219 (1) 93/* Incorrect Pulse-Width of UART Start Bit */ 94#define ANOMALY_05000225 (__SILICON_REVISION__ < 5) 95/* Scratchpad Memory Bank Reads May Return Incorrect Data */ 96#define ANOMALY_05000227 (__SILICON_REVISION__ < 5) 97/* SPI Slave Boot Mode Modifies Registers from Reset Value */ 98#define ANOMALY_05000229 (1) 99/* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */ 100#define ANOMALY_05000230 (__SILICON_REVISION__ < 5) 101/* UART STB Bit Incorrectly Affects Receiver Setting */ 102#define ANOMALY_05000231 (__SILICON_REVISION__ < 5) 103/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */ 104#define ANOMALY_05000233 (__SILICON_REVISION__ < 6) 105/* Incorrect Revision Number in DSPID Register */ 106#define ANOMALY_05000234 (__SILICON_REVISION__ == 4) 107/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */ 108#define ANOMALY_05000242 (__SILICON_REVISION__ < 5) 109/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ 110#define ANOMALY_05000244 (__SILICON_REVISION__ < 5) 111/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ 112#define ANOMALY_05000245 (1) 113/* Data CPLBs Should Prevent False Hardware Errors */ 114#define ANOMALY_05000246 (__SILICON_REVISION__ < 5) 115/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ 116#define ANOMALY_05000250 (__SILICON_REVISION__ == 4) 117/* Maximum External Clock Speed for Timers */ 118#define ANOMALY_05000253 (__SILICON_REVISION__ < 5) 119/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ 120#define ANOMALY_05000254 (__SILICON_REVISION__ > 4) 121/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */ 122#define ANOMALY_05000255 (__SILICON_REVISION__ < 5) 123/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */ 124#define ANOMALY_05000257 (__SILICON_REVISION__ < 5) 125/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */ 126#define ANOMALY_05000258 (__SILICON_REVISION__ < 5) 127/* ICPLB_STATUS MMR Register May Be Corrupted */ 128#define ANOMALY_05000260 (__SILICON_REVISION__ < 5) 129/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */ 130#define ANOMALY_05000261 (__SILICON_REVISION__ < 5) 131/* Stores To Data Cache May Be Lost */ 132#define ANOMALY_05000262 (__SILICON_REVISION__ < 5) 133/* Hardware Loop Corrupted When Taking an ICPLB Exception */ 134#define ANOMALY_05000263 (__SILICON_REVISION__ < 5) 135/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */ 136#define ANOMALY_05000264 (__SILICON_REVISION__ < 5) 137/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ 138#define ANOMALY_05000265 (1) 139/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */ 140#define ANOMALY_05000269 (__SILICON_REVISION__ < 5) 141/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ 142#define ANOMALY_05000270 (__SILICON_REVISION__ < 5) 143/* Spontaneous Reset of Internal Voltage Regulator */ 144#define ANOMALY_05000271 (__SILICON_REVISION__ == 3) 145/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ 146#define ANOMALY_05000272 (1) 147/* Writes to Synchronous SDRAM Memory May Be Lost */ 148#define ANOMALY_05000273 (__SILICON_REVISION__ < 6) 149/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */ 150#define ANOMALY_05000276 (1) 151/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */ 152#define ANOMALY_05000277 (__SILICON_REVISION__ < 6) 153/* Disabling Peripherals with DMA Running May Cause DMA System Instability */ 154#define ANOMALY_05000278 (__SILICON_REVISION__ < 6) 155/* False Hardware Error Exception when ISR Context Is Not Restored */ 156#define ANOMALY_05000281 (__SILICON_REVISION__ < 6) 157/* Memory DMA Corruption with 32-Bit Data and Traffic Control */ 158#define ANOMALY_05000282 (__SILICON_REVISION__ < 6) 159/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */ 160#define ANOMALY_05000283 (__SILICON_REVISION__ < 6) 161/* SPORTs May Receive Bad Data If FIFOs Fill Up */ 162#define ANOMALY_05000288 (__SILICON_REVISION__ < 6) 163/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ 164#define ANOMALY_05000301 (__SILICON_REVISION__ < 6) 165/* SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly */ 166#define ANOMALY_05000302 (__SILICON_REVISION__ < 5) 167/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */ 168#define ANOMALY_05000305 (__SILICON_REVISION__ < 5) 169/* ALT_TIMING Bit in PPI_CONTROL Register Is Not Functional */ 170#define ANOMALY_05000306 (__SILICON_REVISION__ < 5) 171/* SCKELOW Bit Does Not Maintain State Through Hibernate */ 172#define ANOMALY_05000307 (1) /* note: brokenness is noted in documentation, not anomaly sheet */ 173/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ 174#define ANOMALY_05000310 (1) 175/* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */ 176#define ANOMALY_05000311 (__SILICON_REVISION__ < 6) 177/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ 178#define ANOMALY_05000312 (__SILICON_REVISION__ < 6) 179/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ 180#define ANOMALY_05000313 (__SILICON_REVISION__ < 6) 181/* Killed System MMR Write Completes Erroneously on Next System MMR Access */ 182#define ANOMALY_05000315 (__SILICON_REVISION__ < 6) 183/* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */ 184#define ANOMALY_05000319 ((ANOMALY_BF531 || ANOMALY_BF532) && __SILICON_REVISION__ < 6) 185/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ 186#define ANOMALY_05000357 (__SILICON_REVISION__ < 6) 187/* UART Break Signal Issues */ 188#define ANOMALY_05000363 (__SILICON_REVISION__ < 5) 189/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ 190#define ANOMALY_05000366 (1) 191/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ 192#define ANOMALY_05000371 (__SILICON_REVISION__ < 6) 193/* PPI Does Not Start Properly In Specific Mode */ 194#define ANOMALY_05000400 (__SILICON_REVISION__ == 5) 195/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ 196#define ANOMALY_05000402 (__SILICON_REVISION__ == 5) 197/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ 198#define ANOMALY_05000403 (1) 199/* Speculative Fetches Can Cause Undesired External FIFO Operations */ 200#define ANOMALY_05000416 (1) 201/* Multichannel SPORT Channel Misalignment Under Specific Configuration */ 202#define ANOMALY_05000425 (1) 203/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ 204#define ANOMALY_05000426 (1) 205/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ 206#define ANOMALY_05000443 (1) 207/* False Hardware Error when RETI Points to Invalid Memory */ 208#define ANOMALY_05000461 (1) 209/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ 210#define ANOMALY_05000473 (1) 211/* Possible Lockup Condition whem Modifying PLL from External Memory */ 212#define ANOMALY_05000475 (1) 213/* TESTSET Instruction Cannot Be Interrupted */ 214#define ANOMALY_05000477 (1) 215/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ 216#define ANOMALY_05000481 (1) 217/* IFLUSH sucks at life */ 218#define ANOMALY_05000491 (1) 219 220/* These anomalies have been "phased" out of analog.com anomaly sheets and are 221 * here to show running on older silicon just isn't feasible. 222 */ 223 224/* Internal voltage regulator can't be modified via register writes */ 225#define ANOMALY_05000066 (__SILICON_REVISION__ < 2) 226/* Watchpoints (Hardware Breakpoints) are not supported */ 227#define ANOMALY_05000067 (__SILICON_REVISION__ < 3) 228/* SDRAM PSSE bit cannot be set again after SDRAM Powerup */ 229#define ANOMALY_05000070 (__SILICON_REVISION__ < 2) 230/* Writing FIO_DIR can corrupt a programmable flag's data */ 231#define ANOMALY_05000079 (__SILICON_REVISION__ < 2) 232/* Timer Auto-Baud Mode requires the UART clock to be enabled. */ 233#define ANOMALY_05000086 (__SILICON_REVISION__ < 2) 234/* Internal Clocking Modes on SPORT0 not supported */ 235#define ANOMALY_05000088 (__SILICON_REVISION__ < 2) 236/* Internal voltage regulator does not wake up from an RTC wakeup */ 237#define ANOMALY_05000092 (__SILICON_REVISION__ < 2) 238/* The IFLUSH Instruction Must Be Preceded by a CSYNC Instruction */ 239#define ANOMALY_05000093 (__SILICON_REVISION__ < 2) 240/* Vectoring to instruction that is being filled into the i-cache may cause erroneous behavior */ 241#define ANOMALY_05000095 (__SILICON_REVISION__ < 2) 242/* PREFETCH, FLUSH, and FLUSHINV Instructions Must Be Followed by a CSYNC Instruction */ 243#define ANOMALY_05000096 (__SILICON_REVISION__ < 2) 244/* Performance Monitor 0 and 1 are swapped when monitoring memory events */ 245#define ANOMALY_05000097 (__SILICON_REVISION__ < 2) 246/* 32-bit SPORT DMA will be word reversed */ 247#define ANOMALY_05000098 (__SILICON_REVISION__ < 2) 248/* Incorrect status in the UART_IIR register */ 249#define ANOMALY_05000100 (__SILICON_REVISION__ < 2) 250/* Reading X_MODIFY or Y_MODIFY while DMA channel is active */ 251#define ANOMALY_05000101 (__SILICON_REVISION__ < 2) 252/* Descriptor MemDMA may lock up with 32-bit transfers or if transfers span 64KB buffers */ 253#define ANOMALY_05000102 (__SILICON_REVISION__ < 2) 254/* Incorrect Value Written to the Cycle Counters */ 255#define ANOMALY_05000103 (__SILICON_REVISION__ < 2) 256/* Stores to L1 Data Memory Incorrect when a Specific Sequence Is Followed */ 257#define ANOMALY_05000104 (__SILICON_REVISION__ < 2) 258/* Programmable Flag (PF3) functionality not supported in all PPI modes */ 259#define ANOMALY_05000106 (__SILICON_REVISION__ < 2) 260/* Data store can be lost when targeting a cache line fill */ 261#define ANOMALY_05000107 (__SILICON_REVISION__ < 2) 262/* Reserved Bits in SYSCFG Register Not Set at Power-On */ 263#define ANOMALY_05000109 (__SILICON_REVISION__ < 3) 264/* Infinite Core Stall */ 265#define ANOMALY_05000114 (__SILICON_REVISION__ < 2) 266/* PPI_FSx may glitch when generated by the on chip Timers. */ 267#define ANOMALY_05000115 (__SILICON_REVISION__ < 2) 268/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */ 269#define ANOMALY_05000116 (__SILICON_REVISION__ < 3) 270/* DTEST registers allow access to Data Cache when DTEST_COMMAND< 14 >= 0 */ 271#define ANOMALY_05000117 (__SILICON_REVISION__ < 2) 272/* Booting from an 8-bit or 24-bit Addressable SPI device is not supported */ 273#define ANOMALY_05000118 (__SILICON_REVISION__ < 2) 274/* DTEST_COMMAND Initiated Memory Access May Be Incorrect If Data Cache or DMA Is Active */ 275#define ANOMALY_05000123 (__SILICON_REVISION__ < 3) 276/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */ 277#define ANOMALY_05000124 (__SILICON_REVISION__ < 3) 278/* Erroneous Exception when Enabling Cache */ 279#define ANOMALY_05000125 (__SILICON_REVISION__ < 3) 280/* SPI clock polarity and phase bits incorrect during booting */ 281#define ANOMALY_05000126 (__SILICON_REVISION__ < 3) 282/* DMEM_CONTROL<12> Is Not Set on Reset */ 283#define ANOMALY_05000137 (__SILICON_REVISION__ < 3) 284/* SPI boot will not complete if there is a zero fill block in the loader file */ 285#define ANOMALY_05000138 (__SILICON_REVISION__ == 2) 286/* TIMERx_CONFIG[5] must be set for PPI in GP output mode with internal Frame Syncs */ 287#define ANOMALY_05000139 (__SILICON_REVISION__ < 2) 288/* Allowing the SPORT RX FIFO to fill will cause an overflow */ 289#define ANOMALY_05000140 (__SILICON_REVISION__ < 3) 290/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */ 291#define ANOMALY_05000141 (__SILICON_REVISION__ < 3) 292/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */ 293#define ANOMALY_05000142 (__SILICON_REVISION__ < 3) 294/* A read from external memory may return a wrong value with data cache enabled */ 295#define ANOMALY_05000143 (__SILICON_REVISION__ < 3) 296/* DMA and TESTSET conflict when both are accessing external memory */ 297#define ANOMALY_05000144 (__SILICON_REVISION__ < 3) 298/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */ 299#define ANOMALY_05000145 (__SILICON_REVISION__ < 3) 300/* MDMA may lose the first few words of a descriptor chain */ 301#define ANOMALY_05000146 (__SILICON_REVISION__ < 3) 302/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */ 303#define ANOMALY_05000147 (__SILICON_REVISION__ < 3) 304/* When booting from 16-bit asynchronous memory, the upper 8 bits of each word must be 0x00 */ 305#define ANOMALY_05000148 (__SILICON_REVISION__ < 3) 306/* Frame Delay in SPORT Multichannel Mode */ 307#define ANOMALY_05000153 (__SILICON_REVISION__ < 3) 308/* SPORT TFS signal stays active in multichannel mode outside of valid channels */ 309#define ANOMALY_05000154 (__SILICON_REVISION__ < 3) 310/* Timer1 can not be used for PWMOUT mode when a certain PPI mode is in use */ 311#define ANOMALY_05000155 (__SILICON_REVISION__ < 3) 312/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */ 313#define ANOMALY_05000157 (__SILICON_REVISION__ < 3) 314/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */ 315#define ANOMALY_05000163 (__SILICON_REVISION__ < 3) 316/* Undefined Behavior when Power-Up Sequence Is Issued to SDRAM during Auto-Refresh */ 317#define ANOMALY_05000168 (__SILICON_REVISION__ < 3) 318/* DATA CPLB Page Miss Can Result in Lost Write-Through Data Cache Writes */ 319#define ANOMALY_05000169 (__SILICON_REVISION__ < 3) 320/* DMA vs Core accesses to external memory */ 321#define ANOMALY_05000173 (__SILICON_REVISION__ < 3) 322/* Cache Fill Buffer Data lost */ 323#define ANOMALY_05000174 (__SILICON_REVISION__ < 3) 324/* Overlapping Sequencer and Memory Stalls */ 325#define ANOMALY_05000175 (__SILICON_REVISION__ < 3) 326/* Overflow Bit Asserted when Multiplication of -1 by -1 Followed by Accumulator Saturation */ 327#define ANOMALY_05000176 (__SILICON_REVISION__ < 3) 328/* Disabling the PPI Resets the PPI Configuration Registers */ 329#define ANOMALY_05000181 (__SILICON_REVISION__ < 3) 330/* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */ 331#define ANOMALY_05000185 (__SILICON_REVISION__ < 3) 332/* PPI does not invert the Driving PPICLK edge in Transmit Modes */ 333#define ANOMALY_05000191 (__SILICON_REVISION__ < 3) 334/* In PPI Transmit Modes with External Frame Syncs POLC bit must be set to 1 */ 335#define ANOMALY_05000192 (__SILICON_REVISION__ < 3) 336/* Internal Voltage Regulator may not start up */ 337#define ANOMALY_05000206 (__SILICON_REVISION__ < 3) 338 339/* Anomalies that don't exist on this proc */ 340#define ANOMALY_05000120 (0) 341#define ANOMALY_05000149 (0) 342#define ANOMALY_05000171 (0) 343#define ANOMALY_05000182 (0) 344#define ANOMALY_05000220 (0) 345#define ANOMALY_05000248 (0) 346#define ANOMALY_05000266 (0) 347#define ANOMALY_05000274 (0) 348#define ANOMALY_05000287 (0) 349#define ANOMALY_05000323 (0) 350#define ANOMALY_05000353 (1) 351#define ANOMALY_05000362 (1) 352#define ANOMALY_05000364 (0) 353#define ANOMALY_05000380 (0) 354#define ANOMALY_05000386 (1) 355#define ANOMALY_05000389 (0) 356#define ANOMALY_05000412 (0) 357#define ANOMALY_05000430 (0) 358#define ANOMALY_05000432 (0) 359#define ANOMALY_05000435 (0) 360#define ANOMALY_05000447 (0) 361#define ANOMALY_05000448 (0) 362#define ANOMALY_05000456 (0) 363#define ANOMALY_05000450 (0) 364#define ANOMALY_05000465 (0) 365#define ANOMALY_05000467 (0) 366#define ANOMALY_05000474 (0) 367#define ANOMALY_05000485 (0) 368 369#endif 370