1/* 2 * arch/arm/plat-spear/include/plat/clock.h 3 * 4 * Clock framework definitions for SPEAr platform 5 * 6 * Copyright (C) 2009 ST Microelectronics 7 * Viresh Kumar<viresh.kumar@st.com> 8 * 9 * This file is licensed under the terms of the GNU General Public 10 * License version 2. This program is licensed "as is" without any 11 * warranty of any kind, whether express or implied. 12 */ 13 14#ifndef __PLAT_CLOCK_H 15#define __PLAT_CLOCK_H 16 17#include <linux/list.h> 18#include <asm/clkdev.h> 19#include <linux/types.h> 20 21/* clk structure flags */ 22#define ALWAYS_ENABLED (1 << 0) /* clock always enabled */ 23#define RESET_TO_ENABLE (1 << 1) /* reset register bit to enable clk */ 24 25/** 26 * struct clkops - clock operations 27 * @enable: pointer to clock enable function 28 * @disable: pointer to clock disable function 29 */ 30struct clkops { 31 int (*enable) (struct clk *); 32 void (*disable) (struct clk *); 33}; 34 35/** 36 * struct pclk_info - parents info 37 * @pclk: pointer to parent clk 38 * @pclk_mask: value to be written for selecting this parent 39 * @scalable: Is parent scalable (1 - YES, 0 - NO) 40 */ 41struct pclk_info { 42 struct clk *pclk; 43 u8 pclk_mask; 44 u8 scalable; 45}; 46 47/** 48 * struct pclk_sel - parents selection configuration 49 * @pclk_info: pointer to array of parent clock info 50 * @pclk_count: number of parents 51 * @pclk_sel_reg: register for selecting a parent 52 * @pclk_sel_mask: mask for selecting parent (can be used to clear bits also) 53 */ 54struct pclk_sel { 55 struct pclk_info *pclk_info; 56 u8 pclk_count; 57 unsigned int *pclk_sel_reg; 58 unsigned int pclk_sel_mask; 59}; 60 61/** 62 * struct clk - clock structure 63 * @usage_count: num of users who enabled this clock 64 * @flags: flags for clock properties 65 * @rate: programmed clock rate in Hz 66 * @en_reg: clk enable/disable reg 67 * @en_reg_bit: clk enable/disable bit 68 * @ops: clk enable/disable ops - generic_clkops selected if NULL 69 * @recalc: pointer to clock rate recalculate function 70 * @pclk: current parent clk 71 * @pclk_sel: pointer to parent selection structure 72 * @pclk_sel_shift: register shift for selecting parent of this clock 73 * @children: list for childrens or this clock 74 * @sibling: node for list of clocks having same parents 75 * @private_data: clock specific private data 76 */ 77struct clk { 78 unsigned int usage_count; 79 unsigned int flags; 80 unsigned long rate; 81 unsigned int *en_reg; 82 u8 en_reg_bit; 83 const struct clkops *ops; 84 void (*recalc) (struct clk *); 85 86 struct clk *pclk; 87 struct pclk_sel *pclk_sel; 88 unsigned int pclk_sel_shift; 89 90 struct list_head children; 91 struct list_head sibling; 92 void *private_data; 93}; 94 95/* pll configuration structure */ 96struct pll_clk_config { 97 unsigned int *mode_reg; 98 unsigned int *cfg_reg; 99}; 100 101/* ahb and apb bus configuration structure */ 102struct bus_clk_config { 103 unsigned int *reg; 104 unsigned int mask; 105 unsigned int shift; 106}; 107 108/* 109 * Aux clk configuration structure: applicable to GPT, UART and FIRDA 110 */ 111struct aux_clk_config { 112 unsigned int *synth_reg; 113}; 114 115/* platform specific clock functions */ 116void clk_register(struct clk_lookup *cl); 117void recalc_root_clocks(void); 118 119/* clock recalc functions */ 120void follow_parent(struct clk *clk); 121void pll1_clk_recalc(struct clk *clk); 122void bus_clk_recalc(struct clk *clk); 123void gpt_clk_recalc(struct clk *clk); 124void aux_clk_recalc(struct clk *clk); 125 126#endif /* __PLAT_CLOCK_H */ 127