1/***************************************************************************** 2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. 3* 4* Unless you and Broadcom execute a separate written software license 5* agreement governing use of this software, this software is licensed to you 6* under the terms of the GNU General Public License version 2, available at 7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). 8* 9* Notwithstanding the above, under no circumstances may you combine this 10* software in any way with any other Broadcom software provided under a 11* license other than the GPL, without Broadcom's express prior written 12* consent. 13*****************************************************************************/ 14 15#include <linux/linkage.h> 16#include <linux/init.h> 17 18 __INIT 19 20/* 21 * v7_l1_cache_invalidate 22 * 23 * Invalidate contents of L1 cache without flushing its contents 24 * into outer cache and memory. This is needed when the contents 25 * of the cache are unpredictable after power-up. 26 * 27 * corrupts r0-r6 28 */ 29 30ENTRY(v7_l1_cache_invalidate) 31 mov r0, #0 32 mcr p15, 2, r0, c0, c0, 0 @ set cache level to 1 33 mrc p15, 1, r0, c0, c0, 0 @ read CLIDR 34 35 ldr r1, =0x7fff 36 and r2, r1, r0, lsr #13 @ get max # of index size 37 38 ldr r1, =0x3ff 39 and r3, r1, r0, lsr #3 @ NumWays - 1 40 add r2, r2, #1 @ NumSets 41 42 and r0, r0, #0x7 43 add r0, r0, #4 @ SetShift 44 45 clz r1, r3 @ WayShift 46 add r4, r3, #1 @ NumWays 471: sub r2, r2, #1 @ NumSets-- 48 mov r3, r4 @ Temp = NumWays 492: subs r3, r3, #1 @ Temp-- 50 mov r5, r3, lsl r1 51 mov r6, r2, lsl r0 52 orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift) 53 mcr p15, 0, r5, c7, c6, 2 @ Invalidate line 54 bgt 2b 55 cmp r2, #0 56 bgt 1b 57 dsb 58 mov r0,#0 59 mcr p15,0,r0,c7,c5,0 /* Invalidate icache */ 60 isb 61 mov pc, lr 62ENDPROC(v7_l1_cache_invalidate) 63 64/* 65 * v7_all_dcache_invalidate 66 * 67 * Invalidate without flushing the contents of all cache levels 68 * accesible by the current processor core. 69 * This is useful when the contents of cache memory are undetermined 70 * at power-up. 71 * Corrupted registers: r0-r7, r9-r11 72 * 73 * Based on cache-v7.S: v7_flush_dcache_all() 74 */ 75 76ENTRY(v7_all_dcache_invalidate) 77 mrc p15, 1, r0, c0, c0, 1 @ read clidr 78 ands r3, r0, #0x7000000 @ extract loc from clidr 79 mov r3, r3, lsr #23 @ left align loc bit field 80 beq finished @ if loc is 0, then no need to clean 81 mov r10, #0 @ start clean at cache level 0 82loop1: 83 add r2, r10, r10, lsr #1 @ work out 3x current cache level 84 mov r1, r0, lsr r2 @ extract cache type bits from clidr 85 and r1, r1, #7 @ mask of bits for current cache only 86 cmp r1, #2 @ see what cache we have at this level 87 blt skip @ skip if no cache, or just i-cache 88 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 89 isb @ isb to sych the new cssr&csidr 90 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr 91 and r2, r1, #7 @ extract the length of the cache lines 92 add r2, r2, #4 @ add 4 (line length offset) 93 ldr r4, =0x3ff 94 ands r4, r4, r1, lsr #3 @ find maximum number on the way size 95 clz r5, r4 @ find bit pos of way size increment 96 ldr r7, =0x7fff 97 ands r7, r7, r1, lsr #13 @ extract max number of the index size 98loop2: 99 mov r9, r4 @ create working copy of max way size 100loop3: 101 orr r11, r10, r9, lsl r5 @ factor way and cache number into r11 102 orr r11, r11, r7, lsl r2 @ factor index number into r11 103 mcr p15, 0, r11, c7, c6, 2 @ Invalidate line 104 subs r9, r9, #1 @ decrement the way 105 bge loop3 106 subs r7, r7, #1 @ decrement the index 107 bge loop2 108skip: 109 add r10, r10, #2 @ increment cache number 110 cmp r3, r10 111 bgt loop1 112finished: 113 mov r10, #0 @ swith back to cache level 0 114 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 115 dsb 116 isb 117 mov pc, lr 118ENDPROC(v7_all_dcache_invalidate) 119