1#ifndef __MACH_MOTHERBOARD_H 2#define __MACH_MOTHERBOARD_H 3 4/* 5 * Physical addresses, offset from V2M_PA_CS0-3 6 */ 7#define V2M_NOR0 (V2M_PA_CS0) 8#define V2M_NOR1 (V2M_PA_CS1) 9#define V2M_SRAM (V2M_PA_CS2) 10#define V2M_VIDEO_SRAM (V2M_PA_CS3 + 0x00000000) 11#define V2M_LAN9118 (V2M_PA_CS3 + 0x02000000) 12#define V2M_ISP1761 (V2M_PA_CS3 + 0x03000000) 13 14/* 15 * Physical addresses, offset from V2M_PA_CS7 16 */ 17#define V2M_SYSREGS (V2M_PA_CS7 + 0x00000000) 18#define V2M_SYSCTL (V2M_PA_CS7 + 0x00001000) 19#define V2M_SERIAL_BUS_PCI (V2M_PA_CS7 + 0x00002000) 20 21#define V2M_AACI (V2M_PA_CS7 + 0x00004000) 22#define V2M_MMCI (V2M_PA_CS7 + 0x00005000) 23#define V2M_KMI0 (V2M_PA_CS7 + 0x00006000) 24#define V2M_KMI1 (V2M_PA_CS7 + 0x00007000) 25 26#define V2M_UART0 (V2M_PA_CS7 + 0x00009000) 27#define V2M_UART1 (V2M_PA_CS7 + 0x0000a000) 28#define V2M_UART2 (V2M_PA_CS7 + 0x0000b000) 29#define V2M_UART3 (V2M_PA_CS7 + 0x0000c000) 30 31#define V2M_WDT (V2M_PA_CS7 + 0x0000f000) 32 33#define V2M_TIMER01 (V2M_PA_CS7 + 0x00011000) 34#define V2M_TIMER23 (V2M_PA_CS7 + 0x00012000) 35 36#define V2M_SERIAL_BUS_DVI (V2M_PA_CS7 + 0x00016000) 37#define V2M_RTC (V2M_PA_CS7 + 0x00017000) 38 39#define V2M_CF (V2M_PA_CS7 + 0x0001a000) 40#define V2M_CLCD (V2M_PA_CS7 + 0x0001f000) 41 42#define V2M_SYS_ID (V2M_SYSREGS + 0x000) 43#define V2M_SYS_SW (V2M_SYSREGS + 0x004) 44#define V2M_SYS_LED (V2M_SYSREGS + 0x008) 45#define V2M_SYS_100HZ (V2M_SYSREGS + 0x024) 46#define V2M_SYS_FLAGS (V2M_SYSREGS + 0x030) 47#define V2M_SYS_FLAGSSET (V2M_SYSREGS + 0x030) 48#define V2M_SYS_FLAGSCLR (V2M_SYSREGS + 0x034) 49#define V2M_SYS_NVFLAGS (V2M_SYSREGS + 0x038) 50#define V2M_SYS_NVFLAGSSET (V2M_SYSREGS + 0x038) 51#define V2M_SYS_NVFLAGSCLR (V2M_SYSREGS + 0x03c) 52#define V2M_SYS_MCI (V2M_SYSREGS + 0x048) 53#define V2M_SYS_FLASH (V2M_SYSREGS + 0x03c) 54#define V2M_SYS_CFGSW (V2M_SYSREGS + 0x058) 55#define V2M_SYS_24MHZ (V2M_SYSREGS + 0x05c) 56#define V2M_SYS_MISC (V2M_SYSREGS + 0x060) 57#define V2M_SYS_DMA (V2M_SYSREGS + 0x064) 58#define V2M_SYS_PROCID0 (V2M_SYSREGS + 0x084) 59#define V2M_SYS_PROCID1 (V2M_SYSREGS + 0x088) 60#define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0) 61#define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4) 62#define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8) 63 64#define V2M_TIMER0 (V2M_TIMER01 + 0x000) 65#define V2M_TIMER1 (V2M_TIMER01 + 0x020) 66 67#define V2M_TIMER2 (V2M_TIMER23 + 0x000) 68#define V2M_TIMER3 (V2M_TIMER23 + 0x020) 69 70 71/* 72 * Interrupts. Those in {} are for AMBA devices 73 */ 74#define IRQ_V2M_WDT { (32 + 0) } 75#define IRQ_V2M_TIMER0 (32 + 2) 76#define IRQ_V2M_TIMER1 (32 + 2) 77#define IRQ_V2M_TIMER2 (32 + 3) 78#define IRQ_V2M_TIMER3 (32 + 3) 79#define IRQ_V2M_RTC { (32 + 4) } 80#define IRQ_V2M_UART0 { (32 + 5) } 81#define IRQ_V2M_UART1 { (32 + 6) } 82#define IRQ_V2M_UART2 { (32 + 7) } 83#define IRQ_V2M_UART3 { (32 + 8) } 84#define IRQ_V2M_MMCI { (32 + 9), (32 + 10) } 85#define IRQ_V2M_AACI { (32 + 11) } 86#define IRQ_V2M_KMI0 { (32 + 12) } 87#define IRQ_V2M_KMI1 { (32 + 13) } 88#define IRQ_V2M_CLCD { (32 + 14) } 89#define IRQ_V2M_LAN9118 (32 + 15) 90#define IRQ_V2M_ISP1761 (32 + 16) 91#define IRQ_V2M_PCIE (32 + 17) 92 93 94/* 95 * Configuration 96 */ 97#define SYS_CFG_START (1 << 31) 98#define SYS_CFG_WRITE (1 << 30) 99#define SYS_CFG_OSC (1 << 20) 100#define SYS_CFG_VOLT (2 << 20) 101#define SYS_CFG_AMP (3 << 20) 102#define SYS_CFG_TEMP (4 << 20) 103#define SYS_CFG_RESET (5 << 20) 104#define SYS_CFG_SCC (6 << 20) 105#define SYS_CFG_MUXFPGA (7 << 20) 106#define SYS_CFG_SHUTDOWN (8 << 20) 107#define SYS_CFG_REBOOT (9 << 20) 108#define SYS_CFG_DVIMODE (11 << 20) 109#define SYS_CFG_POWER (12 << 20) 110#define SYS_CFG_SITE_MB (0 << 16) 111#define SYS_CFG_SITE_DB1 (1 << 16) 112#define SYS_CFG_SITE_DB2 (2 << 16) 113#define SYS_CFG_STACK(n) ((n) << 12) 114 115#define SYS_CFG_ERR (1 << 1) 116#define SYS_CFG_COMPLETE (1 << 0) 117 118int v2m_cfg_write(u32 devfn, u32 data); 119int v2m_cfg_read(u32 devfn, u32 *data); 120 121#endif 122