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  • only in /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s5p6440/
1/* linux/arch/arm/mach-s5p6440/dev-spi.c
2 *
3 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
4 *	Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/platform_device.h>
12#include <linux/dma-mapping.h>
13#include <linux/gpio.h>
14
15#include <mach/dma.h>
16#include <mach/map.h>
17#include <mach/irqs.h>
18#include <mach/spi-clocks.h>
19
20#include <plat/s3c64xx-spi.h>
21#include <plat/gpio-cfg.h>
22
23static char *spi_src_clks[] = {
24	[S5P6440_SPI_SRCCLK_PCLK] = "pclk",
25	[S5P6440_SPI_SRCCLK_SCLK] = "spi_epll",
26};
27
28/* SPI Controller platform_devices */
29
30/* Since we emulate multi-cs capability, we do not touch the CS.
31 * The emulated CS is toggled by board specific mechanism, as it can
32 * be either some immediate GPIO or some signal out of some other
33 * chip in between ... or some yet another way.
34 * We simply do not assume anything about CS.
35 */
36static int s5p6440_spi_cfg_gpio(struct platform_device *pdev)
37{
38	switch (pdev->id) {
39	case 0:
40		s3c_gpio_cfgpin(S5P6440_GPC(0), S3C_GPIO_SFN(2));
41		s3c_gpio_cfgpin(S5P6440_GPC(1), S3C_GPIO_SFN(2));
42		s3c_gpio_cfgpin(S5P6440_GPC(2), S3C_GPIO_SFN(2));
43		s3c_gpio_setpull(S5P6440_GPC(0), S3C_GPIO_PULL_UP);
44		s3c_gpio_setpull(S5P6440_GPC(1), S3C_GPIO_PULL_UP);
45		s3c_gpio_setpull(S5P6440_GPC(2), S3C_GPIO_PULL_UP);
46		break;
47
48	case 1:
49		s3c_gpio_cfgpin(S5P6440_GPC(4), S3C_GPIO_SFN(2));
50		s3c_gpio_cfgpin(S5P6440_GPC(5), S3C_GPIO_SFN(2));
51		s3c_gpio_cfgpin(S5P6440_GPC(6), S3C_GPIO_SFN(2));
52		s3c_gpio_setpull(S5P6440_GPC(4), S3C_GPIO_PULL_UP);
53		s3c_gpio_setpull(S5P6440_GPC(5), S3C_GPIO_PULL_UP);
54		s3c_gpio_setpull(S5P6440_GPC(6), S3C_GPIO_PULL_UP);
55		break;
56
57	default:
58		dev_err(&pdev->dev, "Invalid SPI Controller number!");
59		return -EINVAL;
60	}
61
62	return 0;
63}
64
65static struct resource s5p6440_spi0_resource[] = {
66	[0] = {
67		.start = S5P6440_PA_SPI0,
68		.end   = S5P6440_PA_SPI0 + 0x100 - 1,
69		.flags = IORESOURCE_MEM,
70	},
71	[1] = {
72		.start = DMACH_SPI0_TX,
73		.end   = DMACH_SPI0_TX,
74		.flags = IORESOURCE_DMA,
75	},
76	[2] = {
77		.start = DMACH_SPI0_RX,
78		.end   = DMACH_SPI0_RX,
79		.flags = IORESOURCE_DMA,
80	},
81	[3] = {
82		.start = IRQ_SPI0,
83		.end   = IRQ_SPI0,
84		.flags = IORESOURCE_IRQ,
85	},
86};
87
88static struct s3c64xx_spi_info s5p6440_spi0_pdata = {
89	.cfg_gpio = s5p6440_spi_cfg_gpio,
90	.fifo_lvl_mask = 0x1ff,
91	.rx_lvl_offset = 15,
92};
93
94static u64 spi_dmamask = DMA_BIT_MASK(32);
95
96struct platform_device s5p6440_device_spi0 = {
97	.name		  = "s3c64xx-spi",
98	.id		  = 0,
99	.num_resources	  = ARRAY_SIZE(s5p6440_spi0_resource),
100	.resource	  = s5p6440_spi0_resource,
101	.dev = {
102		.dma_mask		= &spi_dmamask,
103		.coherent_dma_mask	= DMA_BIT_MASK(32),
104		.platform_data = &s5p6440_spi0_pdata,
105	},
106};
107
108static struct resource s5p6440_spi1_resource[] = {
109	[0] = {
110		.start = S5P6440_PA_SPI1,
111		.end   = S5P6440_PA_SPI1 + 0x100 - 1,
112		.flags = IORESOURCE_MEM,
113	},
114	[1] = {
115		.start = DMACH_SPI1_TX,
116		.end   = DMACH_SPI1_TX,
117		.flags = IORESOURCE_DMA,
118	},
119	[2] = {
120		.start = DMACH_SPI1_RX,
121		.end   = DMACH_SPI1_RX,
122		.flags = IORESOURCE_DMA,
123	},
124	[3] = {
125		.start = IRQ_SPI1,
126		.end   = IRQ_SPI1,
127		.flags = IORESOURCE_IRQ,
128	},
129};
130
131static struct s3c64xx_spi_info s5p6440_spi1_pdata = {
132	.cfg_gpio = s5p6440_spi_cfg_gpio,
133	.fifo_lvl_mask = 0x7f,
134	.rx_lvl_offset = 15,
135};
136
137struct platform_device s5p6440_device_spi1 = {
138	.name		  = "s3c64xx-spi",
139	.id		  = 1,
140	.num_resources	  = ARRAY_SIZE(s5p6440_spi1_resource),
141	.resource	  = s5p6440_spi1_resource,
142	.dev = {
143		.dma_mask		= &spi_dmamask,
144		.coherent_dma_mask	= DMA_BIT_MASK(32),
145		.platform_data = &s5p6440_spi1_pdata,
146	},
147};
148
149void __init s5p6440_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
150{
151	struct s3c64xx_spi_info *pd;
152
153	/* Reject invalid configuration */
154	if (!num_cs || src_clk_nr < 0
155			|| src_clk_nr > S5P6440_SPI_SRCCLK_SCLK) {
156		printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
157		return;
158	}
159
160	switch (cntrlr) {
161	case 0:
162		pd = &s5p6440_spi0_pdata;
163		break;
164	case 1:
165		pd = &s5p6440_spi1_pdata;
166		break;
167	default:
168		printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
169							__func__, cntrlr);
170		return;
171	}
172
173	pd->num_cs = num_cs;
174	pd->src_clk_nr = src_clk_nr;
175	pd->src_clk_name = spi_src_clks[src_clk_nr];
176}
177