1/* 2 * arch/arm/mach-ixp4xx/common-pci.c 3 * 4 * IXP4XX PCI routines for all platforms 5 * 6 * Maintainer: Deepak Saxena <dsaxena@plexity.net> 7 * 8 * Copyright (C) 2002 Intel Corporation. 9 * Copyright (C) 2003 Greg Ungerer <gerg@snapgear.com> 10 * Copyright (C) 2003-2004 MontaVista Software, Inc. 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License version 2 as 14 * published by the Free Software Foundation. 15 * 16 */ 17 18#include <linux/sched.h> 19#include <linux/kernel.h> 20#include <linux/pci.h> 21#include <linux/interrupt.h> 22#include <linux/mm.h> 23#include <linux/init.h> 24#include <linux/ioport.h> 25#include <linux/slab.h> 26#include <linux/delay.h> 27#include <linux/device.h> 28#include <linux/io.h> 29#include <asm/dma-mapping.h> 30 31#include <asm/cputype.h> 32#include <asm/irq.h> 33#include <asm/sizes.h> 34#include <asm/system.h> 35#include <asm/mach/pci.h> 36#include <mach/hardware.h> 37 38 39/* 40 * IXP4xx PCI read function is dependent on whether we are 41 * running A0 or B0 (AppleGate) silicon. 42 */ 43int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data); 44 45/* 46 * Base address for PCI regsiter region 47 */ 48unsigned long ixp4xx_pci_reg_base = 0; 49 50/* 51 * PCI cfg an I/O routines are done by programming a 52 * command/byte enable register, and then read/writing 53 * the data from a data regsiter. We need to ensure 54 * these transactions are atomic or we will end up 55 * with corrupt data on the bus or in a driver. 56 */ 57static DEFINE_SPINLOCK(ixp4xx_pci_lock); 58 59/* 60 * Read from PCI config space 61 */ 62static void crp_read(u32 ad_cbe, u32 *data) 63{ 64 unsigned long flags; 65 spin_lock_irqsave(&ixp4xx_pci_lock, flags); 66 *PCI_CRP_AD_CBE = ad_cbe; 67 *data = *PCI_CRP_RDATA; 68 spin_unlock_irqrestore(&ixp4xx_pci_lock, flags); 69} 70 71/* 72 * Write to PCI config space 73 */ 74static void crp_write(u32 ad_cbe, u32 data) 75{ 76 unsigned long flags; 77 spin_lock_irqsave(&ixp4xx_pci_lock, flags); 78 *PCI_CRP_AD_CBE = CRP_AD_CBE_WRITE | ad_cbe; 79 *PCI_CRP_WDATA = data; 80 spin_unlock_irqrestore(&ixp4xx_pci_lock, flags); 81} 82 83static inline int check_master_abort(void) 84{ 85 /* check Master Abort bit after access */ 86 unsigned long isr = *PCI_ISR; 87 88 if (isr & PCI_ISR_PFE) { 89 /* make sure the Master Abort bit is reset */ 90 *PCI_ISR = PCI_ISR_PFE; 91 pr_debug("%s failed\n", __func__); 92 return 1; 93 } 94 95 return 0; 96} 97 98int ixp4xx_pci_read_errata(u32 addr, u32 cmd, u32* data) 99{ 100 unsigned long flags; 101 int retval = 0; 102 int i; 103 104 spin_lock_irqsave(&ixp4xx_pci_lock, flags); 105 106 *PCI_NP_AD = addr; 107 108 for (i = 0; i < 8; i++) { 109 *PCI_NP_CBE = cmd; 110 *data = *PCI_NP_RDATA; 111 *data = *PCI_NP_RDATA; 112 } 113 114 if(check_master_abort()) 115 retval = 1; 116 117 spin_unlock_irqrestore(&ixp4xx_pci_lock, flags); 118 return retval; 119} 120 121int ixp4xx_pci_read_no_errata(u32 addr, u32 cmd, u32* data) 122{ 123 unsigned long flags; 124 int retval = 0; 125 126 spin_lock_irqsave(&ixp4xx_pci_lock, flags); 127 128 *PCI_NP_AD = addr; 129 130 /* set up and execute the read */ 131 *PCI_NP_CBE = cmd; 132 133 /* the result of the read is now in NP_RDATA */ 134 *data = *PCI_NP_RDATA; 135 136 if(check_master_abort()) 137 retval = 1; 138 139 spin_unlock_irqrestore(&ixp4xx_pci_lock, flags); 140 return retval; 141} 142 143int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data) 144{ 145 unsigned long flags; 146 int retval = 0; 147 148 spin_lock_irqsave(&ixp4xx_pci_lock, flags); 149 150 *PCI_NP_AD = addr; 151 152 /* set up the write */ 153 *PCI_NP_CBE = cmd; 154 155 /* execute the write by writing to NP_WDATA */ 156 *PCI_NP_WDATA = data; 157 158 if(check_master_abort()) 159 retval = 1; 160 161 spin_unlock_irqrestore(&ixp4xx_pci_lock, flags); 162 return retval; 163} 164 165static u32 ixp4xx_config_addr(u8 bus_num, u16 devfn, int where) 166{ 167 u32 addr; 168 if (!bus_num) { 169 /* type 0 */ 170 addr = BIT(32-PCI_SLOT(devfn)) | ((PCI_FUNC(devfn)) << 8) | 171 (where & ~3); 172 } else { 173 /* type 1 */ 174 addr = (bus_num << 16) | ((PCI_SLOT(devfn)) << 11) | 175 ((PCI_FUNC(devfn)) << 8) | (where & ~3) | 1; 176 } 177 return addr; 178} 179 180/* 181 * Mask table, bits to mask for quantity of size 1, 2 or 4 bytes. 182 * 0 and 3 are not valid indexes... 183 */ 184static u32 bytemask[] = { 185 /*0*/ 0, 186 /*1*/ 0xff, 187 /*2*/ 0xffff, 188 /*3*/ 0, 189 /*4*/ 0xffffffff, 190}; 191 192static u32 local_byte_lane_enable_bits(u32 n, int size) 193{ 194 if (size == 1) 195 return (0xf & ~BIT(n)) << CRP_AD_CBE_BESL; 196 if (size == 2) 197 return (0xf & ~(BIT(n) | BIT(n+1))) << CRP_AD_CBE_BESL; 198 if (size == 4) 199 return 0; 200 return 0xffffffff; 201} 202 203static int local_read_config(int where, int size, u32 *value) 204{ 205 u32 n, data; 206 pr_debug("local_read_config from %d size %d\n", where, size); 207 n = where % 4; 208 crp_read(where & ~3, &data); 209 *value = (data >> (8*n)) & bytemask[size]; 210 pr_debug("local_read_config read %#x\n", *value); 211 return PCIBIOS_SUCCESSFUL; 212} 213 214static int local_write_config(int where, int size, u32 value) 215{ 216 u32 n, byte_enables, data; 217 pr_debug("local_write_config %#x to %d size %d\n", value, where, size); 218 n = where % 4; 219 byte_enables = local_byte_lane_enable_bits(n, size); 220 if (byte_enables == 0xffffffff) 221 return PCIBIOS_BAD_REGISTER_NUMBER; 222 data = value << (8*n); 223 crp_write((where & ~3) | byte_enables, data); 224 return PCIBIOS_SUCCESSFUL; 225} 226 227static u32 byte_lane_enable_bits(u32 n, int size) 228{ 229 if (size == 1) 230 return (0xf & ~BIT(n)) << 4; 231 if (size == 2) 232 return (0xf & ~(BIT(n) | BIT(n+1))) << 4; 233 if (size == 4) 234 return 0; 235 return 0xffffffff; 236} 237 238static int ixp4xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value) 239{ 240 u32 n, byte_enables, addr, data; 241 u8 bus_num = bus->number; 242 243 pr_debug("read_config from %d size %d dev %d:%d:%d\n", where, size, 244 bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn)); 245 246 *value = 0xffffffff; 247 n = where % 4; 248 byte_enables = byte_lane_enable_bits(n, size); 249 if (byte_enables == 0xffffffff) 250 return PCIBIOS_BAD_REGISTER_NUMBER; 251 252 addr = ixp4xx_config_addr(bus_num, devfn, where); 253 if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_CONFIGREAD, &data)) 254 return PCIBIOS_DEVICE_NOT_FOUND; 255 256 *value = (data >> (8*n)) & bytemask[size]; 257 pr_debug("read_config_byte read %#x\n", *value); 258 return PCIBIOS_SUCCESSFUL; 259} 260 261static int ixp4xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value) 262{ 263 u32 n, byte_enables, addr, data; 264 u8 bus_num = bus->number; 265 266 pr_debug("write_config_byte %#x to %d size %d dev %d:%d:%d\n", value, where, 267 size, bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn)); 268 269 n = where % 4; 270 byte_enables = byte_lane_enable_bits(n, size); 271 if (byte_enables == 0xffffffff) 272 return PCIBIOS_BAD_REGISTER_NUMBER; 273 274 addr = ixp4xx_config_addr(bus_num, devfn, where); 275 data = value << (8*n); 276 if (ixp4xx_pci_write(addr, byte_enables | NP_CMD_CONFIGWRITE, data)) 277 return PCIBIOS_DEVICE_NOT_FOUND; 278 279 return PCIBIOS_SUCCESSFUL; 280} 281 282struct pci_ops ixp4xx_ops = { 283 .read = ixp4xx_pci_read_config, 284 .write = ixp4xx_pci_write_config, 285}; 286 287/* 288 * PCI abort handler 289 */ 290static int abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs) 291{ 292 u32 isr, status; 293 294 isr = *PCI_ISR; 295 local_read_config(PCI_STATUS, 2, &status); 296 pr_debug("PCI: abort_handler addr = %#lx, isr = %#x, " 297 "status = %#x\n", addr, isr, status); 298 299 /* make sure the Master Abort bit is reset */ 300 *PCI_ISR = PCI_ISR_PFE; 301 status |= PCI_STATUS_REC_MASTER_ABORT; 302 local_write_config(PCI_STATUS, 2, status); 303 304 /* 305 * If it was an imprecise abort, then we need to correct the 306 * return address to be _after_ the instruction. 307 */ 308 if (fsr & (1 << 10)) 309 regs->ARM_pc += 4; 310 311 return 0; 312} 313 314 315/* 316 * Setup DMA mask to 64MB on PCI devices. Ignore all other devices. 317 */ 318static int ixp4xx_pci_platform_notify(struct device *dev) 319{ 320 if(dev->bus == &pci_bus_type) { 321 *dev->dma_mask = SZ_64M - 1; 322 dev->coherent_dma_mask = SZ_64M - 1; 323 dmabounce_register_dev(dev, 2048, 4096); 324 } 325 return 0; 326} 327 328static int ixp4xx_pci_platform_notify_remove(struct device *dev) 329{ 330 if(dev->bus == &pci_bus_type) { 331 dmabounce_unregister_dev(dev); 332 } 333 return 0; 334} 335 336int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size) 337{ 338 return (dev->bus == &pci_bus_type ) && ((dma_addr + size) >= SZ_64M); 339} 340 341/* 342 * Only first 64MB of memory can be accessed via PCI. 343 * We use GFP_DMA to allocate safe buffers to do map/unmap. 344 * This is really ugly and we need a better way of specifying 345 * DMA-capable regions of memory. 346 */ 347void __init ixp4xx_adjust_zones(unsigned long *zone_size, 348 unsigned long *zhole_size) 349{ 350 unsigned int sz = SZ_64M >> PAGE_SHIFT; 351 352 /* 353 * Only adjust if > 64M on current system 354 */ 355 if (zone_size[0] <= sz) 356 return; 357 358 zone_size[1] = zone_size[0] - sz; 359 zone_size[0] = sz; 360 zhole_size[1] = zhole_size[0]; 361 zhole_size[0] = 0; 362} 363 364void __init ixp4xx_pci_preinit(void) 365{ 366 unsigned long cpuid = read_cpuid_id(); 367 368 if (!(cpuid & 0xf) && cpu_is_ixp42x()) { 369 printk("PCI: IXP42x A0 silicon detected - " 370 "PCI Non-Prefetch Workaround Enabled\n"); 371 ixp4xx_pci_read = ixp4xx_pci_read_errata; 372 } else 373 ixp4xx_pci_read = ixp4xx_pci_read_no_errata; 374 375 376 /* hook in our fault handler for PCI errors */ 377 hook_fault_code(16+6, abort_handler, SIGBUS, 0, 378 "imprecise external abort"); 379 380 pr_debug("setup PCI-AHB(inbound) and AHB-PCI(outbound) address mappings\n"); 381 382 /* 383 * We use identity AHB->PCI address translation 384 * in the 0x48000000 to 0x4bffffff address space 385 */ 386 *PCI_PCIMEMBASE = 0x48494A4B; 387 388 /* 389 * We also use identity PCI->AHB address translation 390 * in 4 16MB BARs that begin at the physical memory start 391 */ 392 *PCI_AHBMEMBASE = (PHYS_OFFSET & 0xFF000000) + 393 ((PHYS_OFFSET & 0xFF000000) >> 8) + 394 ((PHYS_OFFSET & 0xFF000000) >> 16) + 395 ((PHYS_OFFSET & 0xFF000000) >> 24) + 396 0x00010203; 397 398 if (*PCI_CSR & PCI_CSR_HOST) { 399 printk("PCI: IXP4xx is host\n"); 400 401 pr_debug("setup BARs in controller\n"); 402 403 /* 404 * We configure the PCI inbound memory windows to be 405 * 1:1 mapped to SDRAM 406 */ 407 local_write_config(PCI_BASE_ADDRESS_0, 4, PHYS_OFFSET); 408 local_write_config(PCI_BASE_ADDRESS_1, 4, PHYS_OFFSET + SZ_16M); 409 local_write_config(PCI_BASE_ADDRESS_2, 4, PHYS_OFFSET + SZ_32M); 410 local_write_config(PCI_BASE_ADDRESS_3, 4, PHYS_OFFSET + SZ_48M); 411 412 /* 413 * Enable CSR window at 64 MiB to allow PCI masters 414 * to continue prefetching past 64 MiB boundary. 415 */ 416 local_write_config(PCI_BASE_ADDRESS_4, 4, PHYS_OFFSET + SZ_64M); 417 418 /* 419 * Enable the IO window to be way up high, at 0xfffffc00 420 */ 421 local_write_config(PCI_BASE_ADDRESS_5, 4, 0xfffffc01); 422 } else { 423 printk("PCI: IXP4xx is target - No bus scan performed\n"); 424 } 425 426 printk("PCI: IXP4xx Using %s access for memory space\n", 427#ifndef CONFIG_IXP4XX_INDIRECT_PCI 428 "direct" 429#else 430 "indirect" 431#endif 432 ); 433 434 pr_debug("clear error bits in ISR\n"); 435 *PCI_ISR = PCI_ISR_PSE | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE; 436 437 /* 438 * Set Initialize Complete in PCI Control Register: allow IXP4XX to 439 * respond to PCI configuration cycles. Specify that the AHB bus is 440 * operating in big endian mode. Set up byte lane swapping between 441 * little-endian PCI and the big-endian AHB bus 442 */ 443#ifdef __ARMEB__ 444 *PCI_CSR = PCI_CSR_IC | PCI_CSR_ABE | PCI_CSR_PDS | PCI_CSR_ADS; 445#else 446 *PCI_CSR = PCI_CSR_IC | PCI_CSR_ABE; 447#endif 448 449 pr_debug("DONE\n"); 450} 451 452int ixp4xx_setup(int nr, struct pci_sys_data *sys) 453{ 454 struct resource *res; 455 456 if (nr >= 1) 457 return 0; 458 459 res = kzalloc(sizeof(*res) * 2, GFP_KERNEL); 460 if (res == NULL) { 461 /* 462 * If we're out of memory this early, something is wrong, 463 * so we might as well catch it here. 464 */ 465 panic("PCI: unable to allocate resources?\n"); 466 } 467 468 local_write_config(PCI_COMMAND, 2, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); 469 470 res[0].name = "PCI I/O Space"; 471 res[0].start = 0x00000000; 472 res[0].end = 0x0000ffff; 473 res[0].flags = IORESOURCE_IO; 474 475 res[1].name = "PCI Memory Space"; 476 res[1].start = PCIBIOS_MIN_MEM; 477 res[1].end = PCIBIOS_MAX_MEM; 478 res[1].flags = IORESOURCE_MEM; 479 480 request_resource(&ioport_resource, &res[0]); 481 request_resource(&iomem_resource, &res[1]); 482 483 sys->resource[0] = &res[0]; 484 sys->resource[1] = &res[1]; 485 sys->resource[2] = NULL; 486 487 platform_notify = ixp4xx_pci_platform_notify; 488 platform_notify_remove = ixp4xx_pci_platform_notify_remove; 489 490 return 1; 491} 492 493struct pci_bus * __devinit ixp4xx_scan_bus(int nr, struct pci_sys_data *sys) 494{ 495 return pci_scan_bus(sys->busnr, &ixp4xx_ops, sys); 496} 497 498int dma_set_coherent_mask(struct device *dev, u64 mask) 499{ 500 if (mask >= SZ_64M - 1) 501 return 0; 502 503 return -EIO; 504} 505 506EXPORT_SYMBOL(ixp4xx_pci_read); 507EXPORT_SYMBOL(ixp4xx_pci_write); 508