1/* 2 * This program is free software; you can redistribute it and/or modify 3 * it under the terms of the GNU General Public License as published by 4 * the Free Software Foundation; either version 2 of the License, or 5 * (at your option) any later version. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 * 12 * You should have received a copy of the GNU General Public License 13 * along with this program; if not, write to the Free Software 14 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 15 */ 16/* DO NOT EDIT!! - this file automatically generated 17 * from .s file by awk -f s2h.awk 18 */ 19/************************************************************************** 20 * * Copyright �� ARM Limited 1998. All rights reserved. 21 * ***********************************************************************/ 22/* ************************************************************************ 23 * 24 * Integrator address map 25 * 26 * ***********************************************************************/ 27 28#ifndef __address_h 29#define __address_h 1 30 31/* ======================================================================== 32 * Integrator definitions 33 * ======================================================================== 34 * ------------------------------------------------------------------------ 35 * Memory definitions 36 * ------------------------------------------------------------------------ 37 * Integrator memory map 38 * 39 */ 40#define INTEGRATOR_BOOT_ROM_LO 0x00000000 41#define INTEGRATOR_BOOT_ROM_HI 0x20000000 42#define INTEGRATOR_BOOT_ROM_BASE INTEGRATOR_BOOT_ROM_HI /* Normal position */ 43#define INTEGRATOR_BOOT_ROM_SIZE SZ_512K 44 45/* 46 * New Core Modules have different amounts of SSRAM, the amount of SSRAM 47 * fitted can be found in HDR_STAT. 48 * 49 * The symbol INTEGRATOR_SSRAM_SIZE is kept, however this now refers to 50 * the minimum amount of SSRAM fitted on any core module. 51 * 52 * New Core Modules also alias the SSRAM. 53 * 54 */ 55#define INTEGRATOR_SSRAM_BASE 0x00000000 56#define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000 57#define INTEGRATOR_SSRAM_SIZE SZ_256K 58 59#define INTEGRATOR_FLASH_BASE 0x24000000 60#define INTEGRATOR_FLASH_SIZE SZ_32M 61 62#define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000 63#define INTEGRATOR_MBRD_SSRAM_SIZE SZ_512K 64 65/* 66 * SDRAM is a SIMM therefore the size is not known. 67 * 68 */ 69#define INTEGRATOR_SDRAM_BASE 0x00040000 70 71#define INTEGRATOR_SDRAM_ALIAS_BASE 0x80000000 72#define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000 73#define INTEGRATOR_HDR1_SDRAM_BASE 0x90000000 74#define INTEGRATOR_HDR2_SDRAM_BASE 0xA0000000 75#define INTEGRATOR_HDR3_SDRAM_BASE 0xB0000000 76 77/* 78 * Logic expansion modules 79 * 80 */ 81#define INTEGRATOR_LOGIC_MODULES_BASE 0xC0000000 82#define INTEGRATOR_LOGIC_MODULE0_BASE 0xC0000000 83#define INTEGRATOR_LOGIC_MODULE1_BASE 0xD0000000 84#define INTEGRATOR_LOGIC_MODULE2_BASE 0xE0000000 85#define INTEGRATOR_LOGIC_MODULE3_BASE 0xF0000000 86 87/* ------------------------------------------------------------------------ 88 * Integrator header card registers 89 * ------------------------------------------------------------------------ 90 * 91 */ 92#define INTEGRATOR_HDR_ID_OFFSET 0x00 93#define INTEGRATOR_HDR_PROC_OFFSET 0x04 94#define INTEGRATOR_HDR_OSC_OFFSET 0x08 95#define INTEGRATOR_HDR_CTRL_OFFSET 0x0C 96#define INTEGRATOR_HDR_STAT_OFFSET 0x10 97#define INTEGRATOR_HDR_LOCK_OFFSET 0x14 98#define INTEGRATOR_HDR_SDRAM_OFFSET 0x20 99#define INTEGRATOR_HDR_INIT_OFFSET 0x24 /* CM9x6 */ 100#define INTEGRATOR_HDR_IC_OFFSET 0x40 101#define INTEGRATOR_HDR_SPDBASE_OFFSET 0x100 102#define INTEGRATOR_HDR_SPDTOP_OFFSET 0x200 103 104#define INTEGRATOR_HDR_BASE 0x10000000 105#define INTEGRATOR_HDR_ID (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_ID_OFFSET) 106#define INTEGRATOR_HDR_PROC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_PROC_OFFSET) 107#define INTEGRATOR_HDR_OSC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_OSC_OFFSET) 108#define INTEGRATOR_HDR_CTRL (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_CTRL_OFFSET) 109#define INTEGRATOR_HDR_STAT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_STAT_OFFSET) 110#define INTEGRATOR_HDR_LOCK (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_LOCK_OFFSET) 111#define INTEGRATOR_HDR_SDRAM (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SDRAM_OFFSET) 112#define INTEGRATOR_HDR_INIT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_INIT_OFFSET) 113#define INTEGRATOR_HDR_IC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_IC_OFFSET) 114#define INTEGRATOR_HDR_SPDBASE (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDBASE_OFFSET) 115#define INTEGRATOR_HDR_SPDTOP (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDTOP_OFFSET) 116 117#define INTEGRATOR_HDR_CTRL_LED 0x01 118#define INTEGRATOR_HDR_CTRL_MBRD_DETECH 0x02 119#define INTEGRATOR_HDR_CTRL_REMAP 0x04 120#define INTEGRATOR_HDR_CTRL_RESET 0x08 121#define INTEGRATOR_HDR_CTRL_HIGHVECTORS 0x10 122#define INTEGRATOR_HDR_CTRL_BIG_ENDIAN 0x20 123#define INTEGRATOR_HDR_CTRL_FASTBUS 0x40 124#define INTEGRATOR_HDR_CTRL_SYNC 0x80 125 126#define INTEGRATOR_HDR_OSC_CORE_10MHz 0x102 127#define INTEGRATOR_HDR_OSC_CORE_15MHz 0x107 128#define INTEGRATOR_HDR_OSC_CORE_20MHz 0x10C 129#define INTEGRATOR_HDR_OSC_CORE_25MHz 0x111 130#define INTEGRATOR_HDR_OSC_CORE_30MHz 0x116 131#define INTEGRATOR_HDR_OSC_CORE_35MHz 0x11B 132#define INTEGRATOR_HDR_OSC_CORE_40MHz 0x120 133#define INTEGRATOR_HDR_OSC_CORE_45MHz 0x125 134#define INTEGRATOR_HDR_OSC_CORE_50MHz 0x12A 135#define INTEGRATOR_HDR_OSC_CORE_55MHz 0x12F 136#define INTEGRATOR_HDR_OSC_CORE_60MHz 0x134 137#define INTEGRATOR_HDR_OSC_CORE_65MHz 0x139 138#define INTEGRATOR_HDR_OSC_CORE_70MHz 0x13E 139#define INTEGRATOR_HDR_OSC_CORE_75MHz 0x143 140#define INTEGRATOR_HDR_OSC_CORE_80MHz 0x148 141#define INTEGRATOR_HDR_OSC_CORE_85MHz 0x14D 142#define INTEGRATOR_HDR_OSC_CORE_90MHz 0x152 143#define INTEGRATOR_HDR_OSC_CORE_95MHz 0x157 144#define INTEGRATOR_HDR_OSC_CORE_100MHz 0x15C 145#define INTEGRATOR_HDR_OSC_CORE_105MHz 0x161 146#define INTEGRATOR_HDR_OSC_CORE_110MHz 0x166 147#define INTEGRATOR_HDR_OSC_CORE_115MHz 0x16B 148#define INTEGRATOR_HDR_OSC_CORE_120MHz 0x170 149#define INTEGRATOR_HDR_OSC_CORE_125MHz 0x175 150#define INTEGRATOR_HDR_OSC_CORE_130MHz 0x17A 151#define INTEGRATOR_HDR_OSC_CORE_135MHz 0x17F 152#define INTEGRATOR_HDR_OSC_CORE_140MHz 0x184 153#define INTEGRATOR_HDR_OSC_CORE_145MHz 0x189 154#define INTEGRATOR_HDR_OSC_CORE_150MHz 0x18E 155#define INTEGRATOR_HDR_OSC_CORE_155MHz 0x193 156#define INTEGRATOR_HDR_OSC_CORE_160MHz 0x198 157#define INTEGRATOR_HDR_OSC_CORE_MASK 0x7FF 158 159#define INTEGRATOR_HDR_OSC_MEM_10MHz 0x10C000 160#define INTEGRATOR_HDR_OSC_MEM_15MHz 0x116000 161#define INTEGRATOR_HDR_OSC_MEM_20MHz 0x120000 162#define INTEGRATOR_HDR_OSC_MEM_25MHz 0x12A000 163#define INTEGRATOR_HDR_OSC_MEM_30MHz 0x134000 164#define INTEGRATOR_HDR_OSC_MEM_33MHz 0x13A000 165#define INTEGRATOR_HDR_OSC_MEM_40MHz 0x148000 166#define INTEGRATOR_HDR_OSC_MEM_50MHz 0x15C000 167#define INTEGRATOR_HDR_OSC_MEM_60MHz 0x170000 168#define INTEGRATOR_HDR_OSC_MEM_66MHz 0x17C000 169#define INTEGRATOR_HDR_OSC_MEM_MASK 0x7FF000 170 171#define INTEGRATOR_HDR_OSC_BUS_MODE_CM7x0 0x0 172#define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x0 0x0800000 173#define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x6 0x1000000 174#define INTEGRATOR_HDR_OSC_BUS_MODE_CM10x00 0x1800000 175#define INTEGRATOR_HDR_OSC_BUS_MODE_MASK 0x1800000 176 177#define INTEGRATOR_HDR_SDRAM_SPD_OK (1 << 5) 178 179 180/* ------------------------------------------------------------------------ 181 * Integrator system registers 182 * ------------------------------------------------------------------------ 183 * 184 */ 185 186/* 187 * System Controller 188 * 189 */ 190#define INTEGRATOR_SC_ID_OFFSET 0x00 191#define INTEGRATOR_SC_OSC_OFFSET 0x04 192#define INTEGRATOR_SC_CTRLS_OFFSET 0x08 193#define INTEGRATOR_SC_CTRLC_OFFSET 0x0C 194#define INTEGRATOR_SC_DEC_OFFSET 0x10 195#define INTEGRATOR_SC_ARB_OFFSET 0x14 196#define INTEGRATOR_SC_PCIENABLE_OFFSET 0x18 197#define INTEGRATOR_SC_LOCK_OFFSET 0x1C 198 199#define INTEGRATOR_SC_BASE 0x11000000 200#define INTEGRATOR_SC_ID (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ID_OFFSET) 201#define INTEGRATOR_SC_OSC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_OSC_OFFSET) 202#define INTEGRATOR_SC_CTRLS (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET) 203#define INTEGRATOR_SC_CTRLC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET) 204#define INTEGRATOR_SC_DEC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_DEC_OFFSET) 205#define INTEGRATOR_SC_ARB (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ARB_OFFSET) 206#define INTEGRATOR_SC_PCIENABLE (INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET) 207#define INTEGRATOR_SC_LOCK (INTEGRATOR_SC_BASE + INTEGRATOR_SC_LOCK_OFFSET) 208 209#define INTEGRATOR_SC_OSC_SYS_10MHz 0x20 210#define INTEGRATOR_SC_OSC_SYS_15MHz 0x34 211#define INTEGRATOR_SC_OSC_SYS_20MHz 0x48 212#define INTEGRATOR_SC_OSC_SYS_25MHz 0x5C 213#define INTEGRATOR_SC_OSC_SYS_33MHz 0x7C 214#define INTEGRATOR_SC_OSC_SYS_MASK 0xFF 215 216#define INTEGRATOR_SC_OSC_PCI_25MHz 0x100 217#define INTEGRATOR_SC_OSC_PCI_33MHz 0x0 218#define INTEGRATOR_SC_OSC_PCI_MASK 0x100 219 220#define INTEGRATOR_SC_CTRL_SOFTRST (1 << 0) 221#define INTEGRATOR_SC_CTRL_nFLVPPEN (1 << 1) 222#define INTEGRATOR_SC_CTRL_nFLWP (1 << 2) 223#define INTEGRATOR_SC_CTRL_URTS0 (1 << 4) 224#define INTEGRATOR_SC_CTRL_UDTR0 (1 << 5) 225#define INTEGRATOR_SC_CTRL_URTS1 (1 << 6) 226#define INTEGRATOR_SC_CTRL_UDTR1 (1 << 7) 227 228/* 229 * External Bus Interface 230 * 231 */ 232#define INTEGRATOR_EBI_BASE 0x12000000 233 234#define INTEGRATOR_EBI_CSR0_OFFSET 0x00 235#define INTEGRATOR_EBI_CSR1_OFFSET 0x04 236#define INTEGRATOR_EBI_CSR2_OFFSET 0x08 237#define INTEGRATOR_EBI_CSR3_OFFSET 0x0C 238#define INTEGRATOR_EBI_LOCK_OFFSET 0x20 239 240#define INTEGRATOR_EBI_CSR0 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR0_OFFSET) 241#define INTEGRATOR_EBI_CSR1 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET) 242#define INTEGRATOR_EBI_CSR2 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR2_OFFSET) 243#define INTEGRATOR_EBI_CSR3 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR3_OFFSET) 244#define INTEGRATOR_EBI_LOCK (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET) 245 246#define INTEGRATOR_EBI_8_BIT 0x00 247#define INTEGRATOR_EBI_16_BIT 0x01 248#define INTEGRATOR_EBI_32_BIT 0x02 249#define INTEGRATOR_EBI_WRITE_ENABLE 0x04 250#define INTEGRATOR_EBI_SYNC 0x08 251#define INTEGRATOR_EBI_WS_2 0x00 252#define INTEGRATOR_EBI_WS_3 0x10 253#define INTEGRATOR_EBI_WS_4 0x20 254#define INTEGRATOR_EBI_WS_5 0x30 255#define INTEGRATOR_EBI_WS_6 0x40 256#define INTEGRATOR_EBI_WS_7 0x50 257#define INTEGRATOR_EBI_WS_8 0x60 258#define INTEGRATOR_EBI_WS_9 0x70 259#define INTEGRATOR_EBI_WS_10 0x80 260#define INTEGRATOR_EBI_WS_11 0x90 261#define INTEGRATOR_EBI_WS_12 0xA0 262#define INTEGRATOR_EBI_WS_13 0xB0 263#define INTEGRATOR_EBI_WS_14 0xC0 264#define INTEGRATOR_EBI_WS_15 0xD0 265#define INTEGRATOR_EBI_WS_16 0xE0 266#define INTEGRATOR_EBI_WS_17 0xF0 267 268 269#define INTEGRATOR_CT_BASE 0x13000000 /* Counter/Timers */ 270#define INTEGRATOR_IC_BASE 0x14000000 /* Interrupt Controller */ 271#define INTEGRATOR_RTC_BASE 0x15000000 /* Real Time Clock */ 272#define INTEGRATOR_UART0_BASE 0x16000000 /* UART 0 */ 273#define INTEGRATOR_UART1_BASE 0x17000000 /* UART 1 */ 274#define INTEGRATOR_KBD_BASE 0x18000000 /* Keyboard */ 275#define INTEGRATOR_MOUSE_BASE 0x19000000 /* Mouse */ 276 277/* 278 * LED's & Switches 279 * 280 */ 281#define INTEGRATOR_DBG_ALPHA_OFFSET 0x00 282#define INTEGRATOR_DBG_LEDS_OFFSET 0x04 283#define INTEGRATOR_DBG_SWITCH_OFFSET 0x08 284 285#define INTEGRATOR_DBG_BASE 0x1A000000 286#define INTEGRATOR_DBG_ALPHA (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_ALPHA_OFFSET) 287#define INTEGRATOR_DBG_LEDS (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_LEDS_OFFSET) 288#define INTEGRATOR_DBG_SWITCH (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_SWITCH_OFFSET) 289 290#define INTEGRATOR_AP_GPIO_BASE 0x1B000000 /* GPIO */ 291 292#define INTEGRATOR_CP_MMC_BASE 0x1C000000 /* MMC */ 293#define INTEGRATOR_CP_AACI_BASE 0x1D000000 /* AACI */ 294#define INTEGRATOR_CP_ETH_BASE 0xC8000000 /* Ethernet */ 295#define INTEGRATOR_CP_GPIO_BASE 0xC9000000 /* GPIO */ 296#define INTEGRATOR_CP_SIC_BASE 0xCA000000 /* SIC */ 297#define INTEGRATOR_CP_CTL_BASE 0xCB000000 /* CP system control */ 298 299/* ------------------------------------------------------------------------ 300 * KMI keyboard/mouse definitions 301 * ------------------------------------------------------------------------ 302 */ 303/* PS2 Keyboard interface */ 304#define KMI0_BASE INTEGRATOR_KBD_BASE 305 306/* PS2 Mouse interface */ 307#define KMI1_BASE INTEGRATOR_MOUSE_BASE 308 309/* KMI definitions are now in include/asm-arm/hardware/amba_kmi.h -- rmk */ 310 311/* ------------------------------------------------------------------------ 312 * Where in the memory map does PCI live? 313 * ------------------------------------------------------------------------ 314 * This represents a fairly liberal usage of address space. Even though 315 * the V3 only has two windows (therefore we need to map stuff on the fly), 316 * we maintain the same addresses, even if they're not mapped. 317 * 318 */ 319#define PHYS_PCI_MEM_BASE 0x40000000 320/* unused 256M from A0000000-AFFFFFFF might be used for I2O ??? 321 */ 322#define PHYS_PCI_IO_BASE 0x60000000 323/* unused (128-16)M from B1000000-B7FFFFFF 324 */ 325#define PHYS_PCI_CONFIG_BASE 0x61000000 326#define PHYS_PCI_V3_BASE 0x62000000 327 328/* ------------------------------------------------------------------------ 329 * Integrator Interrupt Controllers 330 * ------------------------------------------------------------------------ 331 * 332 * Offsets from interrupt controller base 333 * 334 * System Controller interrupt controller base is 335 * 336 * INTEGRATOR_IC_BASE + (header_number << 6) 337 * 338 * Core Module interrupt controller base is 339 * 340 * INTEGRATOR_HDR_IC 341 * 342 */ 343#define IRQ_STATUS 0 344#define IRQ_RAW_STATUS 0x04 345#define IRQ_ENABLE 0x08 346#define IRQ_ENABLE_SET 0x08 347#define IRQ_ENABLE_CLEAR 0x0C 348 349#define INT_SOFT_SET 0x10 350#define INT_SOFT_CLEAR 0x14 351 352#define FIQ_STATUS 0x20 353#define FIQ_RAW_STATUS 0x24 354#define FIQ_ENABLE 0x28 355#define FIQ_ENABLE_SET 0x28 356#define FIQ_ENABLE_CLEAR 0x2C 357 358 359/* ------------------------------------------------------------------------ 360 * Interrupts 361 * ------------------------------------------------------------------------ 362 * 363 * 364 * Each Core Module has two interrupts controllers, one on the core module 365 * itself and one in the system controller on the motherboard. The 366 * READ_INT macro in target.s reads both interrupt controllers and returns 367 * a 32 bit bitmask, bits 0 to 23 are interrupts from the system controller 368 * and bits 24 to 31 are from the core module. 369 * 370 * The following definitions relate to the bitmask returned by READ_INT. 371 * 372 */ 373 374/* ------------------------------------------------------------------------ 375 * LED's 376 * ------------------------------------------------------------------------ 377 * 378 */ 379#define GREEN_LED 0x01 380#define YELLOW_LED 0x02 381#define RED_LED 0x04 382#define GREEN_LED_2 0x08 383#define ALL_LEDS 0x0F 384 385#define LED_BANK INTEGRATOR_DBG_LEDS 386 387/* 388 * Timer definitions 389 * 390 * Only use timer 1 & 2 391 * (both run at 24MHz and will need the clock divider set to 16). 392 * 393 * Timer 0 runs at bus frequency 394 */ 395 396#define INTEGRATOR_TIMER0_BASE INTEGRATOR_CT_BASE 397#define INTEGRATOR_TIMER1_BASE (INTEGRATOR_CT_BASE + 0x100) 398#define INTEGRATOR_TIMER2_BASE (INTEGRATOR_CT_BASE + 0x200) 399 400#define TICKS_PER_uSEC 24 401 402/* 403 * These are useconds NOT ticks. 404 * 405 */ 406#define mSEC_1 1000 407#define mSEC_10 (mSEC_1 * 10) 408 409#define INTEGRATOR_CSR_BASE 0x10000000 410#define INTEGRATOR_CSR_SIZE 0x10000000 411 412#endif 413