1/* 2 * arch/arm/mach-footbridge/include/mach/hardware.h 3 * 4 * Copyright (C) 1998-1999 Russell King. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This file contains the hardware definitions of the EBSA-285. 11 */ 12#ifndef __ASM_ARCH_HARDWARE_H 13#define __ASM_ARCH_HARDWARE_H 14 15/* Virtual Physical Size 16 * 0xff800000 0x40000000 1MB X-Bus 17 * 0xff000000 0x7c000000 1MB PCI I/O space 18 * 0xfe000000 0x42000000 1MB CSR 19 * 0xfd000000 0x78000000 1MB Outbound write flush (not supported) 20 * 0xfc000000 0x79000000 1MB PCI IACK/special space 21 * 0xfb000000 0x7a000000 16MB PCI Config type 1 22 * 0xfa000000 0x7b000000 16MB PCI Config type 0 23 * 0xf9000000 0x50000000 1MB Cache flush 24 * 0xf0000000 0x80000000 16MB ISA memory 25 */ 26#define XBUS_SIZE 0x00100000 27#define XBUS_BASE 0xff800000 28 29#define ARMCSR_SIZE 0x00100000 30#define ARMCSR_BASE 0xfe000000 31 32#define WFLUSH_SIZE 0x00100000 33#define WFLUSH_BASE 0xfd000000 34 35#define PCIIACK_SIZE 0x00100000 36#define PCIIACK_BASE 0xfc000000 37 38#define PCICFG1_SIZE 0x01000000 39#define PCICFG1_BASE 0xfb000000 40 41#define PCICFG0_SIZE 0x01000000 42#define PCICFG0_BASE 0xfa000000 43 44#define PCIMEM_SIZE 0x01000000 45#define PCIMEM_BASE 0xf0000000 46 47#define XBUS_LEDS ((volatile unsigned char *)(XBUS_BASE + 0x12000)) 48#define XBUS_LED_AMBER (1 << 0) 49#define XBUS_LED_GREEN (1 << 1) 50#define XBUS_LED_RED (1 << 2) 51#define XBUS_LED_TOGGLE (1 << 8) 52 53#define XBUS_SWITCH ((volatile unsigned char *)(XBUS_BASE + 0x12000)) 54#define XBUS_SWITCH_SWITCH ((*XBUS_SWITCH) & 15) 55#define XBUS_SWITCH_J17_13 ((*XBUS_SWITCH) & (1 << 4)) 56#define XBUS_SWITCH_J17_11 ((*XBUS_SWITCH) & (1 << 5)) 57#define XBUS_SWITCH_J17_9 ((*XBUS_SWITCH) & (1 << 6)) 58 59#define UNCACHEABLE_ADDR (ARMCSR_BASE + 0x108) 60 61 62/* PIC irq control */ 63#define PIC_LO 0x20 64#define PIC_MASK_LO 0x21 65#define PIC_HI 0xA0 66#define PIC_MASK_HI 0xA1 67 68/* GPIO pins */ 69#define GPIO_CCLK 0x800 70#define GPIO_DSCLK 0x400 71#define GPIO_E2CLK 0x200 72#define GPIO_IOLOAD 0x100 73#define GPIO_RED_LED 0x080 74#define GPIO_WDTIMER 0x040 75#define GPIO_DATA 0x020 76#define GPIO_IOCLK 0x010 77#define GPIO_DONE 0x008 78#define GPIO_FAN 0x004 79#define GPIO_GREEN_LED 0x002 80#define GPIO_RESET 0x001 81 82/* CPLD pins */ 83#define CPLD_DS_ENABLE 8 84#define CPLD_7111_DISABLE 4 85#define CPLD_UNMUTE 2 86#define CPLD_FLASH_WR_ENABLE 1 87 88#ifndef __ASSEMBLY__ 89extern spinlock_t nw_gpio_lock; 90extern void nw_gpio_modify_op(unsigned int mask, unsigned int set); 91extern void nw_gpio_modify_io(unsigned int mask, unsigned int in); 92extern unsigned int nw_gpio_read(void); 93extern void nw_cpld_modify(unsigned int mask, unsigned int set); 94#endif 95 96#define pcibios_assign_all_busses() 1 97 98#define PCIBIOS_MIN_IO 0x1000 99#define PCIBIOS_MIN_MEM 0x81000000 100 101#endif 102