1/* 2 * arch/arm/mach-at91/at91cap9_devices.c 3 * 4 * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com> 5 * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com> 6 * Copyright (C) 2007 Atmel Corporation. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 */ 14#include <asm/mach/arch.h> 15#include <asm/mach/map.h> 16#include <asm/mach/irq.h> 17 18#include <linux/dma-mapping.h> 19#include <linux/platform_device.h> 20#include <linux/i2c-gpio.h> 21 22#include <video/atmel_lcdc.h> 23 24#include <mach/board.h> 25#include <mach/cpu.h> 26#include <mach/gpio.h> 27#include <mach/at91cap9.h> 28#include <mach/at91cap9_matrix.h> 29#include <mach/at91sam9_smc.h> 30 31#include "generic.h" 32 33 34/* -------------------------------------------------------------------- 35 * USB Host 36 * -------------------------------------------------------------------- */ 37 38#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) 39static u64 ohci_dmamask = DMA_BIT_MASK(32); 40static struct at91_usbh_data usbh_data; 41 42static struct resource usbh_resources[] = { 43 [0] = { 44 .start = AT91CAP9_UHP_BASE, 45 .end = AT91CAP9_UHP_BASE + SZ_1M - 1, 46 .flags = IORESOURCE_MEM, 47 }, 48 [1] = { 49 .start = AT91CAP9_ID_UHP, 50 .end = AT91CAP9_ID_UHP, 51 .flags = IORESOURCE_IRQ, 52 }, 53}; 54 55static struct platform_device at91_usbh_device = { 56 .name = "at91_ohci", 57 .id = -1, 58 .dev = { 59 .dma_mask = &ohci_dmamask, 60 .coherent_dma_mask = DMA_BIT_MASK(32), 61 .platform_data = &usbh_data, 62 }, 63 .resource = usbh_resources, 64 .num_resources = ARRAY_SIZE(usbh_resources), 65}; 66 67void __init at91_add_device_usbh(struct at91_usbh_data *data) 68{ 69 int i; 70 71 if (!data) 72 return; 73 74 if (cpu_is_at91cap9_revB()) 75 set_irq_type(AT91CAP9_ID_UHP, IRQ_TYPE_LEVEL_HIGH); 76 77 /* Enable VBus control for UHP ports */ 78 for (i = 0; i < data->ports; i++) { 79 if (data->vbus_pin[i]) 80 at91_set_gpio_output(data->vbus_pin[i], 0); 81 } 82 83 usbh_data = *data; 84 platform_device_register(&at91_usbh_device); 85} 86#else 87void __init at91_add_device_usbh(struct at91_usbh_data *data) {} 88#endif 89 90 91/* -------------------------------------------------------------------- 92 * USB HS Device (Gadget) 93 * -------------------------------------------------------------------- */ 94 95#if defined(CONFIG_USB_GADGET_ATMEL_USBA) || \ 96 defined(CONFIG_USB_GADGET_ATMEL_USBA_MODULE) 97 98static struct resource usba_udc_resources[] = { 99 [0] = { 100 .start = AT91CAP9_UDPHS_FIFO, 101 .end = AT91CAP9_UDPHS_FIFO + SZ_512K - 1, 102 .flags = IORESOURCE_MEM, 103 }, 104 [1] = { 105 .start = AT91CAP9_BASE_UDPHS, 106 .end = AT91CAP9_BASE_UDPHS + SZ_1K - 1, 107 .flags = IORESOURCE_MEM, 108 }, 109 [2] = { 110 .start = AT91CAP9_ID_UDPHS, 111 .end = AT91CAP9_ID_UDPHS, 112 .flags = IORESOURCE_IRQ, 113 }, 114}; 115 116#define EP(nam, idx, maxpkt, maxbk, dma, isoc) \ 117 [idx] = { \ 118 .name = nam, \ 119 .index = idx, \ 120 .fifo_size = maxpkt, \ 121 .nr_banks = maxbk, \ 122 .can_dma = dma, \ 123 .can_isoc = isoc, \ 124 } 125 126static struct usba_ep_data usba_udc_ep[] = { 127 EP("ep0", 0, 64, 1, 0, 0), 128 EP("ep1", 1, 1024, 3, 1, 1), 129 EP("ep2", 2, 1024, 3, 1, 1), 130 EP("ep3", 3, 1024, 2, 1, 1), 131 EP("ep4", 4, 1024, 2, 1, 1), 132 EP("ep5", 5, 1024, 2, 1, 0), 133 EP("ep6", 6, 1024, 2, 1, 0), 134 EP("ep7", 7, 1024, 2, 0, 0), 135}; 136 137#undef EP 138 139/* 140 * pdata doesn't have room for any endpoints, so we need to 141 * append room for the ones we need right after it. 142 */ 143static struct { 144 struct usba_platform_data pdata; 145 struct usba_ep_data ep[8]; 146} usba_udc_data; 147 148static struct platform_device at91_usba_udc_device = { 149 .name = "atmel_usba_udc", 150 .id = -1, 151 .dev = { 152 .platform_data = &usba_udc_data.pdata, 153 }, 154 .resource = usba_udc_resources, 155 .num_resources = ARRAY_SIZE(usba_udc_resources), 156}; 157 158void __init at91_add_device_usba(struct usba_platform_data *data) 159{ 160 if (cpu_is_at91cap9_revB()) { 161 set_irq_type(AT91CAP9_ID_UDPHS, IRQ_TYPE_LEVEL_HIGH); 162 at91_sys_write(AT91_MATRIX_UDPHS, AT91_MATRIX_SELECT_UDPHS | 163 AT91_MATRIX_UDPHS_BYPASS_LOCK); 164 } 165 else 166 at91_sys_write(AT91_MATRIX_UDPHS, AT91_MATRIX_SELECT_UDPHS); 167 168 /* 169 * Invalid pins are 0 on AT91, but the usba driver is shared 170 * with AVR32, which use negative values instead. Once/if 171 * gpio_is_valid() is ported to AT91, revisit this code. 172 */ 173 usba_udc_data.pdata.vbus_pin = -EINVAL; 174 usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep); 175 memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));; 176 177 if (data && data->vbus_pin > 0) { 178 at91_set_gpio_input(data->vbus_pin, 0); 179 at91_set_deglitch(data->vbus_pin, 1); 180 usba_udc_data.pdata.vbus_pin = data->vbus_pin; 181 } 182 183 /* Pullup pin is handled internally by USB device peripheral */ 184 185 /* Clocks */ 186 at91_clock_associate("utmi_clk", &at91_usba_udc_device.dev, "hclk"); 187 at91_clock_associate("udphs_clk", &at91_usba_udc_device.dev, "pclk"); 188 189 platform_device_register(&at91_usba_udc_device); 190} 191#else 192void __init at91_add_device_usba(struct usba_platform_data *data) {} 193#endif 194 195 196/* -------------------------------------------------------------------- 197 * Ethernet 198 * -------------------------------------------------------------------- */ 199 200#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE) 201static u64 eth_dmamask = DMA_BIT_MASK(32); 202static struct at91_eth_data eth_data; 203 204static struct resource eth_resources[] = { 205 [0] = { 206 .start = AT91CAP9_BASE_EMAC, 207 .end = AT91CAP9_BASE_EMAC + SZ_16K - 1, 208 .flags = IORESOURCE_MEM, 209 }, 210 [1] = { 211 .start = AT91CAP9_ID_EMAC, 212 .end = AT91CAP9_ID_EMAC, 213 .flags = IORESOURCE_IRQ, 214 }, 215}; 216 217static struct platform_device at91cap9_eth_device = { 218 .name = "macb", 219 .id = -1, 220 .dev = { 221 .dma_mask = ð_dmamask, 222 .coherent_dma_mask = DMA_BIT_MASK(32), 223 .platform_data = ð_data, 224 }, 225 .resource = eth_resources, 226 .num_resources = ARRAY_SIZE(eth_resources), 227}; 228 229void __init at91_add_device_eth(struct at91_eth_data *data) 230{ 231 if (!data) 232 return; 233 234 if (data->phy_irq_pin) { 235 at91_set_gpio_input(data->phy_irq_pin, 0); 236 at91_set_deglitch(data->phy_irq_pin, 1); 237 } 238 239 /* Pins used for MII and RMII */ 240 at91_set_A_periph(AT91_PIN_PB21, 0); /* ETXCK_EREFCK */ 241 at91_set_A_periph(AT91_PIN_PB22, 0); /* ERXDV */ 242 at91_set_A_periph(AT91_PIN_PB25, 0); /* ERX0 */ 243 at91_set_A_periph(AT91_PIN_PB26, 0); /* ERX1 */ 244 at91_set_A_periph(AT91_PIN_PB27, 0); /* ERXER */ 245 at91_set_A_periph(AT91_PIN_PB28, 0); /* ETXEN */ 246 at91_set_A_periph(AT91_PIN_PB23, 0); /* ETX0 */ 247 at91_set_A_periph(AT91_PIN_PB24, 0); /* ETX1 */ 248 at91_set_A_periph(AT91_PIN_PB30, 0); /* EMDIO */ 249 at91_set_A_periph(AT91_PIN_PB29, 0); /* EMDC */ 250 251 if (!data->is_rmii) { 252 at91_set_B_periph(AT91_PIN_PC25, 0); /* ECRS */ 253 at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */ 254 at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */ 255 at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */ 256 at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */ 257 at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */ 258 at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */ 259 at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */ 260 } 261 262 eth_data = *data; 263 platform_device_register(&at91cap9_eth_device); 264} 265#else 266void __init at91_add_device_eth(struct at91_eth_data *data) {} 267#endif 268 269 270/* -------------------------------------------------------------------- 271 * MMC / SD 272 * -------------------------------------------------------------------- */ 273 274#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE) 275static u64 mmc_dmamask = DMA_BIT_MASK(32); 276static struct at91_mmc_data mmc0_data, mmc1_data; 277 278static struct resource mmc0_resources[] = { 279 [0] = { 280 .start = AT91CAP9_BASE_MCI0, 281 .end = AT91CAP9_BASE_MCI0 + SZ_16K - 1, 282 .flags = IORESOURCE_MEM, 283 }, 284 [1] = { 285 .start = AT91CAP9_ID_MCI0, 286 .end = AT91CAP9_ID_MCI0, 287 .flags = IORESOURCE_IRQ, 288 }, 289}; 290 291static struct platform_device at91cap9_mmc0_device = { 292 .name = "at91_mci", 293 .id = 0, 294 .dev = { 295 .dma_mask = &mmc_dmamask, 296 .coherent_dma_mask = DMA_BIT_MASK(32), 297 .platform_data = &mmc0_data, 298 }, 299 .resource = mmc0_resources, 300 .num_resources = ARRAY_SIZE(mmc0_resources), 301}; 302 303static struct resource mmc1_resources[] = { 304 [0] = { 305 .start = AT91CAP9_BASE_MCI1, 306 .end = AT91CAP9_BASE_MCI1 + SZ_16K - 1, 307 .flags = IORESOURCE_MEM, 308 }, 309 [1] = { 310 .start = AT91CAP9_ID_MCI1, 311 .end = AT91CAP9_ID_MCI1, 312 .flags = IORESOURCE_IRQ, 313 }, 314}; 315 316static struct platform_device at91cap9_mmc1_device = { 317 .name = "at91_mci", 318 .id = 1, 319 .dev = { 320 .dma_mask = &mmc_dmamask, 321 .coherent_dma_mask = DMA_BIT_MASK(32), 322 .platform_data = &mmc1_data, 323 }, 324 .resource = mmc1_resources, 325 .num_resources = ARRAY_SIZE(mmc1_resources), 326}; 327 328void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) 329{ 330 if (!data) 331 return; 332 333 /* input/irq */ 334 if (data->det_pin) { 335 at91_set_gpio_input(data->det_pin, 1); 336 at91_set_deglitch(data->det_pin, 1); 337 } 338 if (data->wp_pin) 339 at91_set_gpio_input(data->wp_pin, 1); 340 if (data->vcc_pin) 341 at91_set_gpio_output(data->vcc_pin, 0); 342 343 if (mmc_id == 0) { /* MCI0 */ 344 /* CLK */ 345 at91_set_A_periph(AT91_PIN_PA2, 0); 346 347 /* CMD */ 348 at91_set_A_periph(AT91_PIN_PA1, 1); 349 350 /* DAT0, maybe DAT1..DAT3 */ 351 at91_set_A_periph(AT91_PIN_PA0, 1); 352 if (data->wire4) { 353 at91_set_A_periph(AT91_PIN_PA3, 1); 354 at91_set_A_periph(AT91_PIN_PA4, 1); 355 at91_set_A_periph(AT91_PIN_PA5, 1); 356 } 357 358 mmc0_data = *data; 359 at91_clock_associate("mci0_clk", &at91cap9_mmc0_device.dev, "mci_clk"); 360 platform_device_register(&at91cap9_mmc0_device); 361 } else { /* MCI1 */ 362 /* CLK */ 363 at91_set_A_periph(AT91_PIN_PA16, 0); 364 365 /* CMD */ 366 at91_set_A_periph(AT91_PIN_PA17, 1); 367 368 /* DAT0, maybe DAT1..DAT3 */ 369 at91_set_A_periph(AT91_PIN_PA18, 1); 370 if (data->wire4) { 371 at91_set_A_periph(AT91_PIN_PA19, 1); 372 at91_set_A_periph(AT91_PIN_PA20, 1); 373 at91_set_A_periph(AT91_PIN_PA21, 1); 374 } 375 376 mmc1_data = *data; 377 at91_clock_associate("mci1_clk", &at91cap9_mmc1_device.dev, "mci_clk"); 378 platform_device_register(&at91cap9_mmc1_device); 379 } 380} 381#else 382void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {} 383#endif 384 385 386/* -------------------------------------------------------------------- 387 * NAND / SmartMedia 388 * -------------------------------------------------------------------- */ 389 390#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE) 391static struct atmel_nand_data nand_data; 392 393#define NAND_BASE AT91_CHIPSELECT_3 394 395static struct resource nand_resources[] = { 396 [0] = { 397 .start = NAND_BASE, 398 .end = NAND_BASE + SZ_256M - 1, 399 .flags = IORESOURCE_MEM, 400 }, 401 [1] = { 402 .start = AT91_BASE_SYS + AT91_ECC, 403 .end = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1, 404 .flags = IORESOURCE_MEM, 405 } 406}; 407 408static struct platform_device at91cap9_nand_device = { 409 .name = "atmel_nand", 410 .id = -1, 411 .dev = { 412 .platform_data = &nand_data, 413 }, 414 .resource = nand_resources, 415 .num_resources = ARRAY_SIZE(nand_resources), 416}; 417 418void __init at91_add_device_nand(struct atmel_nand_data *data) 419{ 420 unsigned long csa; 421 422 if (!data) 423 return; 424 425 csa = at91_sys_read(AT91_MATRIX_EBICSA); 426 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA); 427 428 /* enable pin */ 429 if (data->enable_pin) 430 at91_set_gpio_output(data->enable_pin, 1); 431 432 /* ready/busy pin */ 433 if (data->rdy_pin) 434 at91_set_gpio_input(data->rdy_pin, 1); 435 436 /* card detect pin */ 437 if (data->det_pin) 438 at91_set_gpio_input(data->det_pin, 1); 439 440 nand_data = *data; 441 platform_device_register(&at91cap9_nand_device); 442} 443#else 444void __init at91_add_device_nand(struct atmel_nand_data *data) {} 445#endif 446 447 448/* -------------------------------------------------------------------- 449 * TWI (i2c) 450 * -------------------------------------------------------------------- */ 451 452/* 453 * Prefer the GPIO code since the TWI controller isn't robust 454 * (gets overruns and underruns under load) and can only issue 455 * repeated STARTs in one scenario (the driver doesn't yet handle them). 456 */ 457#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE) 458 459static struct i2c_gpio_platform_data pdata = { 460 .sda_pin = AT91_PIN_PB4, 461 .sda_is_open_drain = 1, 462 .scl_pin = AT91_PIN_PB5, 463 .scl_is_open_drain = 1, 464 .udelay = 2, /* ~100 kHz */ 465}; 466 467static struct platform_device at91cap9_twi_device = { 468 .name = "i2c-gpio", 469 .id = -1, 470 .dev.platform_data = &pdata, 471}; 472 473void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) 474{ 475 at91_set_GPIO_periph(AT91_PIN_PB4, 1); /* TWD (SDA) */ 476 at91_set_multi_drive(AT91_PIN_PB4, 1); 477 478 at91_set_GPIO_periph(AT91_PIN_PB5, 1); /* TWCK (SCL) */ 479 at91_set_multi_drive(AT91_PIN_PB5, 1); 480 481 i2c_register_board_info(0, devices, nr_devices); 482 platform_device_register(&at91cap9_twi_device); 483} 484 485#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE) 486 487static struct resource twi_resources[] = { 488 [0] = { 489 .start = AT91CAP9_BASE_TWI, 490 .end = AT91CAP9_BASE_TWI + SZ_16K - 1, 491 .flags = IORESOURCE_MEM, 492 }, 493 [1] = { 494 .start = AT91CAP9_ID_TWI, 495 .end = AT91CAP9_ID_TWI, 496 .flags = IORESOURCE_IRQ, 497 }, 498}; 499 500static struct platform_device at91cap9_twi_device = { 501 .name = "at91_i2c", 502 .id = -1, 503 .resource = twi_resources, 504 .num_resources = ARRAY_SIZE(twi_resources), 505}; 506 507void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) 508{ 509 /* pins used for TWI interface */ 510 at91_set_B_periph(AT91_PIN_PB4, 0); /* TWD */ 511 at91_set_multi_drive(AT91_PIN_PB4, 1); 512 513 at91_set_B_periph(AT91_PIN_PB5, 0); /* TWCK */ 514 at91_set_multi_drive(AT91_PIN_PB5, 1); 515 516 i2c_register_board_info(0, devices, nr_devices); 517 platform_device_register(&at91cap9_twi_device); 518} 519#else 520void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {} 521#endif 522 523/* -------------------------------------------------------------------- 524 * SPI 525 * -------------------------------------------------------------------- */ 526 527#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE) 528static u64 spi_dmamask = DMA_BIT_MASK(32); 529 530static struct resource spi0_resources[] = { 531 [0] = { 532 .start = AT91CAP9_BASE_SPI0, 533 .end = AT91CAP9_BASE_SPI0 + SZ_16K - 1, 534 .flags = IORESOURCE_MEM, 535 }, 536 [1] = { 537 .start = AT91CAP9_ID_SPI0, 538 .end = AT91CAP9_ID_SPI0, 539 .flags = IORESOURCE_IRQ, 540 }, 541}; 542 543static struct platform_device at91cap9_spi0_device = { 544 .name = "atmel_spi", 545 .id = 0, 546 .dev = { 547 .dma_mask = &spi_dmamask, 548 .coherent_dma_mask = DMA_BIT_MASK(32), 549 }, 550 .resource = spi0_resources, 551 .num_resources = ARRAY_SIZE(spi0_resources), 552}; 553 554static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA5, AT91_PIN_PA3, AT91_PIN_PD0, AT91_PIN_PD1 }; 555 556static struct resource spi1_resources[] = { 557 [0] = { 558 .start = AT91CAP9_BASE_SPI1, 559 .end = AT91CAP9_BASE_SPI1 + SZ_16K - 1, 560 .flags = IORESOURCE_MEM, 561 }, 562 [1] = { 563 .start = AT91CAP9_ID_SPI1, 564 .end = AT91CAP9_ID_SPI1, 565 .flags = IORESOURCE_IRQ, 566 }, 567}; 568 569static struct platform_device at91cap9_spi1_device = { 570 .name = "atmel_spi", 571 .id = 1, 572 .dev = { 573 .dma_mask = &spi_dmamask, 574 .coherent_dma_mask = DMA_BIT_MASK(32), 575 }, 576 .resource = spi1_resources, 577 .num_resources = ARRAY_SIZE(spi1_resources), 578}; 579 580static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB15, AT91_PIN_PB16, AT91_PIN_PB17, AT91_PIN_PB18 }; 581 582void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) 583{ 584 int i; 585 unsigned long cs_pin; 586 short enable_spi0 = 0; 587 short enable_spi1 = 0; 588 589 /* Choose SPI chip-selects */ 590 for (i = 0; i < nr_devices; i++) { 591 if (devices[i].controller_data) 592 cs_pin = (unsigned long) devices[i].controller_data; 593 else if (devices[i].bus_num == 0) 594 cs_pin = spi0_standard_cs[devices[i].chip_select]; 595 else 596 cs_pin = spi1_standard_cs[devices[i].chip_select]; 597 598 if (devices[i].bus_num == 0) 599 enable_spi0 = 1; 600 else 601 enable_spi1 = 1; 602 603 /* enable chip-select pin */ 604 at91_set_gpio_output(cs_pin, 1); 605 606 /* pass chip-select pin to driver */ 607 devices[i].controller_data = (void *) cs_pin; 608 } 609 610 spi_register_board_info(devices, nr_devices); 611 612 /* Configure SPI bus(es) */ 613 if (enable_spi0) { 614 at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */ 615 at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */ 616 at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */ 617 618 at91_clock_associate("spi0_clk", &at91cap9_spi0_device.dev, "spi_clk"); 619 platform_device_register(&at91cap9_spi0_device); 620 } 621 if (enable_spi1) { 622 at91_set_A_periph(AT91_PIN_PB12, 0); /* SPI1_MISO */ 623 at91_set_A_periph(AT91_PIN_PB13, 0); /* SPI1_MOSI */ 624 at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_SPCK */ 625 626 at91_clock_associate("spi1_clk", &at91cap9_spi1_device.dev, "spi_clk"); 627 platform_device_register(&at91cap9_spi1_device); 628 } 629} 630#else 631void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {} 632#endif 633 634 635/* -------------------------------------------------------------------- 636 * Timer/Counter block 637 * -------------------------------------------------------------------- */ 638 639#ifdef CONFIG_ATMEL_TCLIB 640 641static struct resource tcb_resources[] = { 642 [0] = { 643 .start = AT91CAP9_BASE_TCB0, 644 .end = AT91CAP9_BASE_TCB0 + SZ_16K - 1, 645 .flags = IORESOURCE_MEM, 646 }, 647 [1] = { 648 .start = AT91CAP9_ID_TCB, 649 .end = AT91CAP9_ID_TCB, 650 .flags = IORESOURCE_IRQ, 651 }, 652}; 653 654static struct platform_device at91cap9_tcb_device = { 655 .name = "atmel_tcb", 656 .id = 0, 657 .resource = tcb_resources, 658 .num_resources = ARRAY_SIZE(tcb_resources), 659}; 660 661static void __init at91_add_device_tc(void) 662{ 663 /* this chip has one clock and irq for all three TC channels */ 664 at91_clock_associate("tcb_clk", &at91cap9_tcb_device.dev, "t0_clk"); 665 platform_device_register(&at91cap9_tcb_device); 666} 667#else 668static void __init at91_add_device_tc(void) { } 669#endif 670 671 672/* -------------------------------------------------------------------- 673 * RTT 674 * -------------------------------------------------------------------- */ 675 676static struct resource rtt_resources[] = { 677 { 678 .start = AT91_BASE_SYS + AT91_RTT, 679 .end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1, 680 .flags = IORESOURCE_MEM, 681 } 682}; 683 684static struct platform_device at91cap9_rtt_device = { 685 .name = "at91_rtt", 686 .id = 0, 687 .resource = rtt_resources, 688 .num_resources = ARRAY_SIZE(rtt_resources), 689}; 690 691static void __init at91_add_device_rtt(void) 692{ 693 platform_device_register(&at91cap9_rtt_device); 694} 695 696 697/* -------------------------------------------------------------------- 698 * Watchdog 699 * -------------------------------------------------------------------- */ 700 701#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE) 702static struct platform_device at91cap9_wdt_device = { 703 .name = "at91_wdt", 704 .id = -1, 705 .num_resources = 0, 706}; 707 708static void __init at91_add_device_watchdog(void) 709{ 710 platform_device_register(&at91cap9_wdt_device); 711} 712#else 713static void __init at91_add_device_watchdog(void) {} 714#endif 715 716 717/* -------------------------------------------------------------------- 718 * PWM 719 * --------------------------------------------------------------------*/ 720 721#if defined(CONFIG_ATMEL_PWM) 722static u32 pwm_mask; 723 724static struct resource pwm_resources[] = { 725 [0] = { 726 .start = AT91CAP9_BASE_PWMC, 727 .end = AT91CAP9_BASE_PWMC + SZ_16K - 1, 728 .flags = IORESOURCE_MEM, 729 }, 730 [1] = { 731 .start = AT91CAP9_ID_PWMC, 732 .end = AT91CAP9_ID_PWMC, 733 .flags = IORESOURCE_IRQ, 734 }, 735}; 736 737static struct platform_device at91cap9_pwm0_device = { 738 .name = "atmel_pwm", 739 .id = -1, 740 .dev = { 741 .platform_data = &pwm_mask, 742 }, 743 .resource = pwm_resources, 744 .num_resources = ARRAY_SIZE(pwm_resources), 745}; 746 747void __init at91_add_device_pwm(u32 mask) 748{ 749 if (mask & (1 << AT91_PWM0)) 750 at91_set_A_periph(AT91_PIN_PB19, 1); /* enable PWM0 */ 751 752 if (mask & (1 << AT91_PWM1)) 753 at91_set_B_periph(AT91_PIN_PB8, 1); /* enable PWM1 */ 754 755 if (mask & (1 << AT91_PWM2)) 756 at91_set_B_periph(AT91_PIN_PC29, 1); /* enable PWM2 */ 757 758 if (mask & (1 << AT91_PWM3)) 759 at91_set_B_periph(AT91_PIN_PA11, 1); /* enable PWM3 */ 760 761 pwm_mask = mask; 762 763 platform_device_register(&at91cap9_pwm0_device); 764} 765#else 766void __init at91_add_device_pwm(u32 mask) {} 767#endif 768 769 770 771/* -------------------------------------------------------------------- 772 * AC97 773 * -------------------------------------------------------------------- */ 774 775#if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE) 776static u64 ac97_dmamask = DMA_BIT_MASK(32); 777static struct ac97c_platform_data ac97_data; 778 779static struct resource ac97_resources[] = { 780 [0] = { 781 .start = AT91CAP9_BASE_AC97C, 782 .end = AT91CAP9_BASE_AC97C + SZ_16K - 1, 783 .flags = IORESOURCE_MEM, 784 }, 785 [1] = { 786 .start = AT91CAP9_ID_AC97C, 787 .end = AT91CAP9_ID_AC97C, 788 .flags = IORESOURCE_IRQ, 789 }, 790}; 791 792static struct platform_device at91cap9_ac97_device = { 793 .name = "atmel_ac97c", 794 .id = 1, 795 .dev = { 796 .dma_mask = &ac97_dmamask, 797 .coherent_dma_mask = DMA_BIT_MASK(32), 798 .platform_data = &ac97_data, 799 }, 800 .resource = ac97_resources, 801 .num_resources = ARRAY_SIZE(ac97_resources), 802}; 803 804void __init at91_add_device_ac97(struct ac97c_platform_data *data) 805{ 806 if (!data) 807 return; 808 809 at91_set_A_periph(AT91_PIN_PA6, 0); /* AC97FS */ 810 at91_set_A_periph(AT91_PIN_PA7, 0); /* AC97CK */ 811 at91_set_A_periph(AT91_PIN_PA8, 0); /* AC97TX */ 812 at91_set_A_periph(AT91_PIN_PA9, 0); /* AC97RX */ 813 814 /* reset */ 815 if (data->reset_pin) 816 at91_set_gpio_output(data->reset_pin, 0); 817 818 ac97_data = *data; 819 platform_device_register(&at91cap9_ac97_device); 820} 821#else 822void __init at91_add_device_ac97(struct ac97c_platform_data *data) {} 823#endif 824 825 826/* -------------------------------------------------------------------- 827 * LCD Controller 828 * -------------------------------------------------------------------- */ 829 830#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE) 831static u64 lcdc_dmamask = DMA_BIT_MASK(32); 832static struct atmel_lcdfb_info lcdc_data; 833 834static struct resource lcdc_resources[] = { 835 [0] = { 836 .start = AT91CAP9_LCDC_BASE, 837 .end = AT91CAP9_LCDC_BASE + SZ_4K - 1, 838 .flags = IORESOURCE_MEM, 839 }, 840 [1] = { 841 .start = AT91CAP9_ID_LCDC, 842 .end = AT91CAP9_ID_LCDC, 843 .flags = IORESOURCE_IRQ, 844 }, 845}; 846 847static struct platform_device at91_lcdc_device = { 848 .name = "atmel_lcdfb", 849 .id = 0, 850 .dev = { 851 .dma_mask = &lcdc_dmamask, 852 .coherent_dma_mask = DMA_BIT_MASK(32), 853 .platform_data = &lcdc_data, 854 }, 855 .resource = lcdc_resources, 856 .num_resources = ARRAY_SIZE(lcdc_resources), 857}; 858 859void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) 860{ 861 if (!data) 862 return; 863 864 if (cpu_is_at91cap9_revB()) 865 set_irq_type(AT91CAP9_ID_LCDC, IRQ_TYPE_LEVEL_HIGH); 866 867 at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */ 868 at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */ 869 at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */ 870 at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */ 871 at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */ 872 at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */ 873 at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */ 874 at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */ 875 at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */ 876 at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */ 877 at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */ 878 at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */ 879 at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */ 880 at91_set_A_periph(AT91_PIN_PC17, 0); /* LCDD13 */ 881 at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */ 882 at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */ 883 at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */ 884 at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */ 885 at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */ 886 at91_set_A_periph(AT91_PIN_PC25, 0); /* LCDD21 */ 887 at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */ 888 at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */ 889 890 lcdc_data = *data; 891 platform_device_register(&at91_lcdc_device); 892} 893#else 894void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {} 895#endif 896 897 898/* -------------------------------------------------------------------- 899 * SSC -- Synchronous Serial Controller 900 * -------------------------------------------------------------------- */ 901 902#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE) 903static u64 ssc0_dmamask = DMA_BIT_MASK(32); 904 905static struct resource ssc0_resources[] = { 906 [0] = { 907 .start = AT91CAP9_BASE_SSC0, 908 .end = AT91CAP9_BASE_SSC0 + SZ_16K - 1, 909 .flags = IORESOURCE_MEM, 910 }, 911 [1] = { 912 .start = AT91CAP9_ID_SSC0, 913 .end = AT91CAP9_ID_SSC0, 914 .flags = IORESOURCE_IRQ, 915 }, 916}; 917 918static struct platform_device at91cap9_ssc0_device = { 919 .name = "ssc", 920 .id = 0, 921 .dev = { 922 .dma_mask = &ssc0_dmamask, 923 .coherent_dma_mask = DMA_BIT_MASK(32), 924 }, 925 .resource = ssc0_resources, 926 .num_resources = ARRAY_SIZE(ssc0_resources), 927}; 928 929static inline void configure_ssc0_pins(unsigned pins) 930{ 931 if (pins & ATMEL_SSC_TF) 932 at91_set_A_periph(AT91_PIN_PB0, 1); 933 if (pins & ATMEL_SSC_TK) 934 at91_set_A_periph(AT91_PIN_PB1, 1); 935 if (pins & ATMEL_SSC_TD) 936 at91_set_A_periph(AT91_PIN_PB2, 1); 937 if (pins & ATMEL_SSC_RD) 938 at91_set_A_periph(AT91_PIN_PB3, 1); 939 if (pins & ATMEL_SSC_RK) 940 at91_set_A_periph(AT91_PIN_PB4, 1); 941 if (pins & ATMEL_SSC_RF) 942 at91_set_A_periph(AT91_PIN_PB5, 1); 943} 944 945static u64 ssc1_dmamask = DMA_BIT_MASK(32); 946 947static struct resource ssc1_resources[] = { 948 [0] = { 949 .start = AT91CAP9_BASE_SSC1, 950 .end = AT91CAP9_BASE_SSC1 + SZ_16K - 1, 951 .flags = IORESOURCE_MEM, 952 }, 953 [1] = { 954 .start = AT91CAP9_ID_SSC1, 955 .end = AT91CAP9_ID_SSC1, 956 .flags = IORESOURCE_IRQ, 957 }, 958}; 959 960static struct platform_device at91cap9_ssc1_device = { 961 .name = "ssc", 962 .id = 1, 963 .dev = { 964 .dma_mask = &ssc1_dmamask, 965 .coherent_dma_mask = DMA_BIT_MASK(32), 966 }, 967 .resource = ssc1_resources, 968 .num_resources = ARRAY_SIZE(ssc1_resources), 969}; 970 971static inline void configure_ssc1_pins(unsigned pins) 972{ 973 if (pins & ATMEL_SSC_TF) 974 at91_set_A_periph(AT91_PIN_PB6, 1); 975 if (pins & ATMEL_SSC_TK) 976 at91_set_A_periph(AT91_PIN_PB7, 1); 977 if (pins & ATMEL_SSC_TD) 978 at91_set_A_periph(AT91_PIN_PB8, 1); 979 if (pins & ATMEL_SSC_RD) 980 at91_set_A_periph(AT91_PIN_PB9, 1); 981 if (pins & ATMEL_SSC_RK) 982 at91_set_A_periph(AT91_PIN_PB10, 1); 983 if (pins & ATMEL_SSC_RF) 984 at91_set_A_periph(AT91_PIN_PB11, 1); 985} 986 987/* 988 * SSC controllers are accessed through library code, instead of any 989 * kind of all-singing/all-dancing driver. For example one could be 990 * used by a particular I2S audio codec's driver, while another one 991 * on the same system might be used by a custom data capture driver. 992 */ 993void __init at91_add_device_ssc(unsigned id, unsigned pins) 994{ 995 struct platform_device *pdev; 996 997 /* 998 * NOTE: caller is responsible for passing information matching 999 * "pins" to whatever will be using each particular controller. 1000 */ 1001 switch (id) { 1002 case AT91CAP9_ID_SSC0: 1003 pdev = &at91cap9_ssc0_device; 1004 configure_ssc0_pins(pins); 1005 at91_clock_associate("ssc0_clk", &pdev->dev, "ssc"); 1006 break; 1007 case AT91CAP9_ID_SSC1: 1008 pdev = &at91cap9_ssc1_device; 1009 configure_ssc1_pins(pins); 1010 at91_clock_associate("ssc1_clk", &pdev->dev, "ssc"); 1011 break; 1012 default: 1013 return; 1014 } 1015 1016 platform_device_register(pdev); 1017} 1018 1019#else 1020void __init at91_add_device_ssc(unsigned id, unsigned pins) {} 1021#endif 1022 1023 1024/* -------------------------------------------------------------------- 1025 * UART 1026 * -------------------------------------------------------------------- */ 1027 1028#if defined(CONFIG_SERIAL_ATMEL) 1029static struct resource dbgu_resources[] = { 1030 [0] = { 1031 .start = AT91_VA_BASE_SYS + AT91_DBGU, 1032 .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1, 1033 .flags = IORESOURCE_MEM, 1034 }, 1035 [1] = { 1036 .start = AT91_ID_SYS, 1037 .end = AT91_ID_SYS, 1038 .flags = IORESOURCE_IRQ, 1039 }, 1040}; 1041 1042static struct atmel_uart_data dbgu_data = { 1043 .use_dma_tx = 0, 1044 .use_dma_rx = 0, /* DBGU not capable of receive DMA */ 1045 .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU), 1046}; 1047 1048static u64 dbgu_dmamask = DMA_BIT_MASK(32); 1049 1050static struct platform_device at91cap9_dbgu_device = { 1051 .name = "atmel_usart", 1052 .id = 0, 1053 .dev = { 1054 .dma_mask = &dbgu_dmamask, 1055 .coherent_dma_mask = DMA_BIT_MASK(32), 1056 .platform_data = &dbgu_data, 1057 }, 1058 .resource = dbgu_resources, 1059 .num_resources = ARRAY_SIZE(dbgu_resources), 1060}; 1061 1062static inline void configure_dbgu_pins(void) 1063{ 1064 at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */ 1065 at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */ 1066} 1067 1068static struct resource uart0_resources[] = { 1069 [0] = { 1070 .start = AT91CAP9_BASE_US0, 1071 .end = AT91CAP9_BASE_US0 + SZ_16K - 1, 1072 .flags = IORESOURCE_MEM, 1073 }, 1074 [1] = { 1075 .start = AT91CAP9_ID_US0, 1076 .end = AT91CAP9_ID_US0, 1077 .flags = IORESOURCE_IRQ, 1078 }, 1079}; 1080 1081static struct atmel_uart_data uart0_data = { 1082 .use_dma_tx = 1, 1083 .use_dma_rx = 1, 1084}; 1085 1086static u64 uart0_dmamask = DMA_BIT_MASK(32); 1087 1088static struct platform_device at91cap9_uart0_device = { 1089 .name = "atmel_usart", 1090 .id = 1, 1091 .dev = { 1092 .dma_mask = &uart0_dmamask, 1093 .coherent_dma_mask = DMA_BIT_MASK(32), 1094 .platform_data = &uart0_data, 1095 }, 1096 .resource = uart0_resources, 1097 .num_resources = ARRAY_SIZE(uart0_resources), 1098}; 1099 1100static inline void configure_usart0_pins(unsigned pins) 1101{ 1102 at91_set_A_periph(AT91_PIN_PA22, 1); /* TXD0 */ 1103 at91_set_A_periph(AT91_PIN_PA23, 0); /* RXD0 */ 1104 1105 if (pins & ATMEL_UART_RTS) 1106 at91_set_A_periph(AT91_PIN_PA24, 0); /* RTS0 */ 1107 if (pins & ATMEL_UART_CTS) 1108 at91_set_A_periph(AT91_PIN_PA25, 0); /* CTS0 */ 1109} 1110 1111static struct resource uart1_resources[] = { 1112 [0] = { 1113 .start = AT91CAP9_BASE_US1, 1114 .end = AT91CAP9_BASE_US1 + SZ_16K - 1, 1115 .flags = IORESOURCE_MEM, 1116 }, 1117 [1] = { 1118 .start = AT91CAP9_ID_US1, 1119 .end = AT91CAP9_ID_US1, 1120 .flags = IORESOURCE_IRQ, 1121 }, 1122}; 1123 1124static struct atmel_uart_data uart1_data = { 1125 .use_dma_tx = 1, 1126 .use_dma_rx = 1, 1127}; 1128 1129static u64 uart1_dmamask = DMA_BIT_MASK(32); 1130 1131static struct platform_device at91cap9_uart1_device = { 1132 .name = "atmel_usart", 1133 .id = 2, 1134 .dev = { 1135 .dma_mask = &uart1_dmamask, 1136 .coherent_dma_mask = DMA_BIT_MASK(32), 1137 .platform_data = &uart1_data, 1138 }, 1139 .resource = uart1_resources, 1140 .num_resources = ARRAY_SIZE(uart1_resources), 1141}; 1142 1143static inline void configure_usart1_pins(unsigned pins) 1144{ 1145 at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */ 1146 at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */ 1147 1148 if (pins & ATMEL_UART_RTS) 1149 at91_set_B_periph(AT91_PIN_PD7, 0); /* RTS1 */ 1150 if (pins & ATMEL_UART_CTS) 1151 at91_set_B_periph(AT91_PIN_PD8, 0); /* CTS1 */ 1152} 1153 1154static struct resource uart2_resources[] = { 1155 [0] = { 1156 .start = AT91CAP9_BASE_US2, 1157 .end = AT91CAP9_BASE_US2 + SZ_16K - 1, 1158 .flags = IORESOURCE_MEM, 1159 }, 1160 [1] = { 1161 .start = AT91CAP9_ID_US2, 1162 .end = AT91CAP9_ID_US2, 1163 .flags = IORESOURCE_IRQ, 1164 }, 1165}; 1166 1167static struct atmel_uart_data uart2_data = { 1168 .use_dma_tx = 1, 1169 .use_dma_rx = 1, 1170}; 1171 1172static u64 uart2_dmamask = DMA_BIT_MASK(32); 1173 1174static struct platform_device at91cap9_uart2_device = { 1175 .name = "atmel_usart", 1176 .id = 3, 1177 .dev = { 1178 .dma_mask = &uart2_dmamask, 1179 .coherent_dma_mask = DMA_BIT_MASK(32), 1180 .platform_data = &uart2_data, 1181 }, 1182 .resource = uart2_resources, 1183 .num_resources = ARRAY_SIZE(uart2_resources), 1184}; 1185 1186static inline void configure_usart2_pins(unsigned pins) 1187{ 1188 at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */ 1189 at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */ 1190 1191 if (pins & ATMEL_UART_RTS) 1192 at91_set_B_periph(AT91_PIN_PD5, 0); /* RTS2 */ 1193 if (pins & ATMEL_UART_CTS) 1194 at91_set_B_periph(AT91_PIN_PD6, 0); /* CTS2 */ 1195} 1196 1197static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ 1198struct platform_device *atmel_default_console_device; /* the serial console device */ 1199 1200void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) 1201{ 1202 struct platform_device *pdev; 1203 1204 switch (id) { 1205 case 0: /* DBGU */ 1206 pdev = &at91cap9_dbgu_device; 1207 configure_dbgu_pins(); 1208 at91_clock_associate("mck", &pdev->dev, "usart"); 1209 break; 1210 case AT91CAP9_ID_US0: 1211 pdev = &at91cap9_uart0_device; 1212 configure_usart0_pins(pins); 1213 at91_clock_associate("usart0_clk", &pdev->dev, "usart"); 1214 break; 1215 case AT91CAP9_ID_US1: 1216 pdev = &at91cap9_uart1_device; 1217 configure_usart1_pins(pins); 1218 at91_clock_associate("usart1_clk", &pdev->dev, "usart"); 1219 break; 1220 case AT91CAP9_ID_US2: 1221 pdev = &at91cap9_uart2_device; 1222 configure_usart2_pins(pins); 1223 at91_clock_associate("usart2_clk", &pdev->dev, "usart"); 1224 break; 1225 default: 1226 return; 1227 } 1228 pdev->id = portnr; /* update to mapped ID */ 1229 1230 if (portnr < ATMEL_MAX_UART) 1231 at91_uarts[portnr] = pdev; 1232} 1233 1234void __init at91_set_serial_console(unsigned portnr) 1235{ 1236 if (portnr < ATMEL_MAX_UART) 1237 atmel_default_console_device = at91_uarts[portnr]; 1238} 1239 1240void __init at91_add_device_serial(void) 1241{ 1242 int i; 1243 1244 for (i = 0; i < ATMEL_MAX_UART; i++) { 1245 if (at91_uarts[i]) 1246 platform_device_register(at91_uarts[i]); 1247 } 1248 1249 if (!atmel_default_console_device) 1250 printk(KERN_INFO "AT91: No default serial console defined.\n"); 1251} 1252#else 1253void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {} 1254void __init at91_set_serial_console(unsigned portnr) {} 1255void __init at91_add_device_serial(void) {} 1256#endif 1257 1258 1259/* -------------------------------------------------------------------- */ 1260/* 1261 * These devices are always present and don't need any board-specific 1262 * setup. 1263 */ 1264static int __init at91_add_standard_devices(void) 1265{ 1266 at91_add_device_rtt(); 1267 at91_add_device_watchdog(); 1268 at91_add_device_tc(); 1269 return 0; 1270} 1271 1272arch_initcall(at91_add_standard_devices); 1273