1/* 2 * wm8400.c -- WM8400 ALSA Soc Audio driver 3 * 4 * Copyright 2008, 2009 Wolfson Microelectronics PLC. 5 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 * 12 */ 13 14#include <linux/module.h> 15#include <linux/moduleparam.h> 16#include <linux/kernel.h> 17#include <linux/slab.h> 18#include <linux/init.h> 19#include <linux/delay.h> 20#include <linux/pm.h> 21#include <linux/platform_device.h> 22#include <linux/regulator/consumer.h> 23#include <linux/mfd/wm8400-audio.h> 24#include <linux/mfd/wm8400-private.h> 25#include <sound/core.h> 26#include <sound/pcm.h> 27#include <sound/pcm_params.h> 28#include <sound/soc.h> 29#include <sound/soc-dapm.h> 30#include <sound/initval.h> 31#include <sound/tlv.h> 32 33#include "wm8400.h" 34 35/* Fake register for internal state */ 36#define WM8400_INTDRIVBITS (WM8400_REGISTER_COUNT + 1) 37#define WM8400_INMIXL_PWR 0 38#define WM8400_AINLMUX_PWR 1 39#define WM8400_INMIXR_PWR 2 40#define WM8400_AINRMUX_PWR 3 41 42static struct regulator_bulk_data power[] = { 43 { 44 .supply = "I2S1VDD", 45 }, 46 { 47 .supply = "I2S2VDD", 48 }, 49 { 50 .supply = "DCVDD", 51 }, 52 { 53 .supply = "AVDD", 54 }, 55 { 56 .supply = "FLLVDD", 57 }, 58 { 59 .supply = "HPVDD", 60 }, 61 { 62 .supply = "SPKVDD", 63 }, 64}; 65 66/* codec private data */ 67struct wm8400_priv { 68 struct snd_soc_codec codec; 69 struct wm8400 *wm8400; 70 u16 fake_register; 71 unsigned int sysclk; 72 unsigned int pcmclk; 73 struct work_struct work; 74 int fll_in, fll_out; 75}; 76 77static inline unsigned int wm8400_read(struct snd_soc_codec *codec, 78 unsigned int reg) 79{ 80 struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec); 81 82 if (reg == WM8400_INTDRIVBITS) 83 return wm8400->fake_register; 84 else 85 return wm8400_reg_read(wm8400->wm8400, reg); 86} 87 88/* 89 * write to the wm8400 register space 90 */ 91static int wm8400_write(struct snd_soc_codec *codec, unsigned int reg, 92 unsigned int value) 93{ 94 struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec); 95 96 if (reg == WM8400_INTDRIVBITS) { 97 wm8400->fake_register = value; 98 return 0; 99 } else 100 return wm8400_set_bits(wm8400->wm8400, reg, 0xffff, value); 101} 102 103static void wm8400_codec_reset(struct snd_soc_codec *codec) 104{ 105 struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec); 106 107 wm8400_reset_codec_reg_cache(wm8400->wm8400); 108} 109 110static const DECLARE_TLV_DB_SCALE(rec_mix_tlv, -1500, 600, 0); 111 112static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1650, 3000, 0); 113 114static const DECLARE_TLV_DB_SCALE(out_mix_tlv, -2100, 0, 0); 115 116static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -7300, 600, 0); 117 118static const DECLARE_TLV_DB_SCALE(out_omix_tlv, -600, 0, 0); 119 120static const DECLARE_TLV_DB_SCALE(out_dac_tlv, -7163, 0, 0); 121 122static const DECLARE_TLV_DB_SCALE(in_adc_tlv, -7163, 1763, 0); 123 124static const DECLARE_TLV_DB_SCALE(out_sidetone_tlv, -3600, 0, 0); 125 126static int wm8400_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol, 127 struct snd_ctl_elem_value *ucontrol) 128{ 129 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 130 struct soc_mixer_control *mc = 131 (struct soc_mixer_control *)kcontrol->private_value; 132 int reg = mc->reg; 133 int ret; 134 u16 val; 135 136 ret = snd_soc_put_volsw(kcontrol, ucontrol); 137 if (ret < 0) 138 return ret; 139 140 /* now hit the volume update bits (always bit 8) */ 141 val = wm8400_read(codec, reg); 142 return wm8400_write(codec, reg, val | 0x0100); 143} 144 145#define WM8400_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert, tlv_array) \ 146{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ 147 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ 148 SNDRV_CTL_ELEM_ACCESS_READWRITE,\ 149 .tlv.p = (tlv_array), \ 150 .info = snd_soc_info_volsw, \ 151 .get = snd_soc_get_volsw, .put = wm8400_outpga_put_volsw_vu, \ 152 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) } 153 154 155static const char *wm8400_digital_sidetone[] = 156 {"None", "Left ADC", "Right ADC", "Reserved"}; 157 158static const struct soc_enum wm8400_left_digital_sidetone_enum = 159SOC_ENUM_SINGLE(WM8400_DIGITAL_SIDE_TONE, 160 WM8400_ADC_TO_DACL_SHIFT, 2, wm8400_digital_sidetone); 161 162static const struct soc_enum wm8400_right_digital_sidetone_enum = 163SOC_ENUM_SINGLE(WM8400_DIGITAL_SIDE_TONE, 164 WM8400_ADC_TO_DACR_SHIFT, 2, wm8400_digital_sidetone); 165 166static const char *wm8400_adcmode[] = 167 {"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"}; 168 169static const struct soc_enum wm8400_right_adcmode_enum = 170SOC_ENUM_SINGLE(WM8400_ADC_CTRL, WM8400_ADC_HPF_CUT_SHIFT, 3, wm8400_adcmode); 171 172static const struct snd_kcontrol_new wm8400_snd_controls[] = { 173/* INMIXL */ 174SOC_SINGLE("LIN12 PGA Boost", WM8400_INPUT_MIXER3, WM8400_L12MNBST_SHIFT, 175 1, 0), 176SOC_SINGLE("LIN34 PGA Boost", WM8400_INPUT_MIXER3, WM8400_L34MNBST_SHIFT, 177 1, 0), 178/* INMIXR */ 179SOC_SINGLE("RIN12 PGA Boost", WM8400_INPUT_MIXER3, WM8400_R12MNBST_SHIFT, 180 1, 0), 181SOC_SINGLE("RIN34 PGA Boost", WM8400_INPUT_MIXER3, WM8400_R34MNBST_SHIFT, 182 1, 0), 183 184/* LOMIX */ 185SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8400_OUTPUT_MIXER3, 186 WM8400_LLI3LOVOL_SHIFT, 7, 0, out_mix_tlv), 187SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER3, 188 WM8400_LR12LOVOL_SHIFT, 7, 0, out_mix_tlv), 189SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER3, 190 WM8400_LL12LOVOL_SHIFT, 7, 0, out_mix_tlv), 191SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8400_OUTPUT_MIXER5, 192 WM8400_LRI3LOVOL_SHIFT, 7, 0, out_mix_tlv), 193SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8400_OUTPUT_MIXER5, 194 WM8400_LRBLOVOL_SHIFT, 7, 0, out_mix_tlv), 195SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8400_OUTPUT_MIXER5, 196 WM8400_LRBLOVOL_SHIFT, 7, 0, out_mix_tlv), 197 198/* ROMIX */ 199SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8400_OUTPUT_MIXER4, 200 WM8400_RRI3ROVOL_SHIFT, 7, 0, out_mix_tlv), 201SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER4, 202 WM8400_RL12ROVOL_SHIFT, 7, 0, out_mix_tlv), 203SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER4, 204 WM8400_RR12ROVOL_SHIFT, 7, 0, out_mix_tlv), 205SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8400_OUTPUT_MIXER6, 206 WM8400_RLI3ROVOL_SHIFT, 7, 0, out_mix_tlv), 207SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8400_OUTPUT_MIXER6, 208 WM8400_RLBROVOL_SHIFT, 7, 0, out_mix_tlv), 209SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8400_OUTPUT_MIXER6, 210 WM8400_RRBROVOL_SHIFT, 7, 0, out_mix_tlv), 211 212/* LOUT */ 213WM8400_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8400_LEFT_OUTPUT_VOLUME, 214 WM8400_LOUTVOL_SHIFT, WM8400_LOUTVOL_MASK, 0, out_pga_tlv), 215SOC_SINGLE("LOUT ZC", WM8400_LEFT_OUTPUT_VOLUME, WM8400_LOZC_SHIFT, 1, 0), 216 217/* ROUT */ 218WM8400_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8400_RIGHT_OUTPUT_VOLUME, 219 WM8400_ROUTVOL_SHIFT, WM8400_ROUTVOL_MASK, 0, out_pga_tlv), 220SOC_SINGLE("ROUT ZC", WM8400_RIGHT_OUTPUT_VOLUME, WM8400_ROZC_SHIFT, 1, 0), 221 222/* LOPGA */ 223WM8400_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8400_LEFT_OPGA_VOLUME, 224 WM8400_LOPGAVOL_SHIFT, WM8400_LOPGAVOL_MASK, 0, out_pga_tlv), 225SOC_SINGLE("LOPGA ZC Switch", WM8400_LEFT_OPGA_VOLUME, 226 WM8400_LOPGAZC_SHIFT, 1, 0), 227 228/* ROPGA */ 229WM8400_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8400_RIGHT_OPGA_VOLUME, 230 WM8400_ROPGAVOL_SHIFT, WM8400_ROPGAVOL_MASK, 0, out_pga_tlv), 231SOC_SINGLE("ROPGA ZC Switch", WM8400_RIGHT_OPGA_VOLUME, 232 WM8400_ROPGAZC_SHIFT, 1, 0), 233 234SOC_SINGLE("LON Mute Switch", WM8400_LINE_OUTPUTS_VOLUME, 235 WM8400_LONMUTE_SHIFT, 1, 0), 236SOC_SINGLE("LOP Mute Switch", WM8400_LINE_OUTPUTS_VOLUME, 237 WM8400_LOPMUTE_SHIFT, 1, 0), 238SOC_SINGLE("LOP Attenuation Switch", WM8400_LINE_OUTPUTS_VOLUME, 239 WM8400_LOATTN_SHIFT, 1, 0), 240SOC_SINGLE("RON Mute Switch", WM8400_LINE_OUTPUTS_VOLUME, 241 WM8400_RONMUTE_SHIFT, 1, 0), 242SOC_SINGLE("ROP Mute Switch", WM8400_LINE_OUTPUTS_VOLUME, 243 WM8400_ROPMUTE_SHIFT, 1, 0), 244SOC_SINGLE("ROP Attenuation Switch", WM8400_LINE_OUTPUTS_VOLUME, 245 WM8400_ROATTN_SHIFT, 1, 0), 246 247SOC_SINGLE("OUT3 Mute Switch", WM8400_OUT3_4_VOLUME, 248 WM8400_OUT3MUTE_SHIFT, 1, 0), 249SOC_SINGLE("OUT3 Attenuation Switch", WM8400_OUT3_4_VOLUME, 250 WM8400_OUT3ATTN_SHIFT, 1, 0), 251 252SOC_SINGLE("OUT4 Mute Switch", WM8400_OUT3_4_VOLUME, 253 WM8400_OUT4MUTE_SHIFT, 1, 0), 254SOC_SINGLE("OUT4 Attenuation Switch", WM8400_OUT3_4_VOLUME, 255 WM8400_OUT4ATTN_SHIFT, 1, 0), 256 257SOC_SINGLE("Speaker Mode Switch", WM8400_CLASSD1, 258 WM8400_CDMODE_SHIFT, 1, 0), 259 260SOC_SINGLE("Speaker Output Attenuation Volume", WM8400_SPEAKER_VOLUME, 261 WM8400_SPKATTN_SHIFT, WM8400_SPKATTN_MASK, 0), 262SOC_SINGLE("Speaker DC Boost Volume", WM8400_CLASSD3, 263 WM8400_DCGAIN_SHIFT, 6, 0), 264SOC_SINGLE("Speaker AC Boost Volume", WM8400_CLASSD3, 265 WM8400_ACGAIN_SHIFT, 6, 0), 266 267WM8400_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume", 268 WM8400_LEFT_DAC_DIGITAL_VOLUME, WM8400_DACL_VOL_SHIFT, 269 127, 0, out_dac_tlv), 270 271WM8400_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume", 272 WM8400_RIGHT_DAC_DIGITAL_VOLUME, WM8400_DACR_VOL_SHIFT, 273 127, 0, out_dac_tlv), 274 275SOC_ENUM("Left Digital Sidetone", wm8400_left_digital_sidetone_enum), 276SOC_ENUM("Right Digital Sidetone", wm8400_right_digital_sidetone_enum), 277 278SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8400_DIGITAL_SIDE_TONE, 279 WM8400_ADCL_DAC_SVOL_SHIFT, 15, 0, out_sidetone_tlv), 280SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8400_DIGITAL_SIDE_TONE, 281 WM8400_ADCR_DAC_SVOL_SHIFT, 15, 0, out_sidetone_tlv), 282 283SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8400_ADC_CTRL, 284 WM8400_ADC_HPF_ENA_SHIFT, 1, 0), 285 286SOC_ENUM("ADC HPF Mode", wm8400_right_adcmode_enum), 287 288WM8400_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume", 289 WM8400_LEFT_ADC_DIGITAL_VOLUME, 290 WM8400_ADCL_VOL_SHIFT, 291 WM8400_ADCL_VOL_MASK, 292 0, 293 in_adc_tlv), 294 295WM8400_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume", 296 WM8400_RIGHT_ADC_DIGITAL_VOLUME, 297 WM8400_ADCR_VOL_SHIFT, 298 WM8400_ADCR_VOL_MASK, 299 0, 300 in_adc_tlv), 301 302WM8400_OUTPGA_SINGLE_R_TLV("LIN12 Volume", 303 WM8400_LEFT_LINE_INPUT_1_2_VOLUME, 304 WM8400_LIN12VOL_SHIFT, 305 WM8400_LIN12VOL_MASK, 306 0, 307 in_pga_tlv), 308 309SOC_SINGLE("LIN12 ZC Switch", WM8400_LEFT_LINE_INPUT_1_2_VOLUME, 310 WM8400_LI12ZC_SHIFT, 1, 0), 311 312SOC_SINGLE("LIN12 Mute Switch", WM8400_LEFT_LINE_INPUT_1_2_VOLUME, 313 WM8400_LI12MUTE_SHIFT, 1, 0), 314 315WM8400_OUTPGA_SINGLE_R_TLV("LIN34 Volume", 316 WM8400_LEFT_LINE_INPUT_3_4_VOLUME, 317 WM8400_LIN34VOL_SHIFT, 318 WM8400_LIN34VOL_MASK, 319 0, 320 in_pga_tlv), 321 322SOC_SINGLE("LIN34 ZC Switch", WM8400_LEFT_LINE_INPUT_3_4_VOLUME, 323 WM8400_LI34ZC_SHIFT, 1, 0), 324 325SOC_SINGLE("LIN34 Mute Switch", WM8400_LEFT_LINE_INPUT_3_4_VOLUME, 326 WM8400_LI34MUTE_SHIFT, 1, 0), 327 328WM8400_OUTPGA_SINGLE_R_TLV("RIN12 Volume", 329 WM8400_RIGHT_LINE_INPUT_1_2_VOLUME, 330 WM8400_RIN12VOL_SHIFT, 331 WM8400_RIN12VOL_MASK, 332 0, 333 in_pga_tlv), 334 335SOC_SINGLE("RIN12 ZC Switch", WM8400_RIGHT_LINE_INPUT_1_2_VOLUME, 336 WM8400_RI12ZC_SHIFT, 1, 0), 337 338SOC_SINGLE("RIN12 Mute Switch", WM8400_RIGHT_LINE_INPUT_1_2_VOLUME, 339 WM8400_RI12MUTE_SHIFT, 1, 0), 340 341WM8400_OUTPGA_SINGLE_R_TLV("RIN34 Volume", 342 WM8400_RIGHT_LINE_INPUT_3_4_VOLUME, 343 WM8400_RIN34VOL_SHIFT, 344 WM8400_RIN34VOL_MASK, 345 0, 346 in_pga_tlv), 347 348SOC_SINGLE("RIN34 ZC Switch", WM8400_RIGHT_LINE_INPUT_3_4_VOLUME, 349 WM8400_RI34ZC_SHIFT, 1, 0), 350 351SOC_SINGLE("RIN34 Mute Switch", WM8400_RIGHT_LINE_INPUT_3_4_VOLUME, 352 WM8400_RI34MUTE_SHIFT, 1, 0), 353 354}; 355 356/* add non dapm controls */ 357static int wm8400_add_controls(struct snd_soc_codec *codec) 358{ 359 return snd_soc_add_controls(codec, wm8400_snd_controls, 360 ARRAY_SIZE(wm8400_snd_controls)); 361} 362 363/* 364 * _DAPM_ Controls 365 */ 366 367static int inmixer_event (struct snd_soc_dapm_widget *w, 368 struct snd_kcontrol *kcontrol, int event) 369{ 370 u16 reg, fakepower; 371 372 reg = wm8400_read(w->codec, WM8400_POWER_MANAGEMENT_2); 373 fakepower = wm8400_read(w->codec, WM8400_INTDRIVBITS); 374 375 if (fakepower & ((1 << WM8400_INMIXL_PWR) | 376 (1 << WM8400_AINLMUX_PWR))) { 377 reg |= WM8400_AINL_ENA; 378 } else { 379 reg &= ~WM8400_AINL_ENA; 380 } 381 382 if (fakepower & ((1 << WM8400_INMIXR_PWR) | 383 (1 << WM8400_AINRMUX_PWR))) { 384 reg |= WM8400_AINR_ENA; 385 } else { 386 reg &= ~WM8400_AINL_ENA; 387 } 388 wm8400_write(w->codec, WM8400_POWER_MANAGEMENT_2, reg); 389 390 return 0; 391} 392 393static int outmixer_event (struct snd_soc_dapm_widget *w, 394 struct snd_kcontrol * kcontrol, int event) 395{ 396 struct soc_mixer_control *mc = 397 (struct soc_mixer_control *)kcontrol->private_value; 398 u32 reg_shift = mc->shift; 399 int ret = 0; 400 u16 reg; 401 402 switch (reg_shift) { 403 case WM8400_SPEAKER_MIXER | (WM8400_LDSPK << 8) : 404 reg = wm8400_read(w->codec, WM8400_OUTPUT_MIXER1); 405 if (reg & WM8400_LDLO) { 406 printk(KERN_WARNING 407 "Cannot set as Output Mixer 1 LDLO Set\n"); 408 ret = -1; 409 } 410 break; 411 case WM8400_SPEAKER_MIXER | (WM8400_RDSPK << 8): 412 reg = wm8400_read(w->codec, WM8400_OUTPUT_MIXER2); 413 if (reg & WM8400_RDRO) { 414 printk(KERN_WARNING 415 "Cannot set as Output Mixer 2 RDRO Set\n"); 416 ret = -1; 417 } 418 break; 419 case WM8400_OUTPUT_MIXER1 | (WM8400_LDLO << 8): 420 reg = wm8400_read(w->codec, WM8400_SPEAKER_MIXER); 421 if (reg & WM8400_LDSPK) { 422 printk(KERN_WARNING 423 "Cannot set as Speaker Mixer LDSPK Set\n"); 424 ret = -1; 425 } 426 break; 427 case WM8400_OUTPUT_MIXER2 | (WM8400_RDRO << 8): 428 reg = wm8400_read(w->codec, WM8400_SPEAKER_MIXER); 429 if (reg & WM8400_RDSPK) { 430 printk(KERN_WARNING 431 "Cannot set as Speaker Mixer RDSPK Set\n"); 432 ret = -1; 433 } 434 break; 435 } 436 437 return ret; 438} 439 440/* INMIX dB values */ 441static const unsigned int in_mix_tlv[] = { 442 TLV_DB_RANGE_HEAD(1), 443 0,7, TLV_DB_SCALE_ITEM(-1200, 600, 0), 444}; 445 446/* Left In PGA Connections */ 447static const struct snd_kcontrol_new wm8400_dapm_lin12_pga_controls[] = { 448SOC_DAPM_SINGLE("LIN1 Switch", WM8400_INPUT_MIXER2, WM8400_LMN1_SHIFT, 1, 0), 449SOC_DAPM_SINGLE("LIN2 Switch", WM8400_INPUT_MIXER2, WM8400_LMP2_SHIFT, 1, 0), 450}; 451 452static const struct snd_kcontrol_new wm8400_dapm_lin34_pga_controls[] = { 453SOC_DAPM_SINGLE("LIN3 Switch", WM8400_INPUT_MIXER2, WM8400_LMN3_SHIFT, 1, 0), 454SOC_DAPM_SINGLE("LIN4 Switch", WM8400_INPUT_MIXER2, WM8400_LMP4_SHIFT, 1, 0), 455}; 456 457/* Right In PGA Connections */ 458static const struct snd_kcontrol_new wm8400_dapm_rin12_pga_controls[] = { 459SOC_DAPM_SINGLE("RIN1 Switch", WM8400_INPUT_MIXER2, WM8400_RMN1_SHIFT, 1, 0), 460SOC_DAPM_SINGLE("RIN2 Switch", WM8400_INPUT_MIXER2, WM8400_RMP2_SHIFT, 1, 0), 461}; 462 463static const struct snd_kcontrol_new wm8400_dapm_rin34_pga_controls[] = { 464SOC_DAPM_SINGLE("RIN3 Switch", WM8400_INPUT_MIXER2, WM8400_RMN3_SHIFT, 1, 0), 465SOC_DAPM_SINGLE("RIN4 Switch", WM8400_INPUT_MIXER2, WM8400_RMP4_SHIFT, 1, 0), 466}; 467 468/* INMIXL */ 469static const struct snd_kcontrol_new wm8400_dapm_inmixl_controls[] = { 470SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8400_INPUT_MIXER3, 471 WM8400_LDBVOL_SHIFT, WM8400_LDBVOL_MASK, 0, in_mix_tlv), 472SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8400_INPUT_MIXER5, WM8400_LI2BVOL_SHIFT, 473 7, 0, in_mix_tlv), 474SOC_DAPM_SINGLE("LINPGA12 Switch", WM8400_INPUT_MIXER3, WM8400_L12MNB_SHIFT, 475 1, 0), 476SOC_DAPM_SINGLE("LINPGA34 Switch", WM8400_INPUT_MIXER3, WM8400_L34MNB_SHIFT, 477 1, 0), 478}; 479 480/* INMIXR */ 481static const struct snd_kcontrol_new wm8400_dapm_inmixr_controls[] = { 482SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8400_INPUT_MIXER4, 483 WM8400_RDBVOL_SHIFT, WM8400_RDBVOL_MASK, 0, in_mix_tlv), 484SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8400_INPUT_MIXER6, WM8400_RI2BVOL_SHIFT, 485 7, 0, in_mix_tlv), 486SOC_DAPM_SINGLE("RINPGA12 Switch", WM8400_INPUT_MIXER3, WM8400_L12MNB_SHIFT, 487 1, 0), 488SOC_DAPM_SINGLE("RINPGA34 Switch", WM8400_INPUT_MIXER3, WM8400_L34MNB_SHIFT, 489 1, 0), 490}; 491 492/* AINLMUX */ 493static const char *wm8400_ainlmux[] = 494 {"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"}; 495 496static const struct soc_enum wm8400_ainlmux_enum = 497SOC_ENUM_SINGLE( WM8400_INPUT_MIXER1, WM8400_AINLMODE_SHIFT, 498 ARRAY_SIZE(wm8400_ainlmux), wm8400_ainlmux); 499 500static const struct snd_kcontrol_new wm8400_dapm_ainlmux_controls = 501SOC_DAPM_ENUM("Route", wm8400_ainlmux_enum); 502 503/* DIFFINL */ 504 505/* AINRMUX */ 506static const char *wm8400_ainrmux[] = 507 {"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"}; 508 509static const struct soc_enum wm8400_ainrmux_enum = 510SOC_ENUM_SINGLE( WM8400_INPUT_MIXER1, WM8400_AINRMODE_SHIFT, 511 ARRAY_SIZE(wm8400_ainrmux), wm8400_ainrmux); 512 513static const struct snd_kcontrol_new wm8400_dapm_ainrmux_controls = 514SOC_DAPM_ENUM("Route", wm8400_ainrmux_enum); 515 516/* RXVOICE */ 517static const struct snd_kcontrol_new wm8400_dapm_rxvoice_controls[] = { 518SOC_DAPM_SINGLE_TLV("LIN4/RXN", WM8400_INPUT_MIXER5, WM8400_LR4BVOL_SHIFT, 519 WM8400_LR4BVOL_MASK, 0, in_mix_tlv), 520SOC_DAPM_SINGLE_TLV("RIN4/RXP", WM8400_INPUT_MIXER6, WM8400_RL4BVOL_SHIFT, 521 WM8400_RL4BVOL_MASK, 0, in_mix_tlv), 522}; 523 524/* LOMIX */ 525static const struct snd_kcontrol_new wm8400_dapm_lomix_controls[] = { 526SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8400_OUTPUT_MIXER1, 527 WM8400_LRBLO_SHIFT, 1, 0), 528SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8400_OUTPUT_MIXER1, 529 WM8400_LLBLO_SHIFT, 1, 0), 530SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8400_OUTPUT_MIXER1, 531 WM8400_LRI3LO_SHIFT, 1, 0), 532SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8400_OUTPUT_MIXER1, 533 WM8400_LLI3LO_SHIFT, 1, 0), 534SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER1, 535 WM8400_LR12LO_SHIFT, 1, 0), 536SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER1, 537 WM8400_LL12LO_SHIFT, 1, 0), 538SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8400_OUTPUT_MIXER1, 539 WM8400_LDLO_SHIFT, 1, 0), 540}; 541 542/* ROMIX */ 543static const struct snd_kcontrol_new wm8400_dapm_romix_controls[] = { 544SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8400_OUTPUT_MIXER2, 545 WM8400_RLBRO_SHIFT, 1, 0), 546SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8400_OUTPUT_MIXER2, 547 WM8400_RRBRO_SHIFT, 1, 0), 548SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8400_OUTPUT_MIXER2, 549 WM8400_RLI3RO_SHIFT, 1, 0), 550SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8400_OUTPUT_MIXER2, 551 WM8400_RRI3RO_SHIFT, 1, 0), 552SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER2, 553 WM8400_RL12RO_SHIFT, 1, 0), 554SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER2, 555 WM8400_RR12RO_SHIFT, 1, 0), 556SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8400_OUTPUT_MIXER2, 557 WM8400_RDRO_SHIFT, 1, 0), 558}; 559 560/* LONMIX */ 561static const struct snd_kcontrol_new wm8400_dapm_lonmix_controls[] = { 562SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8400_LINE_MIXER1, 563 WM8400_LLOPGALON_SHIFT, 1, 0), 564SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8400_LINE_MIXER1, 565 WM8400_LROPGALON_SHIFT, 1, 0), 566SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8400_LINE_MIXER1, 567 WM8400_LOPLON_SHIFT, 1, 0), 568}; 569 570/* LOPMIX */ 571static const struct snd_kcontrol_new wm8400_dapm_lopmix_controls[] = { 572SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8400_LINE_MIXER1, 573 WM8400_LR12LOP_SHIFT, 1, 0), 574SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8400_LINE_MIXER1, 575 WM8400_LL12LOP_SHIFT, 1, 0), 576SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8400_LINE_MIXER1, 577 WM8400_LLOPGALOP_SHIFT, 1, 0), 578}; 579 580/* RONMIX */ 581static const struct snd_kcontrol_new wm8400_dapm_ronmix_controls[] = { 582SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8400_LINE_MIXER2, 583 WM8400_RROPGARON_SHIFT, 1, 0), 584SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8400_LINE_MIXER2, 585 WM8400_RLOPGARON_SHIFT, 1, 0), 586SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8400_LINE_MIXER2, 587 WM8400_ROPRON_SHIFT, 1, 0), 588}; 589 590/* ROPMIX */ 591static const struct snd_kcontrol_new wm8400_dapm_ropmix_controls[] = { 592SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8400_LINE_MIXER2, 593 WM8400_RL12ROP_SHIFT, 1, 0), 594SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8400_LINE_MIXER2, 595 WM8400_RR12ROP_SHIFT, 1, 0), 596SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8400_LINE_MIXER2, 597 WM8400_RROPGAROP_SHIFT, 1, 0), 598}; 599 600/* OUT3MIX */ 601static const struct snd_kcontrol_new wm8400_dapm_out3mix_controls[] = { 602SOC_DAPM_SINGLE("OUT3MIX LIN4/RXP Bypass Switch", WM8400_OUT3_4_MIXER, 603 WM8400_LI4O3_SHIFT, 1, 0), 604SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8400_OUT3_4_MIXER, 605 WM8400_LPGAO3_SHIFT, 1, 0), 606}; 607 608/* OUT4MIX */ 609static const struct snd_kcontrol_new wm8400_dapm_out4mix_controls[] = { 610SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8400_OUT3_4_MIXER, 611 WM8400_RPGAO4_SHIFT, 1, 0), 612SOC_DAPM_SINGLE("OUT4MIX RIN4/RXP Bypass Switch", WM8400_OUT3_4_MIXER, 613 WM8400_RI4O4_SHIFT, 1, 0), 614}; 615 616/* SPKMIX */ 617static const struct snd_kcontrol_new wm8400_dapm_spkmix_controls[] = { 618SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8400_SPEAKER_MIXER, 619 WM8400_LI2SPK_SHIFT, 1, 0), 620SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8400_SPEAKER_MIXER, 621 WM8400_LB2SPK_SHIFT, 1, 0), 622SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8400_SPEAKER_MIXER, 623 WM8400_LOPGASPK_SHIFT, 1, 0), 624SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8400_SPEAKER_MIXER, 625 WM8400_LDSPK_SHIFT, 1, 0), 626SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8400_SPEAKER_MIXER, 627 WM8400_RDSPK_SHIFT, 1, 0), 628SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8400_SPEAKER_MIXER, 629 WM8400_ROPGASPK_SHIFT, 1, 0), 630SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8400_SPEAKER_MIXER, 631 WM8400_RL12ROP_SHIFT, 1, 0), 632SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8400_SPEAKER_MIXER, 633 WM8400_RI2SPK_SHIFT, 1, 0), 634}; 635 636static const struct snd_soc_dapm_widget wm8400_dapm_widgets[] = { 637/* Input Side */ 638/* Input Lines */ 639SND_SOC_DAPM_INPUT("LIN1"), 640SND_SOC_DAPM_INPUT("LIN2"), 641SND_SOC_DAPM_INPUT("LIN3"), 642SND_SOC_DAPM_INPUT("LIN4/RXN"), 643SND_SOC_DAPM_INPUT("RIN3"), 644SND_SOC_DAPM_INPUT("RIN4/RXP"), 645SND_SOC_DAPM_INPUT("RIN1"), 646SND_SOC_DAPM_INPUT("RIN2"), 647SND_SOC_DAPM_INPUT("Internal ADC Source"), 648 649/* DACs */ 650SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8400_POWER_MANAGEMENT_2, 651 WM8400_ADCL_ENA_SHIFT, 0), 652SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8400_POWER_MANAGEMENT_2, 653 WM8400_ADCR_ENA_SHIFT, 0), 654 655/* Input PGAs */ 656SND_SOC_DAPM_MIXER("LIN12 PGA", WM8400_POWER_MANAGEMENT_2, 657 WM8400_LIN12_ENA_SHIFT, 658 0, &wm8400_dapm_lin12_pga_controls[0], 659 ARRAY_SIZE(wm8400_dapm_lin12_pga_controls)), 660SND_SOC_DAPM_MIXER("LIN34 PGA", WM8400_POWER_MANAGEMENT_2, 661 WM8400_LIN34_ENA_SHIFT, 662 0, &wm8400_dapm_lin34_pga_controls[0], 663 ARRAY_SIZE(wm8400_dapm_lin34_pga_controls)), 664SND_SOC_DAPM_MIXER("RIN12 PGA", WM8400_POWER_MANAGEMENT_2, 665 WM8400_RIN12_ENA_SHIFT, 666 0, &wm8400_dapm_rin12_pga_controls[0], 667 ARRAY_SIZE(wm8400_dapm_rin12_pga_controls)), 668SND_SOC_DAPM_MIXER("RIN34 PGA", WM8400_POWER_MANAGEMENT_2, 669 WM8400_RIN34_ENA_SHIFT, 670 0, &wm8400_dapm_rin34_pga_controls[0], 671 ARRAY_SIZE(wm8400_dapm_rin34_pga_controls)), 672 673/* INMIXL */ 674SND_SOC_DAPM_MIXER_E("INMIXL", WM8400_INTDRIVBITS, WM8400_INMIXL_PWR, 0, 675 &wm8400_dapm_inmixl_controls[0], 676 ARRAY_SIZE(wm8400_dapm_inmixl_controls), 677 inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 678 679/* AINLMUX */ 680SND_SOC_DAPM_MUX_E("AILNMUX", WM8400_INTDRIVBITS, WM8400_AINLMUX_PWR, 0, 681 &wm8400_dapm_ainlmux_controls, inmixer_event, 682 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 683 684/* INMIXR */ 685SND_SOC_DAPM_MIXER_E("INMIXR", WM8400_INTDRIVBITS, WM8400_INMIXR_PWR, 0, 686 &wm8400_dapm_inmixr_controls[0], 687 ARRAY_SIZE(wm8400_dapm_inmixr_controls), 688 inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 689 690/* AINRMUX */ 691SND_SOC_DAPM_MUX_E("AIRNMUX", WM8400_INTDRIVBITS, WM8400_AINRMUX_PWR, 0, 692 &wm8400_dapm_ainrmux_controls, inmixer_event, 693 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 694 695/* Output Side */ 696/* DACs */ 697SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8400_POWER_MANAGEMENT_3, 698 WM8400_DACL_ENA_SHIFT, 0), 699SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8400_POWER_MANAGEMENT_3, 700 WM8400_DACR_ENA_SHIFT, 0), 701 702/* LOMIX */ 703SND_SOC_DAPM_MIXER_E("LOMIX", WM8400_POWER_MANAGEMENT_3, 704 WM8400_LOMIX_ENA_SHIFT, 705 0, &wm8400_dapm_lomix_controls[0], 706 ARRAY_SIZE(wm8400_dapm_lomix_controls), 707 outmixer_event, SND_SOC_DAPM_PRE_REG), 708 709/* LONMIX */ 710SND_SOC_DAPM_MIXER("LONMIX", WM8400_POWER_MANAGEMENT_3, WM8400_LON_ENA_SHIFT, 711 0, &wm8400_dapm_lonmix_controls[0], 712 ARRAY_SIZE(wm8400_dapm_lonmix_controls)), 713 714/* LOPMIX */ 715SND_SOC_DAPM_MIXER("LOPMIX", WM8400_POWER_MANAGEMENT_3, WM8400_LOP_ENA_SHIFT, 716 0, &wm8400_dapm_lopmix_controls[0], 717 ARRAY_SIZE(wm8400_dapm_lopmix_controls)), 718 719/* OUT3MIX */ 720SND_SOC_DAPM_MIXER("OUT3MIX", WM8400_POWER_MANAGEMENT_1, WM8400_OUT3_ENA_SHIFT, 721 0, &wm8400_dapm_out3mix_controls[0], 722 ARRAY_SIZE(wm8400_dapm_out3mix_controls)), 723 724/* SPKMIX */ 725SND_SOC_DAPM_MIXER_E("SPKMIX", WM8400_POWER_MANAGEMENT_1, WM8400_SPK_ENA_SHIFT, 726 0, &wm8400_dapm_spkmix_controls[0], 727 ARRAY_SIZE(wm8400_dapm_spkmix_controls), outmixer_event, 728 SND_SOC_DAPM_PRE_REG), 729 730/* OUT4MIX */ 731SND_SOC_DAPM_MIXER("OUT4MIX", WM8400_POWER_MANAGEMENT_1, WM8400_OUT4_ENA_SHIFT, 732 0, &wm8400_dapm_out4mix_controls[0], 733 ARRAY_SIZE(wm8400_dapm_out4mix_controls)), 734 735/* ROPMIX */ 736SND_SOC_DAPM_MIXER("ROPMIX", WM8400_POWER_MANAGEMENT_3, WM8400_ROP_ENA_SHIFT, 737 0, &wm8400_dapm_ropmix_controls[0], 738 ARRAY_SIZE(wm8400_dapm_ropmix_controls)), 739 740/* RONMIX */ 741SND_SOC_DAPM_MIXER("RONMIX", WM8400_POWER_MANAGEMENT_3, WM8400_RON_ENA_SHIFT, 742 0, &wm8400_dapm_ronmix_controls[0], 743 ARRAY_SIZE(wm8400_dapm_ronmix_controls)), 744 745/* ROMIX */ 746SND_SOC_DAPM_MIXER_E("ROMIX", WM8400_POWER_MANAGEMENT_3, 747 WM8400_ROMIX_ENA_SHIFT, 748 0, &wm8400_dapm_romix_controls[0], 749 ARRAY_SIZE(wm8400_dapm_romix_controls), 750 outmixer_event, SND_SOC_DAPM_PRE_REG), 751 752/* LOUT PGA */ 753SND_SOC_DAPM_PGA("LOUT PGA", WM8400_POWER_MANAGEMENT_1, WM8400_LOUT_ENA_SHIFT, 754 0, NULL, 0), 755 756/* ROUT PGA */ 757SND_SOC_DAPM_PGA("ROUT PGA", WM8400_POWER_MANAGEMENT_1, WM8400_ROUT_ENA_SHIFT, 758 0, NULL, 0), 759 760/* LOPGA */ 761SND_SOC_DAPM_PGA("LOPGA", WM8400_POWER_MANAGEMENT_3, WM8400_LOPGA_ENA_SHIFT, 0, 762 NULL, 0), 763 764/* ROPGA */ 765SND_SOC_DAPM_PGA("ROPGA", WM8400_POWER_MANAGEMENT_3, WM8400_ROPGA_ENA_SHIFT, 0, 766 NULL, 0), 767 768/* MICBIAS */ 769SND_SOC_DAPM_MICBIAS("MICBIAS", WM8400_POWER_MANAGEMENT_1, 770 WM8400_MIC1BIAS_ENA_SHIFT, 0), 771 772SND_SOC_DAPM_OUTPUT("LON"), 773SND_SOC_DAPM_OUTPUT("LOP"), 774SND_SOC_DAPM_OUTPUT("OUT3"), 775SND_SOC_DAPM_OUTPUT("LOUT"), 776SND_SOC_DAPM_OUTPUT("SPKN"), 777SND_SOC_DAPM_OUTPUT("SPKP"), 778SND_SOC_DAPM_OUTPUT("ROUT"), 779SND_SOC_DAPM_OUTPUT("OUT4"), 780SND_SOC_DAPM_OUTPUT("ROP"), 781SND_SOC_DAPM_OUTPUT("RON"), 782 783SND_SOC_DAPM_OUTPUT("Internal DAC Sink"), 784}; 785 786static const struct snd_soc_dapm_route audio_map[] = { 787 /* Make DACs turn on when playing even if not mixed into any outputs */ 788 {"Internal DAC Sink", NULL, "Left DAC"}, 789 {"Internal DAC Sink", NULL, "Right DAC"}, 790 791 /* Make ADCs turn on when recording 792 * even if not mixed from any inputs */ 793 {"Left ADC", NULL, "Internal ADC Source"}, 794 {"Right ADC", NULL, "Internal ADC Source"}, 795 796 /* Input Side */ 797 /* LIN12 PGA */ 798 {"LIN12 PGA", "LIN1 Switch", "LIN1"}, 799 {"LIN12 PGA", "LIN2 Switch", "LIN2"}, 800 /* LIN34 PGA */ 801 {"LIN34 PGA", "LIN3 Switch", "LIN3"}, 802 {"LIN34 PGA", "LIN4 Switch", "LIN4/RXN"}, 803 /* INMIXL */ 804 {"INMIXL", "Record Left Volume", "LOMIX"}, 805 {"INMIXL", "LIN2 Volume", "LIN2"}, 806 {"INMIXL", "LINPGA12 Switch", "LIN12 PGA"}, 807 {"INMIXL", "LINPGA34 Switch", "LIN34 PGA"}, 808 /* AILNMUX */ 809 {"AILNMUX", "INMIXL Mix", "INMIXL"}, 810 {"AILNMUX", "DIFFINL Mix", "LIN12 PGA"}, 811 {"AILNMUX", "DIFFINL Mix", "LIN34 PGA"}, 812 {"AILNMUX", "RXVOICE Mix", "LIN4/RXN"}, 813 {"AILNMUX", "RXVOICE Mix", "RIN4/RXP"}, 814 /* ADC */ 815 {"Left ADC", NULL, "AILNMUX"}, 816 817 /* RIN12 PGA */ 818 {"RIN12 PGA", "RIN1 Switch", "RIN1"}, 819 {"RIN12 PGA", "RIN2 Switch", "RIN2"}, 820 /* RIN34 PGA */ 821 {"RIN34 PGA", "RIN3 Switch", "RIN3"}, 822 {"RIN34 PGA", "RIN4 Switch", "RIN4/RXP"}, 823 /* INMIXL */ 824 {"INMIXR", "Record Right Volume", "ROMIX"}, 825 {"INMIXR", "RIN2 Volume", "RIN2"}, 826 {"INMIXR", "RINPGA12 Switch", "RIN12 PGA"}, 827 {"INMIXR", "RINPGA34 Switch", "RIN34 PGA"}, 828 /* AIRNMUX */ 829 {"AIRNMUX", "INMIXR Mix", "INMIXR"}, 830 {"AIRNMUX", "DIFFINR Mix", "RIN12 PGA"}, 831 {"AIRNMUX", "DIFFINR Mix", "RIN34 PGA"}, 832 {"AIRNMUX", "RXVOICE Mix", "LIN4/RXN"}, 833 {"AIRNMUX", "RXVOICE Mix", "RIN4/RXP"}, 834 /* ADC */ 835 {"Right ADC", NULL, "AIRNMUX"}, 836 837 /* LOMIX */ 838 {"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"}, 839 {"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"}, 840 {"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"}, 841 {"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"}, 842 {"LOMIX", "LOMIX Right ADC Bypass Switch", "AIRNMUX"}, 843 {"LOMIX", "LOMIX Left ADC Bypass Switch", "AILNMUX"}, 844 {"LOMIX", "LOMIX Left DAC Switch", "Left DAC"}, 845 846 /* ROMIX */ 847 {"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"}, 848 {"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"}, 849 {"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"}, 850 {"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"}, 851 {"ROMIX", "ROMIX Right ADC Bypass Switch", "AIRNMUX"}, 852 {"ROMIX", "ROMIX Left ADC Bypass Switch", "AILNMUX"}, 853 {"ROMIX", "ROMIX Right DAC Switch", "Right DAC"}, 854 855 /* SPKMIX */ 856 {"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"}, 857 {"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"}, 858 {"SPKMIX", "SPKMIX LADC Bypass Switch", "AILNMUX"}, 859 {"SPKMIX", "SPKMIX RADC Bypass Switch", "AIRNMUX"}, 860 {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"}, 861 {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"}, 862 {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"}, 863 {"SPKMIX", "SPKMIX Left DAC Switch", "Right DAC"}, 864 865 /* LONMIX */ 866 {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"}, 867 {"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"}, 868 {"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"}, 869 870 /* LOPMIX */ 871 {"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"}, 872 {"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"}, 873 {"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"}, 874 875 /* OUT3MIX */ 876 {"OUT3MIX", "OUT3MIX LIN4/RXP Bypass Switch", "LIN4/RXN"}, 877 {"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"}, 878 879 /* OUT4MIX */ 880 {"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"}, 881 {"OUT4MIX", "OUT4MIX RIN4/RXP Bypass Switch", "RIN4/RXP"}, 882 883 /* RONMIX */ 884 {"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"}, 885 {"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"}, 886 {"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"}, 887 888 /* ROPMIX */ 889 {"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"}, 890 {"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"}, 891 {"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"}, 892 893 /* Out Mixer PGAs */ 894 {"LOPGA", NULL, "LOMIX"}, 895 {"ROPGA", NULL, "ROMIX"}, 896 897 {"LOUT PGA", NULL, "LOMIX"}, 898 {"ROUT PGA", NULL, "ROMIX"}, 899 900 /* Output Pins */ 901 {"LON", NULL, "LONMIX"}, 902 {"LOP", NULL, "LOPMIX"}, 903 {"OUT3", NULL, "OUT3MIX"}, 904 {"LOUT", NULL, "LOUT PGA"}, 905 {"SPKN", NULL, "SPKMIX"}, 906 {"ROUT", NULL, "ROUT PGA"}, 907 {"OUT4", NULL, "OUT4MIX"}, 908 {"ROP", NULL, "ROPMIX"}, 909 {"RON", NULL, "RONMIX"}, 910}; 911 912static int wm8400_add_widgets(struct snd_soc_codec *codec) 913{ 914 snd_soc_dapm_new_controls(codec, wm8400_dapm_widgets, 915 ARRAY_SIZE(wm8400_dapm_widgets)); 916 917 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); 918 919 return 0; 920} 921 922/* 923 * Clock after FLL and dividers 924 */ 925static int wm8400_set_dai_sysclk(struct snd_soc_dai *codec_dai, 926 int clk_id, unsigned int freq, int dir) 927{ 928 struct snd_soc_codec *codec = codec_dai->codec; 929 struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec); 930 931 wm8400->sysclk = freq; 932 return 0; 933} 934 935struct fll_factors { 936 u16 n; 937 u16 k; 938 u16 outdiv; 939 u16 fratio; 940 u16 freq_ref; 941}; 942 943#define FIXED_FLL_SIZE ((1 << 16) * 10) 944 945static int fll_factors(struct wm8400_priv *wm8400, struct fll_factors *factors, 946 unsigned int Fref, unsigned int Fout) 947{ 948 u64 Kpart; 949 unsigned int K, Nmod, target; 950 951 factors->outdiv = 2; 952 while (Fout * factors->outdiv < 90000000 || 953 Fout * factors->outdiv > 100000000) { 954 factors->outdiv *= 2; 955 if (factors->outdiv > 32) { 956 dev_err(wm8400->wm8400->dev, 957 "Unsupported FLL output frequency %uHz\n", 958 Fout); 959 return -EINVAL; 960 } 961 } 962 target = Fout * factors->outdiv; 963 factors->outdiv = factors->outdiv >> 2; 964 965 if (Fref < 48000) 966 factors->freq_ref = 1; 967 else 968 factors->freq_ref = 0; 969 970 if (Fref < 1000000) 971 factors->fratio = 9; 972 else 973 factors->fratio = 0; 974 975 /* Ensure we have a fractional part */ 976 do { 977 if (Fref < 1000000) 978 factors->fratio--; 979 else 980 factors->fratio++; 981 982 if (factors->fratio < 1 || factors->fratio > 8) { 983 dev_err(wm8400->wm8400->dev, 984 "Unable to calculate FRATIO\n"); 985 return -EINVAL; 986 } 987 988 factors->n = target / (Fref * factors->fratio); 989 Nmod = target % (Fref * factors->fratio); 990 } while (Nmod == 0); 991 992 /* Calculate fractional part - scale up so we can round. */ 993 Kpart = FIXED_FLL_SIZE * (long long)Nmod; 994 995 do_div(Kpart, (Fref * factors->fratio)); 996 997 K = Kpart & 0xFFFFFFFF; 998 999 if ((K % 10) >= 5) 1000 K += 5; 1001 1002 /* Move down to proper range now rounding is done */ 1003 factors->k = K / 10; 1004 1005 dev_dbg(wm8400->wm8400->dev, 1006 "FLL: Fref=%u Fout=%u N=%x K=%x, FRATIO=%x OUTDIV=%x\n", 1007 Fref, Fout, 1008 factors->n, factors->k, factors->fratio, factors->outdiv); 1009 1010 return 0; 1011} 1012 1013static int wm8400_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id, 1014 int source, unsigned int freq_in, 1015 unsigned int freq_out) 1016{ 1017 struct snd_soc_codec *codec = codec_dai->codec; 1018 struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec); 1019 struct fll_factors factors; 1020 int ret; 1021 u16 reg; 1022 1023 if (freq_in == wm8400->fll_in && freq_out == wm8400->fll_out) 1024 return 0; 1025 1026 if (freq_out) { 1027 ret = fll_factors(wm8400, &factors, freq_in, freq_out); 1028 if (ret != 0) 1029 return ret; 1030 } else { 1031 /* Bodge GCC 4.4.0 uninitialised variable warning - it 1032 * doesn't seem capable of working out that we exit if 1033 * freq_out is 0 before any of the uses. */ 1034 memset(&factors, 0, sizeof(factors)); 1035 } 1036 1037 wm8400->fll_out = freq_out; 1038 wm8400->fll_in = freq_in; 1039 1040 /* We *must* disable the FLL before any changes */ 1041 reg = wm8400_read(codec, WM8400_POWER_MANAGEMENT_2); 1042 reg &= ~WM8400_FLL_ENA; 1043 wm8400_write(codec, WM8400_POWER_MANAGEMENT_2, reg); 1044 1045 reg = wm8400_read(codec, WM8400_FLL_CONTROL_1); 1046 reg &= ~WM8400_FLL_OSC_ENA; 1047 wm8400_write(codec, WM8400_FLL_CONTROL_1, reg); 1048 1049 if (!freq_out) 1050 return 0; 1051 1052 reg &= ~(WM8400_FLL_REF_FREQ | WM8400_FLL_FRATIO_MASK); 1053 reg |= WM8400_FLL_FRAC | factors.fratio; 1054 reg |= factors.freq_ref << WM8400_FLL_REF_FREQ_SHIFT; 1055 wm8400_write(codec, WM8400_FLL_CONTROL_1, reg); 1056 1057 wm8400_write(codec, WM8400_FLL_CONTROL_2, factors.k); 1058 wm8400_write(codec, WM8400_FLL_CONTROL_3, factors.n); 1059 1060 reg = wm8400_read(codec, WM8400_FLL_CONTROL_4); 1061 reg &= WM8400_FLL_OUTDIV_MASK; 1062 reg |= factors.outdiv; 1063 wm8400_write(codec, WM8400_FLL_CONTROL_4, reg); 1064 1065 return 0; 1066} 1067 1068/* 1069 * Sets ADC and Voice DAC format. 1070 */ 1071static int wm8400_set_dai_fmt(struct snd_soc_dai *codec_dai, 1072 unsigned int fmt) 1073{ 1074 struct snd_soc_codec *codec = codec_dai->codec; 1075 u16 audio1, audio3; 1076 1077 audio1 = wm8400_read(codec, WM8400_AUDIO_INTERFACE_1); 1078 audio3 = wm8400_read(codec, WM8400_AUDIO_INTERFACE_3); 1079 1080 /* set master/slave audio interface */ 1081 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1082 case SND_SOC_DAIFMT_CBS_CFS: 1083 audio3 &= ~WM8400_AIF_MSTR1; 1084 break; 1085 case SND_SOC_DAIFMT_CBM_CFM: 1086 audio3 |= WM8400_AIF_MSTR1; 1087 break; 1088 default: 1089 return -EINVAL; 1090 } 1091 1092 audio1 &= ~WM8400_AIF_FMT_MASK; 1093 1094 /* interface format */ 1095 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1096 case SND_SOC_DAIFMT_I2S: 1097 audio1 |= WM8400_AIF_FMT_I2S; 1098 audio1 &= ~WM8400_AIF_LRCLK_INV; 1099 break; 1100 case SND_SOC_DAIFMT_RIGHT_J: 1101 audio1 |= WM8400_AIF_FMT_RIGHTJ; 1102 audio1 &= ~WM8400_AIF_LRCLK_INV; 1103 break; 1104 case SND_SOC_DAIFMT_LEFT_J: 1105 audio1 |= WM8400_AIF_FMT_LEFTJ; 1106 audio1 &= ~WM8400_AIF_LRCLK_INV; 1107 break; 1108 case SND_SOC_DAIFMT_DSP_A: 1109 audio1 |= WM8400_AIF_FMT_DSP; 1110 audio1 &= ~WM8400_AIF_LRCLK_INV; 1111 break; 1112 case SND_SOC_DAIFMT_DSP_B: 1113 audio1 |= WM8400_AIF_FMT_DSP | WM8400_AIF_LRCLK_INV; 1114 break; 1115 default: 1116 return -EINVAL; 1117 } 1118 1119 wm8400_write(codec, WM8400_AUDIO_INTERFACE_1, audio1); 1120 wm8400_write(codec, WM8400_AUDIO_INTERFACE_3, audio3); 1121 return 0; 1122} 1123 1124static int wm8400_set_dai_clkdiv(struct snd_soc_dai *codec_dai, 1125 int div_id, int div) 1126{ 1127 struct snd_soc_codec *codec = codec_dai->codec; 1128 u16 reg; 1129 1130 switch (div_id) { 1131 case WM8400_MCLK_DIV: 1132 reg = wm8400_read(codec, WM8400_CLOCKING_2) & 1133 ~WM8400_MCLK_DIV_MASK; 1134 wm8400_write(codec, WM8400_CLOCKING_2, reg | div); 1135 break; 1136 case WM8400_DACCLK_DIV: 1137 reg = wm8400_read(codec, WM8400_CLOCKING_2) & 1138 ~WM8400_DAC_CLKDIV_MASK; 1139 wm8400_write(codec, WM8400_CLOCKING_2, reg | div); 1140 break; 1141 case WM8400_ADCCLK_DIV: 1142 reg = wm8400_read(codec, WM8400_CLOCKING_2) & 1143 ~WM8400_ADC_CLKDIV_MASK; 1144 wm8400_write(codec, WM8400_CLOCKING_2, reg | div); 1145 break; 1146 case WM8400_BCLK_DIV: 1147 reg = wm8400_read(codec, WM8400_CLOCKING_1) & 1148 ~WM8400_BCLK_DIV_MASK; 1149 wm8400_write(codec, WM8400_CLOCKING_1, reg | div); 1150 break; 1151 default: 1152 return -EINVAL; 1153 } 1154 1155 return 0; 1156} 1157 1158/* 1159 * Set PCM DAI bit size and sample rate. 1160 */ 1161static int wm8400_hw_params(struct snd_pcm_substream *substream, 1162 struct snd_pcm_hw_params *params, 1163 struct snd_soc_dai *dai) 1164{ 1165 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1166 struct snd_soc_device *socdev = rtd->socdev; 1167 struct snd_soc_codec *codec = socdev->card->codec; 1168 u16 audio1 = wm8400_read(codec, WM8400_AUDIO_INTERFACE_1); 1169 1170 audio1 &= ~WM8400_AIF_WL_MASK; 1171 /* bit size */ 1172 switch (params_format(params)) { 1173 case SNDRV_PCM_FORMAT_S16_LE: 1174 break; 1175 case SNDRV_PCM_FORMAT_S20_3LE: 1176 audio1 |= WM8400_AIF_WL_20BITS; 1177 break; 1178 case SNDRV_PCM_FORMAT_S24_LE: 1179 audio1 |= WM8400_AIF_WL_24BITS; 1180 break; 1181 case SNDRV_PCM_FORMAT_S32_LE: 1182 audio1 |= WM8400_AIF_WL_32BITS; 1183 break; 1184 } 1185 1186 wm8400_write(codec, WM8400_AUDIO_INTERFACE_1, audio1); 1187 return 0; 1188} 1189 1190static int wm8400_mute(struct snd_soc_dai *dai, int mute) 1191{ 1192 struct snd_soc_codec *codec = dai->codec; 1193 u16 val = wm8400_read(codec, WM8400_DAC_CTRL) & ~WM8400_DAC_MUTE; 1194 1195 if (mute) 1196 wm8400_write(codec, WM8400_DAC_CTRL, val | WM8400_DAC_MUTE); 1197 else 1198 wm8400_write(codec, WM8400_DAC_CTRL, val); 1199 1200 return 0; 1201} 1202 1203/* TODO: set bias for best performance at standby */ 1204static int wm8400_set_bias_level(struct snd_soc_codec *codec, 1205 enum snd_soc_bias_level level) 1206{ 1207 struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec); 1208 u16 val; 1209 int ret; 1210 1211 switch (level) { 1212 case SND_SOC_BIAS_ON: 1213 break; 1214 1215 case SND_SOC_BIAS_PREPARE: 1216 /* VMID=2*50k */ 1217 val = wm8400_read(codec, WM8400_POWER_MANAGEMENT_1) & 1218 ~WM8400_VMID_MODE_MASK; 1219 wm8400_write(codec, WM8400_POWER_MANAGEMENT_1, val | 0x2); 1220 break; 1221 1222 case SND_SOC_BIAS_STANDBY: 1223 if (codec->bias_level == SND_SOC_BIAS_OFF) { 1224 ret = regulator_bulk_enable(ARRAY_SIZE(power), 1225 &power[0]); 1226 if (ret != 0) { 1227 dev_err(wm8400->wm8400->dev, 1228 "Failed to enable regulators: %d\n", 1229 ret); 1230 return ret; 1231 } 1232 1233 wm8400_write(codec, WM8400_POWER_MANAGEMENT_1, 1234 WM8400_CODEC_ENA | WM8400_SYSCLK_ENA); 1235 1236 /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */ 1237 wm8400_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST | 1238 WM8400_BUFDCOPEN | WM8400_POBCTRL); 1239 1240 msleep(50); 1241 1242 /* Enable VREF & VMID at 2x50k */ 1243 val = wm8400_read(codec, WM8400_POWER_MANAGEMENT_1); 1244 val |= 0x2 | WM8400_VREF_ENA; 1245 wm8400_write(codec, WM8400_POWER_MANAGEMENT_1, val); 1246 1247 /* Enable BUFIOEN */ 1248 wm8400_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST | 1249 WM8400_BUFDCOPEN | WM8400_POBCTRL | 1250 WM8400_BUFIOEN); 1251 1252 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */ 1253 wm8400_write(codec, WM8400_ANTIPOP2, WM8400_BUFIOEN); 1254 } 1255 1256 /* VMID=2*300k */ 1257 val = wm8400_read(codec, WM8400_POWER_MANAGEMENT_1) & 1258 ~WM8400_VMID_MODE_MASK; 1259 wm8400_write(codec, WM8400_POWER_MANAGEMENT_1, val | 0x4); 1260 break; 1261 1262 case SND_SOC_BIAS_OFF: 1263 /* Enable POBCTRL and SOFT_ST */ 1264 wm8400_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST | 1265 WM8400_POBCTRL | WM8400_BUFIOEN); 1266 1267 /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */ 1268 wm8400_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST | 1269 WM8400_BUFDCOPEN | WM8400_POBCTRL | 1270 WM8400_BUFIOEN); 1271 1272 /* mute DAC */ 1273 val = wm8400_read(codec, WM8400_DAC_CTRL); 1274 wm8400_write(codec, WM8400_DAC_CTRL, val | WM8400_DAC_MUTE); 1275 1276 /* Enable any disabled outputs */ 1277 val = wm8400_read(codec, WM8400_POWER_MANAGEMENT_1); 1278 val |= WM8400_SPK_ENA | WM8400_OUT3_ENA | 1279 WM8400_OUT4_ENA | WM8400_LOUT_ENA | 1280 WM8400_ROUT_ENA; 1281 wm8400_write(codec, WM8400_POWER_MANAGEMENT_1, val); 1282 1283 /* Disable VMID */ 1284 val &= ~WM8400_VMID_MODE_MASK; 1285 wm8400_write(codec, WM8400_POWER_MANAGEMENT_1, val); 1286 1287 msleep(300); 1288 1289 /* Enable all output discharge bits */ 1290 wm8400_write(codec, WM8400_ANTIPOP1, WM8400_DIS_LLINE | 1291 WM8400_DIS_RLINE | WM8400_DIS_OUT3 | 1292 WM8400_DIS_OUT4 | WM8400_DIS_LOUT | 1293 WM8400_DIS_ROUT); 1294 1295 /* Disable VREF */ 1296 val &= ~WM8400_VREF_ENA; 1297 wm8400_write(codec, WM8400_POWER_MANAGEMENT_1, val); 1298 1299 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */ 1300 wm8400_write(codec, WM8400_ANTIPOP2, 0x0); 1301 1302 ret = regulator_bulk_disable(ARRAY_SIZE(power), 1303 &power[0]); 1304 if (ret != 0) 1305 return ret; 1306 1307 break; 1308 } 1309 1310 codec->bias_level = level; 1311 return 0; 1312} 1313 1314#define WM8400_RATES SNDRV_PCM_RATE_8000_96000 1315 1316#define WM8400_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 1317 SNDRV_PCM_FMTBIT_S24_LE) 1318 1319static struct snd_soc_dai_ops wm8400_dai_ops = { 1320 .hw_params = wm8400_hw_params, 1321 .digital_mute = wm8400_mute, 1322 .set_fmt = wm8400_set_dai_fmt, 1323 .set_clkdiv = wm8400_set_dai_clkdiv, 1324 .set_sysclk = wm8400_set_dai_sysclk, 1325 .set_pll = wm8400_set_dai_pll, 1326}; 1327 1328/* 1329 * The WM8400 supports 2 different and mutually exclusive DAI 1330 * configurations. 1331 * 1332 * 1. ADC/DAC on Primary Interface 1333 * 2. ADC on Primary Interface/DAC on secondary 1334 */ 1335struct snd_soc_dai wm8400_dai = { 1336/* ADC/DAC on primary */ 1337 .name = "WM8400 ADC/DAC Primary", 1338 .id = 1, 1339 .playback = { 1340 .stream_name = "Playback", 1341 .channels_min = 1, 1342 .channels_max = 2, 1343 .rates = WM8400_RATES, 1344 .formats = WM8400_FORMATS, 1345 }, 1346 .capture = { 1347 .stream_name = "Capture", 1348 .channels_min = 1, 1349 .channels_max = 2, 1350 .rates = WM8400_RATES, 1351 .formats = WM8400_FORMATS, 1352 }, 1353 .ops = &wm8400_dai_ops, 1354}; 1355EXPORT_SYMBOL_GPL(wm8400_dai); 1356 1357static int wm8400_suspend(struct platform_device *pdev, pm_message_t state) 1358{ 1359 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1360 struct snd_soc_codec *codec = socdev->card->codec; 1361 1362 wm8400_set_bias_level(codec, SND_SOC_BIAS_OFF); 1363 1364 return 0; 1365} 1366 1367static int wm8400_resume(struct platform_device *pdev) 1368{ 1369 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1370 struct snd_soc_codec *codec = socdev->card->codec; 1371 1372 wm8400_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1373 1374 return 0; 1375} 1376 1377static struct snd_soc_codec *wm8400_codec; 1378 1379static int wm8400_probe(struct platform_device *pdev) 1380{ 1381 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1382 struct snd_soc_codec *codec; 1383 int ret; 1384 1385 if (!wm8400_codec) { 1386 dev_err(&pdev->dev, "wm8400 not yet discovered\n"); 1387 return -ENODEV; 1388 } 1389 codec = wm8400_codec; 1390 1391 socdev->card->codec = codec; 1392 1393 /* register pcms */ 1394 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); 1395 if (ret < 0) { 1396 dev_err(&pdev->dev, "failed to create pcms\n"); 1397 goto pcm_err; 1398 } 1399 1400 wm8400_add_controls(codec); 1401 wm8400_add_widgets(codec); 1402 1403pcm_err: 1404 return ret; 1405} 1406 1407/* power down chip */ 1408static int wm8400_remove(struct platform_device *pdev) 1409{ 1410 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1411 1412 snd_soc_free_pcms(socdev); 1413 snd_soc_dapm_free(socdev); 1414 1415 return 0; 1416} 1417 1418struct snd_soc_codec_device soc_codec_dev_wm8400 = { 1419 .probe = wm8400_probe, 1420 .remove = wm8400_remove, 1421 .suspend = wm8400_suspend, 1422 .resume = wm8400_resume, 1423}; 1424 1425static void wm8400_probe_deferred(struct work_struct *work) 1426{ 1427 struct wm8400_priv *priv = container_of(work, struct wm8400_priv, 1428 work); 1429 struct snd_soc_codec *codec = &priv->codec; 1430 int ret; 1431 1432 /* charge output caps */ 1433 wm8400_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1434 1435 /* We're done, tell the subsystem. */ 1436 ret = snd_soc_register_codec(codec); 1437 if (ret != 0) { 1438 dev_err(priv->wm8400->dev, 1439 "Failed to register codec: %d\n", ret); 1440 goto err; 1441 } 1442 1443 ret = snd_soc_register_dai(&wm8400_dai); 1444 if (ret != 0) { 1445 dev_err(priv->wm8400->dev, 1446 "Failed to register DAI: %d\n", ret); 1447 goto err_codec; 1448 } 1449 1450 return; 1451 1452err_codec: 1453 snd_soc_unregister_codec(codec); 1454err: 1455 wm8400_set_bias_level(codec, SND_SOC_BIAS_OFF); 1456} 1457 1458static int wm8400_codec_probe(struct platform_device *dev) 1459{ 1460 struct wm8400_priv *priv; 1461 int ret; 1462 u16 reg; 1463 struct snd_soc_codec *codec; 1464 1465 priv = kzalloc(sizeof(struct wm8400_priv), GFP_KERNEL); 1466 if (priv == NULL) 1467 return -ENOMEM; 1468 1469 codec = &priv->codec; 1470 snd_soc_codec_set_drvdata(codec, priv); 1471 codec->control_data = dev_get_drvdata(&dev->dev); 1472 priv->wm8400 = dev_get_drvdata(&dev->dev); 1473 1474 ret = regulator_bulk_get(priv->wm8400->dev, 1475 ARRAY_SIZE(power), &power[0]); 1476 if (ret != 0) { 1477 dev_err(&dev->dev, "Failed to get regulators: %d\n", ret); 1478 goto err; 1479 } 1480 1481 codec->dev = &dev->dev; 1482 wm8400_dai.dev = &dev->dev; 1483 1484 codec->name = "WM8400"; 1485 codec->owner = THIS_MODULE; 1486 codec->read = wm8400_read; 1487 codec->write = wm8400_write; 1488 codec->bias_level = SND_SOC_BIAS_OFF; 1489 codec->set_bias_level = wm8400_set_bias_level; 1490 codec->dai = &wm8400_dai; 1491 codec->num_dai = 1; 1492 codec->reg_cache_size = WM8400_REGISTER_COUNT; 1493 mutex_init(&codec->mutex); 1494 INIT_LIST_HEAD(&codec->dapm_widgets); 1495 INIT_LIST_HEAD(&codec->dapm_paths); 1496 INIT_WORK(&priv->work, wm8400_probe_deferred); 1497 1498 wm8400_codec_reset(codec); 1499 1500 reg = wm8400_read(codec, WM8400_POWER_MANAGEMENT_1); 1501 wm8400_write(codec, WM8400_POWER_MANAGEMENT_1, reg | WM8400_CODEC_ENA); 1502 1503 /* Latch volume update bits */ 1504 reg = wm8400_read(codec, WM8400_LEFT_LINE_INPUT_1_2_VOLUME); 1505 wm8400_write(codec, WM8400_LEFT_LINE_INPUT_1_2_VOLUME, 1506 reg & WM8400_IPVU); 1507 reg = wm8400_read(codec, WM8400_RIGHT_LINE_INPUT_1_2_VOLUME); 1508 wm8400_write(codec, WM8400_RIGHT_LINE_INPUT_1_2_VOLUME, 1509 reg & WM8400_IPVU); 1510 1511 wm8400_write(codec, WM8400_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8)); 1512 wm8400_write(codec, WM8400_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8)); 1513 1514 wm8400_codec = codec; 1515 1516 if (!schedule_work(&priv->work)) { 1517 ret = -EINVAL; 1518 goto err_regulator; 1519 } 1520 1521 return 0; 1522 1523err_regulator: 1524 wm8400_codec = NULL; 1525 regulator_bulk_free(ARRAY_SIZE(power), power); 1526err: 1527 kfree(priv); 1528 return ret; 1529} 1530 1531static int __exit wm8400_codec_remove(struct platform_device *dev) 1532{ 1533 struct wm8400_priv *priv = snd_soc_codec_get_drvdata(wm8400_codec); 1534 u16 reg; 1535 1536 snd_soc_unregister_dai(&wm8400_dai); 1537 snd_soc_unregister_codec(wm8400_codec); 1538 1539 reg = wm8400_read(wm8400_codec, WM8400_POWER_MANAGEMENT_1); 1540 wm8400_write(wm8400_codec, WM8400_POWER_MANAGEMENT_1, 1541 reg & (~WM8400_CODEC_ENA)); 1542 1543 regulator_bulk_free(ARRAY_SIZE(power), power); 1544 kfree(priv); 1545 1546 wm8400_codec = NULL; 1547 1548 return 0; 1549} 1550 1551static struct platform_driver wm8400_codec_driver = { 1552 .driver = { 1553 .name = "wm8400-codec", 1554 .owner = THIS_MODULE, 1555 }, 1556 .probe = wm8400_codec_probe, 1557 .remove = __exit_p(wm8400_codec_remove), 1558}; 1559 1560static int __init wm8400_codec_init(void) 1561{ 1562 return platform_driver_register(&wm8400_codec_driver); 1563} 1564module_init(wm8400_codec_init); 1565 1566static void __exit wm8400_codec_exit(void) 1567{ 1568 platform_driver_unregister(&wm8400_codec_driver); 1569} 1570module_exit(wm8400_codec_exit); 1571 1572EXPORT_SYMBOL_GPL(soc_codec_dev_wm8400); 1573 1574MODULE_DESCRIPTION("ASoC WM8400 driver"); 1575MODULE_AUTHOR("Mark Brown"); 1576MODULE_LICENSE("GPL"); 1577MODULE_ALIAS("platform:wm8400-codec"); 1578